WO2015100836A1 - 薄膜晶体管阵列基板、液晶显示面板及液晶显示面板的修复方法 - Google Patents

薄膜晶体管阵列基板、液晶显示面板及液晶显示面板的修复方法 Download PDF

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Publication number
WO2015100836A1
WO2015100836A1 PCT/CN2014/071860 CN2014071860W WO2015100836A1 WO 2015100836 A1 WO2015100836 A1 WO 2015100836A1 CN 2014071860 W CN2014071860 W CN 2014071860W WO 2015100836 A1 WO2015100836 A1 WO 2015100836A1
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Prior art keywords
lines
line
growth
thin film
film transistor
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English (en)
French (fr)
Inventor
阙祥灯
蓝世才
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/777,139 priority Critical patent/US9897878B2/en
Publication of WO2015100836A1 publication Critical patent/WO2015100836A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to a Thin Film Transistor Array (TFT) array substrate, a liquid crystal display panel having the same, and a liquid crystal display panel.
  • TFT Thin Film Transistor Array
  • the liquid crystal display panel is generally driven by an active thin film transistor array, and each pixel on the thin film transistor array substrate needs to be connected with the cross-hatching scan lines and data lines for selecting and inputting display voltages. Since the existing thin film transistor array substrate has up to several million pixels, nearly 10,000 scan lines and data lines are required. When a thin film transistor array substrate is fabricated, the resulting thin film transistor array substrate inevitably has point defects or line defects. At present, the industry's usual method for repairing point defects is to cut off the signal of the TFT to the transparent conductive film (indium tin metal oxide), and simultaneously short-circuit the transparent conductive film and the common com line to repair the bright spot. In the normally dark state, this process requires the growth of a common electrode line.
  • the transparent conductive film indium tin metal oxide
  • the repair of wire defects in the industry is usually done by repairing the wiring, and it is also necessary to grow the common electrode wire.
  • the repair of the point defects and the repair of the line defects are generally performed independently in the industry, not only the wiring structure is complicated, but also the distance of the required growth lines is also Longer, this will reduce the aperture ratio of the liquid crystal display panel.
  • the present invention provides a thin film transistor array substrate comprising a plurality of data lines parallel to each other and extending in a first direction, a plurality of lines extending parallel to each other and extending in a second direction perpendicular to the first direction a scan line, a plurality of pixels defined by the plurality of data lines and the plurality of scan lines, and a common electrode having a main line and a plurality of growth lines.
  • the main line is parallel to the plurality of scan lines, and the growth line extends perpendicularly from the main line.
  • Each pixel includes a pixel electrode and a thin film crystal Body tube, part of the main line and two growth lines.
  • the thin film transistor is electrically connected to the pixel electrode, the corresponding data line, and the corresponding scan line.
  • the projections of the two growth lines overlap the pixel electrode.
  • Each pixel is provided with a common area that overlaps the growth line.
  • the common area is configured to be punctured to electrically connect the pixel electrode to a corresponding growth line, and to be electrically connected to another punctured common area adjacent to the second direction after being punctured
  • the growth lines corresponding to the two shared regions are electrically connected.
  • two growth lines in each pixel extend perpendicularly from opposite ends of the corresponding main line, and each growth line is in the same line as the nearest growth line in the pixel adjacent in the first direction. on.
  • the thin film transistor array substrate further includes a shielding metal
  • the shielding metal includes a plurality of first shielding regions, a plurality of second shielding regions, and the plurality of common regions, and the plurality of first shielding regions and growth on the plurality of straight lines Corresponding to and spaced apart from the data line, the plurality of second shielding regions corresponding to the plurality of pixels, and respectively located in a region of the pixel electrode in the corresponding pixel, each of the second shielding regions passing through the shared region and the two ends A shielded area is connected.
  • the second shielding area in each pixel comprises two segments crisscrossed or includes a segment along the second direction.
  • the common area is a part of the main line, and the two growth lines extend perpendicularly from opposite sides of the common area.
  • the shape of the common area is a circle, a triangle, a quadrangle or other polygons.
  • the pixel electrode is formed of a transparent conductive film.
  • the plurality of scan lines are made of a first metal layer for transmitting a scan signal
  • the common electrode is made of a first metal layer
  • the plurality of data lines are made of a second metal layer, Transmit data signals.
  • the present invention also provides a liquid crystal display panel comprising the thin film transistor array substrate as described above.
  • two growth lines in each pixel extend perpendicularly from opposite ends of the corresponding main line, and each growth line is in the same line as the nearest growth line in the pixel adjacent in the first direction. on.
  • the thin film transistor array substrate further includes a shielding metal
  • the shielding metal includes a plurality of first shielding regions, a plurality of second shielding regions, and the plurality of common regions, and the plurality of first shielding regions and growth on the plurality of straight lines
  • the line corresponds to and is spaced apart from the data line
  • the plurality of second shielding areas correspond to the plurality of pixels.
  • each of the second shielding regions is connected to the first shielding region at both ends through the common region.
  • the second shielding area in each pixel comprises two segments crisscrossed or includes a segment along the second direction.
  • the common area is a part of the main line, and the two growth lines extend perpendicularly from opposite sides of the common area.
  • the shape of the common area is a circle, a triangle, a quadrangle or other polygons.
  • the pixel electrode is formed of a transparent conductive film.
  • the plurality of scan lines are made of a first metal layer for transmitting a scan signal
  • the common electrode is made of a first metal layer
  • the plurality of data lines are made of a second metal layer, Transmit data signals.
  • the present invention also provides a method of repairing a liquid crystal display panel for repairing point defects and line defects on a thin film transistor array substrate as described above.
  • the method for repairing a liquid crystal panel includes: when a pixel has a dot defect, cutting a signal of the thin film transistor in the pixel to the pixel electrode in the pixel, and performing the laser drilling on the common region in the pixel
  • the pixel electrode is short-circuited with the growth line overlapping therewith; and when the main line has a wire break defect at the intersection with the data line, the main line passes through the two common areas in the two pixels located along the second direction
  • the laser is perforated and metallized in the hole and a metal wire is placed between the two holes to electrically connect the growth lines corresponding to the two common regions.
  • the repairing method of the liquid crystal display panel further includes: when the main line and the data line are short-circuited at the intersection, first cutting off the main line at the intersection to eliminate the short-circuit between the main line and the data line at the intersection, and then The main line is laser-punched on two common areas in the two pixels in the second direction, and finally metal is plated in the two holes and a metal wire is placed between the two holes to make the two The growth lines corresponding to the common areas are electrically connected.
  • the thin film transistor array substrate, the liquid crystal display panel and the liquid crystal panel repairing method provided by the invention are all provided with a common area, and the point area is repaired and the line defect is repaired simultaneously by using the shared area, and the wiring structure is simple, and the used structure is used.
  • the growth line is shorter than the growth line used to repair the point defect and the line defect, which effectively reduces the aperture ratio of the liquid crystal display panel.
  • FIG. 1 is a schematic view of a thin film transistor array substrate according to a first embodiment of the present invention
  • FIG. 2 is a schematic view of a thin film transistor array substrate according to a third embodiment of the present invention.
  • a thin film transistor array substrate 100 includes a plurality of data lines and a plurality of scanning lines that are vertically and horizontally staggered.
  • the present embodiment is described by taking the thin film transistor array substrate 100 as three data lines G1, G2, and G3 and two scanning lines S1 and S2 as an example.
  • the three data lines G1, G2, and G3 are parallel to each other and extend in a first direction (horizontal direction), and the two scanning lines S1 and S2 are parallel to each other and extend in a second direction (vertical direction).
  • the thin film transistor array substrate 100 further includes a common electrode 10, four pixels P11, P12, P21, and P22 defined by the three data lines G1, G2, and G3 and the two scan lines S1 and S2 being vertically and horizontally staggered with each other. Shield metal 30.
  • the two scan lines S1 and S2 are made of a first metal layer for transmitting a scan signal.
  • the common electrode 10 is also made of a first metal layer.
  • the three data lines G1, G2, and G3 are made of a second metal layer for transmitting data signals.
  • the first metal layer and the second metal layer are separated by a silicon nitride insulating layer.
  • the common electrode 10 includes a main line 12 and eight growth lines 14.
  • the main line 12 is located between the two scanning lines S1 and S2 and is parallel to the two scanning lines S1 and S2. That is, the main line 12 also extends in the second direction.
  • the four pixels P11, P12, P21 and P22 are evenly distributed on opposite sides of the main line 12.
  • the eight growth lines 14 are respectively distributed on both sides of the back side of the main line 12, and each of the pixels P11, P12, P21 and P22 has two growth lines 14 in the region.
  • Each of the pixels P11, P12, P21 and P22 includes a pixel electrode 22, a thin film transistor 24, Part of the main line 12 and two growth lines 14.
  • the pixel electrode 22 is formed of a transparent conductive film, and the specific material is indium tin metal oxide.
  • the gate of the thin film transistor 24 is electrically connected to the scan line S2 (only the pixel P1 2 is taken as an example), and the source is electrically connected to the data line G1 (only the pixel P1 2 is taken as an example), and the drain and the pixel are connected.
  • the electrodes 22 are electrically connected.
  • the two growth lines 14 each extend perpendicularly from opposite ends of the corresponding partial trunk line 12, and each growth line 14 is identical to the nearest neighbor growth line 14 in the pixel P11 adjacent in the first direction. On the straight line, the eight growth lines 14 form a total of four straight lines in the first direction. The projections of the two growth lines 14 overlap the pixel electrode 22.
  • the shield metal 30 includes four first shield regions 32, four second shield regions 34, and eight common regions 36.
  • the projections of the four first shielding regions 32 overlap with the growth lines 14 on the four straight lines, and the four first shielding regions 32 are adjacent to and spaced apart from the three data lines G1, G2, and G3, respectively.
  • the four second shielding regions 34 correspond to the four pixels P11, P12, P21, and P22, and are respectively located in the regions where the pixel electrodes 22 of the corresponding pixels P11, P12, P21, and P22 are located.
  • the second shielding region 34 of the pixels P12 and P22 includes two segments crisscrossed, and the second shielding region 34 of the pixels P11 and P21 includes only a segment along the second direction.
  • Two common regions 36 are distributed in each of the pixels P11, P12, P21 and P22, and the two common regions 36 extend from the two first shielding regions 32 in the respective pixels P11, P12, P21 and P22.
  • Each of the second shield regions 34 is connected to the first shield regions 32 at both ends through the two common regions 36.
  • the common area 36 is a triangle.
  • the common area 36 is not limited to a triangle in this embodiment, and may be a circle, a quadrangle or other polygons, and may have a regular or irregular shape.
  • the size of the shared area 36 is not limited as long as it is satisfied.
  • Each of the second shielding regions 34 can be connected to the first shielding regions 32 at both ends through the two common regions 36.
  • the second shielding regions 34 of each of the pixels P11, P12, P21, and P22 may all be two segments including criss-crossing, or all of them may include only one segment along the second direction. It can be any combination of the above two structures.
  • a liquid crystal panel repairing method for repairing point defects and line defects on the thin film transistor array substrate 100 as described in the first embodiment includes:
  • the signal of the thin film transistor 24 in the pixel P12 to the pixel electrode 22 in the pixel P12 is cut off, and one of the common regions 36 in the pixel P12 is For example, the common electrode region 36 at B1 is short-circuited by the laser perforation welding to the growth line 14 overlapping the pixel electrode 22, thereby repairing the bright spot in P12 to a normally dark state.
  • the two main areas 36 ie, B1 in the two pixels P12 and P22 where the main line 12 is located along the second direction
  • the common area 36 and the common area 36) at B2 are all laser-punched, and metal is plated in the two holes and a metal line is placed between the two holes to make the growth line corresponding to the two common areas 36. 14 electrical connection.
  • a silicon nitride insulating hole at the intersection of the main line 12 and the data line G2 (at the A) causes a short circuit, or a short circuit occurs when the main line 12 and the data line G2 at the intersection (at the point A) are electrostatically damaged.
  • the main line 12 of the intersection (at the A) is first cut to eliminate the short circuit of the intersection line (at the A) and the data line G2, and then the main line 12 is along the second direction.
  • the two common regions 36 in the two pixels P12 and P22 are laser-punched, and finally metallized in two holes and in two Metal wires are placed between the holes to electrically connect the growth wires 14 corresponding to the two common regions 36.
  • a thin film transistor array substrate 200 includes a plurality of data lines and a plurality of scanning lines which are criss-crossed with each other.
  • the present embodiment is described by taking the thin film transistor array substrate 200 as three examples of three data lines G1, G2, and G3 and two scanning lines S1 and S2.
  • the three data lines G1, G2, and G3 are parallel to each other and extend in a first direction (vertical direction), and the two scanning lines S1 and S2 are parallel to each other and extend in a second direction (horizontal direction).
  • the thin film transistor array substrate 100 further includes a common electrode 40, two pixels P11 and P12 defined by the three data lines G1, G2, and G3 and the two scanning lines S1 and S2 being vertically and horizontally staggered.
  • the two scan lines S1 and S2 are made of a first metal layer for transmitting a scan signal.
  • the common electrode 40 is also made of a first metal layer.
  • the three data lines G1, G2, and G3 are made of a second metal layer for transmitting data signals.
  • the first metal layer and the second metal layer are separated by a silicon nitride insulating layer.
  • the common electrode 40 includes a main line 42 and four growth lines 44.
  • the main line 42 is located between the two scanning lines S1 and S2 and is parallel to the two scanning lines S1 and S2. That is, the main line 42 also extends in the second direction.
  • the main line 42 passes through the two pixels P11 and P12.
  • the four growth lines 44 are evenly distributed on opposite sides of the main line 42, and each of the pixels P11 and P12 has two growth lines 44.
  • Each of the pixels P11 and P12 includes a pixel electrode 52 and a thin film transistor 54, a partial main line 42 and two growth lines 44.
  • the pixel electrode 52 is formed of a transparent conductive film, and the specific material is indium tin metal oxide.
  • the gate of the thin film transistor 54 and the scan line S2 (only pixel P12)
  • the source is electrically connected to the data line G2 (only the pixel P12 is taken as an example), and the drain is electrically connected to the pixel electrode 52.
  • a common area A is defined on the portion of the main line 42, and the two growth lines 44 each extend perpendicularly from opposite sides of the common area A (the area indicated by the triangle).
  • the projections of the two growth lines 44 overlap the pixel electrode 52.
  • the structure of the pixel P11 is exactly the same as that of the pixel P12, and details are not described herein again.
  • the common area A is not limited to a triangle in this embodiment, and may be a circle, a quadrangle or other polygons, and a regular or irregular shape may be used, and the size of the common area A is not limited.
  • a liquid crystal panel repairing method for repairing point defects and line defects on the thin film transistor array substrate 200 as described in the third embodiment includes:
  • the signal of the thin film transistor 54 in the pixel P12 to the pixel electrode 52 in the pixel P12 is cut, and the laser is passed through the common area A in the pixel P12.
  • the method of punching and soldering causes the pixel electrode 52 to be short-circuited with the main line 42 overlapping therewith, thereby repairing the bright spot in P12 to a normally dark state.
  • the main line 42 When the main line 42 has a broken line between the two common areas A in the pixels P11 and P12, the two common areas A are laser-punched, and the two holes are plated with metal and placed between the two holes.
  • the upper metal line is electrically connected to the growth line 44 corresponding to the two common areas A.
  • the present invention also provides a liquid crystal display panel comprising the thin film transistor array substrate 100 as described in the first embodiment or the thin film transistor array substrate 200 as described in the third embodiment, which will not be described in detail herein.
  • the thin film transistor array substrates 100 and 200, the liquid crystal display panel and the liquid crystal panel repairing method provided by the present invention are all provided with a common area 36 or a common area A, and the point area repair and line are simultaneously completed by using the shared area 36 or the shared area A. Repair of defects, not only the wiring structure is simple, but also The growth line used is shorter than the growth line used to repair the two defects independently, thus effectively reducing the aperture ratio of the liquid crystal display panel.

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Abstract

一种薄膜晶体管阵列基板（100、200）、液晶显示面板及其修复方法。薄膜晶体管阵列基板（100、200）包括均朝第一方向延伸的多条数据线（G1、G2、G3）、均朝与第一方向垂直的第二方向延伸的多条扫描线（S1、S2）、由数据线（G1、G2、G3）及扫描线（S1、S2）定义的多个像素（P11、P12、P21、P22）及具主干线（12）及生长线（14）的公共电极（10）。主干线（12）与扫描线（S1、S2）平行，生长线（14）自主干线（12）垂直延伸。每个像素（P11、P12、P21、P22）包括像素电极（22）、薄膜晶体管（24）、部分主干线（12）及两条生长线（14）。薄膜晶体管（24）与像素电极（22）、数据线（G1、G2、G3）及扫描线（S1、S2）均电性连接。两条生长线（14）的投影与像素电极（22）有交叠。每个像素（P11、P12、P21、P22）均设置有与生长线（14）有交叠的共用区域（36）。共用区域（36）用于被打穿以使像素电极（22）与生长线（14）电性连接，及用于被打穿后与在第二方向上相邻的另一被打穿的共用区域（36）电性连接以使与两个共用区域（36）对应的生长线（14）电性连接。

Description

薄膜晶体管阵列基板、 液晶显示面板及液晶显示面板的修复方法 技术领域
本发明涉及液晶显示器领域， 尤其涉及一种薄膜晶体管 (Thin Film Transistor Array, TFT)阵列基板、一种具有该薄膜晶体管阵列基板的液晶显示面板及一种液 晶显示面板的修复方法。 背景技术
液晶显示面板一般釆用主动式薄膜晶体管阵列进行驱动， 薄膜晶体管阵列 基板上的每个像素需要连接纵横交错的扫描线及数据线进行选中及输入显示电 压的操作。 因现有的薄膜晶体管阵列基板的像素多达几百万， 所需要的扫描线 及数据线也近万条。 在制作薄膜晶体管阵列基板时， 最终制作完成的薄膜晶体 管阵列基板难免会存在点缺陷或线缺陷。 目前， 业界对点缺陷的修复通常的做 法是切断 TFT给入透明导电薄膜 (铟锡金属氧化物)的信号， 同时将透明导电薄 膜和公共电极线 (com line)短路， 从而将亮点处修复成常暗状态， 此过程需要生 长公共电极线。 业界对线缺陷的修复通常是釆用修补配线的方式来完成， 其中 也需要生长公共电极线。 然而， 一旦薄膜晶体管阵列基板中同时存在上述的点 缺陷及线缺陷， 业界通常对点缺陷的修复及线缺陷的修复都是独立进行， 不仅 布线结构复杂， 而且所需要的生长的线的距离也较长， 如此便会降低液晶显示 面板的开口率。
因此， 有必要提供能够解决上述问题的薄膜晶体管阵列基板、 液晶显示面 板及液晶显示面板的 4爹复方法。 发明内容
为了解决上述技术问题， 本发明提供了一种薄膜晶体管阵列基板， 包括多 条彼此相互平行并朝第一方向延伸的数据线、 多条彼此相互平行并朝与第一方 向垂直的第二方向延伸的扫描线、 由该多条数据线及该多条扫描线定义的多个 像素及具有一条主干线及多条生长线的公共电极。 该主干线与该多条扫描线平 行， 该生长线自该主干线垂直延伸。 每个像素包括一个像素电极、 一个薄膜晶 体管、 部分主干线以及两条生长线。 该薄膜晶体管与该像素电极、 对应的数据 线及对应的扫描线均电性连接。 该两条生长线的投影与该像素电极有交叠。 每 个像素均设置有共用区域， 该共用区域与该生长线有交叠。 该共用区域用于被 打穿以使该像素电极与对应的生长线电性连接， 及用于被打穿后与在该第二方 向上相邻的另一被打穿的共用区域电性连接以使与该两个共用区域对应的生长 线电性连接。
其中， 每个像素内的两条生长线均自对应的主干线相对的两端垂直延伸， 每条生长线均与在该第一方向上相邻的像素内的最邻近的生长线处于同一直线 上。
其中， 该薄膜晶体管阵列基板进一步包括屏蔽金属， 该屏蔽金属包括多个 第一屏蔽区、 多个第二屏蔽区及该多个共用区域， 该多个第一屏蔽区与多条直 线上的生长线对应并与数据线间隔， 该多个第二屏蔽区与该多个像素——对应， 并分别位于对应像素内的像素电极所在区域， 每个第二屏蔽区均通过共用区域 与两端的第一屏蔽区连接。
其中， 每个像素内的第二屏蔽区包括纵横交错的两段或者是包括沿第二方 向的一段。
其中， 该共用区域为该主干线上的一部分， 该两条生长线自该共用区域相 背的两侧垂直延伸。
其中， 该共用区域的形状为圓形、 三角形、 四边形或其他多边形。
其中， 该像素电极由透明导电薄膜形成。
其中， 该多条扫描线是以第一金属层制成， 用来传输扫描信号， 该公共电 极是以第一金属层制成， 该多条数据线是以第二金属层制成， 用来传输数据信 号。
本发明还提供了一种液晶显示面板， 包括如上所述的薄膜晶体管阵列基板。 其中， 每个像素内的两条生长线均自对应的主干线相对的两端垂直延伸， 每条生长线均与在该第一方向上相邻的像素内的最邻近的生长线处于同一直线 上。
其中， 该薄膜晶体管阵列基板进一步包括屏蔽金属， 该屏蔽金属包括多个 第一屏蔽区、 多个第二屏蔽区及该多个共用区域， 该多个第一屏蔽区与多条直 线上的生长线对应并与数据线间隔， 该多个第二屏蔽区与该多个像素——对应 , 并分别位于对应像素内的像素电极所在区域， 每个第二屏蔽区均通过共用区域 与两端的第一屏蔽区连接。
其中， 每个像素内的第二屏蔽区包括纵横交错的两段或者是包括沿第二方 向的一段。
其中， 该共用区域为该主干线上的一部分， 该两条生长线自该共用区域相 背的两侧垂直延伸。
其中， 该共用区域的形状为圓形、 三角形、 四边形或其他多边形。
其中， 该像素电极由透明导电薄膜形成。
其中， 该多条扫描线是以第一金属层制成， 用来传输扫描信号， 该公共电 极是以第一金属层制成， 该多条数据线是以第二金属层制成， 用来传输数据信 号。
本发明还提供了一种液晶显示面板的修复方法， 该液晶面板的修复方法用 于修复如上所述的薄膜晶体管阵列基板上的点缺陷及线缺陷。 该液晶面板的修 复方法包括： 当像素存在点缺陷时， 切断该像素中的薄膜晶体管对该像素中的 像素电极的信号， 并在该像素内的共用区域上通过激光打孔焊接的方式使该像 素电极与与其交叠的生长线短路； 及当主干线在与数据线相交叠处存在断线缺 陷时， 在该主干线沿着该第二方向所在两个像素内的两个共用区域上均通过激 光打孔并在孔内镀金属及在两个孔之间架上金属线以使与该两个共用区域对应 的生长线电性连接。
其中， 该液晶显示面板的修复方法进一步包括： 当主干线与数据线相交叠 处短路时， 则先将该相交叠处的主干线切断以消除该相交叠处的主干线与数据 线短路， 然后在该主干线沿着该第二方向所在的两个像素内的两个共用区域上 均通过激光打孔， 最后在两个孔内镀金属及在两个孔之间架上金属线以使与该 两个共用区域对应的生长线电性连接。
本发明提供的薄膜晶体管阵列基板、 液晶显示面板及液晶面板修复方法均 设置有共用区域， 并利用该共用区域同时完成点缺陷的修复及线缺陷的修复， 不仅布线结构简单， 而且其中用到的生长线较分别修复点缺陷及线缺陷时用到 的生长线短， 如此有效降低液晶显示面板的开口率。 附图说明 例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述 中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付 出创造性劳动性的前提下， 还可以根据这些附图获得其他的附图。
图 1是本发明第一实施例所提供的薄膜晶体管阵列基板的示意图； 图 2是本发明第三实施例所提供的薄膜晶体管阵列基板的示意图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行清 楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是 全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作出创造 性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
第一实施例
请参阅图 1 ,本发明第一实施例所提供的薄膜晶体管阵列基板 100包括纵横 交错的多条数据线及多条扫描线。 为了便于解释， 本实施例仅以该薄膜晶体管 阵列基板 100包括三条数据线 Gl、G2及 G3及两条扫描线 S1及 S2为例来说明。 该三条数据线 Gl、 G2及 G3彼此相互平行并朝第一方向（水平方向)延伸， 该两 条扫描线 S1及 S2彼此相互平行并朝第二方向 (垂直方向)延伸。该薄膜晶体管阵 列基板 100进一步包括一个公共电极 10、 由该三条数据线 Gl、 G2及 G3及该两 条扫描线 S1及 S2彼此纵横交错定义的四个像素 Pll、 P12、 P21及 P22、 以及 一个屏蔽金属 30。 其中， 该两条扫描线 S1及 S2是以第一金属层制成， 用来传 输扫描信号。 该公共电极 10也是以第一金属层制成。 该三条数据线 Gl、 G2及 G3是以第二金属层制成， 用来传输数据信号。 该第一金属层及该第二金属层之 间有氮化硅绝缘层隔离。
该公共电极 10包括一条主干线 12及八条生长线 14。该主干线 12位于该两 条扫描线 S1及 S2之间并与该两条扫描线 S1及 S2平行。 即， 该主干线 12也朝 第二方向延伸。 该四个像素 Pll、 P12、 P21及 P22均匀分布在该主干线 12相背 的两侧。 该八条生长线 14均勾分布在该主干线 12相背的两侧， 且各像素 P11、 P12、 P21及 P22的区域中均具有两条生长线 14。
各像素 Pll、 P12、 P21及 P22均包括一个像素电极 22、一个薄膜晶体管 24、 部分主干线 12及两条生长线 14。 本实施例中， 该像素电极 22由透明导电薄膜 形成， 具体材料为铟锡金属氧化物。 该薄膜晶体管 24的栅极与该扫描线 S2(仅 以像素 P12为例）电性连接， 源极与该数据线 G1 (仅以像素 P12为例）电性连接， 漏极与该像素电极 22电性连接。 该两条生长线 14均自对应的部分主干线 12相 对的两端垂直延伸， 且每条生长线 14均与在该第一方向上相邻的像素 P11内的 最邻近的生长线 14处于同一直线上， 即该八条生长线 14在该第一方向上两两 共形成四条直线。 该两条生长线 14的投影与该像素电极 22均有交叠。
该屏蔽金属 30包括四个第一屏蔽区 32、 四个第二屏蔽区 34及八个共用区 域 36。 该四个第一屏蔽区 32的投影与该四条直线上的生长线 14有交叠， 且该 四个第一屏蔽区 32分别与该三条数据线 Gl、 G2及 G3均相邻且间隔。 该四个 第二屏蔽区 34与该四个像素 Pll、 P12、 P21及 P22——对应， 并分别位于对应 像素 Pll、 P12、 P21及 P22的像素电极 22所在区域。 其中， 像素 P12及 P22 中的第二屏蔽区 34包括纵横交错的两段，而像素 P11及 P21中的第二屏蔽区 34 仅包括沿第二方向的一段。 各像素 Pll、 P12、 P21及 P22中均分布有两个共用 区域 36, 且该两个共用区域 36分别自各像素 Pll、 P12、 P21及 P22区域内的 两个第一屏蔽区 32延伸。 每个第二屏蔽区 34均通过该两个共用区域 36与两端 的第一屏蔽区 32连接。 本实施例中， 该共用区域 36为三角形。
可以理解，该共用区域 36并不局限于本实施例中为三角形，还可以是圓形、 四边形或其他多边形， 规则或不规则的形状均可， 该共用区域 36的大小也没有 局限， 只要满足每个第二屏蔽区 34均能通过该两个共用区域 36与两端的第一 屏蔽区 32连接即可。 另夕卜， 在其他实施例中， 各像素 Pll、 P12、 P21及 P22中 的第二屏蔽区 34可全部为包括纵横交错的两段， 也可全部为仅包括沿第二方向 的一段， 还可以是上述两种结构的任意组合。
第二实施例
一种用于修复如第一实施例所述的薄膜晶体管阵列基板 100上的点缺陷及 线缺陷的液晶面板修复方法包括：
当像素 P12内存在点缺陷时， 即 P12为亮点时， 则切断该像素 P12中的薄 膜晶体管 24对该像素 P12中的像素电极 22的信号， 并在该像素 P12内的其中 一个共用区域 36, 例如 B1处的共用区域 36上通过激光打孔焊接的方式使该像 素电极 22与与其交叠的生长线 14短路， 从而将 P12内的亮点修复成常暗状态。 当主干线 12在与数据线 G2相交叠处 (A处)存在断线时， 在该主干线 12沿 着该第二方向所在的两个像素 P12及 P22内的两个共用区域 36(即 B1处的共用 区域 36及 B2处的共用区域 36)上均通过激光打孔，并在两个孔内镀金属及在两 个孔之间架上金属线以使与该两个共用区域 36对应的生长线 14电性连接。
当主干线 12与数据线 G2相交叠处 (A处)的氮化硅绝缘破洞造成短路，或者 是当该相交叠处 (A处)的主干线 12与数据线 G2被静电击伤而造成短路时，则先 将该相交叠处 (A处)的主干线 12切断以消除该相交叠处 (A处)的主干线 12与数 据线 G2短路， 然后在该主干线 12沿着该第二方向所在的两个像素 P12及 P22 内的两个共用区域 36(即 B1处的共用区域 36及 B2处的共用区域 36)上均通过 激光打孔， 最后在两个孔内镀金属及在两个孔之间架上金属线以使与该两个共 用区域 36对应的生长线 14电性连接。
第三实施例
请参阅图 2,本发明第三实施例所提供的薄膜晶体管阵列基板 200包括相互 纵横交错的多条数据线及多条扫描线。 为了便于解释， 本实施例仅以该薄膜晶 体管阵列基板 200包括三条数据线 Gl、 G2及 G3及两条扫描线 S1及 S2为例来 说明。该三条数据线 Gl、 G2及 G3彼此相互平行并朝第一方向 (垂直方向)延伸， 该两条扫描线 S1及 S2彼此相互平行并朝第二方向（水平方向)延伸。该薄膜晶体 管阵列基板 100进一步包括一个公共电极 40、 由该三条数据线 Gl、 G2及 G3 及该两条扫描线 S1及 S2彼此纵横交错定义的两个像素 P11及 P12。 其中， 该 两条扫描线 S1及 S2是以第一金属层制成， 用来传输扫描信号。 该公共电极 40 也是以第一金属层制成。 该三条数据线 Gl、 G2及 G3是以第二金属层制成， 用 来传输数据信号。 该第一金属层及该第二金属层之间有氮化硅绝缘层隔离。
该公共电极 40包括一条主干线 42及四条生长线 44。该主干线 42位于该两 条扫描线 S1及 S2之间并与该两条扫描线 S1及 S2平行。 即， 该主干线 42也朝 第二方向延伸。该主干线 42穿过该两个像素 P11及 P12。该四条生长线 44均匀 分布在该主干线 42相背的两侧， 且各像素 P11及 P12的区域中均具有两条生长 线 44。
各像素 P11及 P12均包括一个像素电极 52及一个薄膜晶体管 54、部分主干 线 42及两条生长线 44。 本实施例中， 该像素电极 52由透明导电薄膜形成， 具 体材料为铟锡金属氧化物。该薄膜晶体管 54的栅极与该扫描线 S2(仅以像素 P12 为例）电性连接， 源极与该数据线 G2(仅以像素 P12为例）电性连接， 漏极与该像 素电极 52电性连接。 该部分主干线 42上定义一个共用区域 A, 该两条生长线 44 均自对该共用区域 A (三角形所示区域)相背的两侧垂直延伸。 该两条生长线 44的投影与该像素电极 52均有交叠。像素 P11的结构与像素 P12的结构完全相 同， 在此不再赘述。
可以理解， 该共用区域 A并不局限于本实施例中为三角形， 还可以是圓形、 四边形或其他多边形， 规则或不规则的形状均可， 该共用区域 A的大小也没有 局限。
第四实施例
一种用于修复如第三实施例所述的薄膜晶体管阵列基板 200上的点缺陷及 线缺陷的液晶面板修复方法包括：
当像素 P12内存在点缺陷时， 即 P12为亮点时， 则切断该像素 P12中的薄 膜晶体管 54对该像素 P12中的像素电极 52的信号， 并在该像素 P12内的共用 区域 A上通过激光打孔焊接的方式使该像素电极 52与与其交叠的主干线 42短 路， 从而将 P12内的亮点修复成常暗状态。
当主干线 42在像素 P11及 P12中两个共用区域 A之间存在断线时，在该两 个共用区域 A上均通过激光打孔， 并在两个孔内镀金属及在两个孔之间架上金 属线以使与该两个共用区域 A对应的生长线 44电性连接。
当主干线 42与数据线 G2相交叠处 (C处)的氮化硅绝缘破洞造成短路，或者 是当该相交叠处 (C处)的主干线 42与数据线 G2被静电击伤而造成短路时，则先 将该相交叠处 (C处)的主干线 42切断以消除该相交叠处 (C处)的主干线 42与数 据线 G2短路， 然后在该两个共用区域 A上均通过激光打孔， 并在两个孔内镀 金属及在两个孔之间架上金属线以使与该两个共用区域 A对应的生长线 44电性 连接。
此外， 本发明还提供一种液晶显示面板， 包括如第一实施例中所述的薄膜 晶体管阵列基板 100或者如第三实施例中所述的薄膜晶体管阵列基板 200,在此 不做详述。
本发明提供的薄膜晶体管阵列基板 100及 200、液晶显示面板及液晶面板修 复方法均设置有一个共用区域 36或共用区域 A, 并利用该共用区域 36或共用 区域 A同时完成点缺陷的修复及线缺陷的修复， 不仅布线结构简单， 而且其中 用到的生长线较独立完成两种缺陷的修复时用到的生长线短， 如此有效降低液 晶显示面板的开口率。
以上所揭露的仅为本发明一种较佳实施例而已， 当然不能以此来限定本发 明之权利范围， 因此依本发明权利要求所作的等同变化， 仍属本发明所涵盖的 范围。

Claims

权 利 要 求 书
1. 一种薄膜晶体管阵列基板， 包括多条彼此相互平行并朝第一方向延伸的 数据线、 多条彼此相互平行并朝与第一方向垂直的第二方向延伸的扫描线、 由 该多条数据线及该多条扫描线定义的多个像素及具有一条主干线及多条生长线 的公共电极， 其中， 该主干线与该多条扫描线平行， 该生长线自该主干线垂直 延伸， 每个像素包括一个像素电极、 一个薄膜晶体管、 部分主干线以及两条生 长线， 该薄膜晶体管与该像素电极、 对应的数据线及对应的扫描线均电性连接， 该两条生长线的投影与该像素电极有交叠， 每个像素均设置有共用区域， 该共 用区域与该生长线有交叠， 该共用区域用于被打穿以使该像素电极与对应的生 长线电性连接， 及用于被打穿后与在该第二方向上相邻的另一被打穿的共用区 域电性连接以使与该两个共用区域对应的生长线电性连接。
2. 如权利要求 1所述的薄膜晶体管阵列基板， 其中， 每个像素内的两条生 长线均自对应的主干线相对的两端垂直延伸， 每条生长线均与在该第一方向上 相邻的像素内的最邻近的生长线处于同一直线上。
3. 如权利要求 2所述的薄膜晶体管阵列基板， 其中， 该薄膜晶体管阵列基 板进一步包括屏蔽金属， 该屏蔽金属包括多个第一屏蔽区、 多个第二屏蔽区及 该多个共用区域， 该多个第一屏蔽区与多条直线上的生长线对应并与数据线间 隔， 该多个第二屏蔽区与该多个像素——对应， 并分别位于对应像素内的像素 电极所在区域， 每个第二屏蔽区均通过共用区域与两端的第一屏蔽区连接。
4. 如权利要求 3所述的薄膜晶体管阵列基板， 其中， 每个像素内的第二屏 蔽区包括纵横交错的两段或者是包括沿第二方向的一段。
5. 如权利要求 1所述的薄膜晶体管阵列基板， 其中， 该共用区域为该主干 线上的一部分， 该两条生长线自该共用区域相背的两侧垂直延伸。
6. 如权利要求 1所述的薄膜晶体管阵列基板， 其中， 该共用区域的形状为 圓形、 三角形、 四边形或其他多边形。
7 如权利要求 1 所述的薄膜晶体管阵列基板， 其中， 该像素电极由透明导 电薄膜形成。
8. 如权利要求 1所述的薄膜晶体管阵列基板， 其中， 该多条扫描线是以第 一金属层制成， 用来传输扫描信号， 该公共电极是以第一金属层制成， 该多条 数据线是以第二金属层制成， 用来传输数据信号。
9. 一种液晶显示面板， 包括如权利要求 1所述的薄膜晶体管阵列基板。
10. 如权利要求 9所述的液晶显示面板， 其中， 每个像素内的两条生长线均 自对应的主干线相对的两端垂直延伸， 每条生长线均与在该第一方向上相邻的 像素内的最邻近的生长线处于同一直线上。
11. 如权利要求 10所述的液晶显示面板， 其中， 该薄膜晶体管阵列基板进 一步包括屏蔽金属， 该屏蔽金属包括多个第一屏蔽区、 多个第二屏蔽区及该多 个共用区域， 该多个第一屏蔽区与多条直线上的生长线对应并与数据线间隔， 该多个第二屏蔽区与该多个像素——对应， 并分别位于对应像素内的像素电极 所在区域， 每个第二屏蔽区均通过共用区域与两端的第一屏蔽区连接。
12. 如权利要求 11所述的液晶显示面板， 其中， 每个像素内的第二屏蔽区 包括纵横交错的两段或者是包括沿第二方向的一段。
13. 如权利要求 9所述的液晶显示面板， 其中， 该共用区域为该主干线上的 一部分， 该两条生长线自该共用区域相背的两侧垂直延伸。
14. 如权利要求 9所述的液晶显示面板， 其中， 该共用区域的形状为圓形、 三角形、 四边形或其他多边形。
15. 如权利要求 9所述的液晶显示面板， 其中， 该像素电极由透明导电薄膜 形成。
16. 如权利要求 9所述的液晶显示面板， 其中， 该多条扫描线是以第一金属 层制成， 用来传输扫描信号， 该公共电极是以第一金属层制成， 该多条数据线 是以第二金属层制成 , 用来传输数据信号。
17. 一种液晶显示面板的修复方法，该液晶面板的修复方法用于修复如权利 要求 1 所述的薄膜晶体管阵列基板上的点缺陷及线缺陷， 该液晶面板的修复方 法包括：
当像素存在点缺陷时， 切断该像素中的薄膜晶体管对该像素中的像素电极 的信号， 并在该像素内的共用区域上通过激光打孔焊接的方式使该像素电极与 与其交叠的生长线短路； 及
当主干线在与数据线相交叠处存在断线缺陷时， 在该主干线沿着该第二方 向所在两个像素内的两个共用区域上均通过激光打孔并在孔内镀金属及在两个 孔之间架上金属线以使与该两个共用区域对应的生长线电性连接。
18. 如权利要求 17所述的液晶显示面板的修复方法， 其特征在于， 该液晶 显示面板的修复方法进一步包括： 当主干线与数据线相交叠处短路时， 则先将 该相交叠处的主干线切断以消除该相交叠处的主干线与数据线短路， 然后在该 主干线沿着该第二方向所在的两个像素内的两个共用区域上均通过激光打孔， 最后在两个孔内镀金属及在两个孔之间架上金属线以使与该两个共用区域对应 的生长线电性连接。
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