WO2015100755A1 - 薄膜晶体管液晶显示装置及其信号线 - Google Patents

薄膜晶体管液晶显示装置及其信号线 Download PDF

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WO2015100755A1
WO2015100755A1 PCT/CN2014/070197 CN2014070197W WO2015100755A1 WO 2015100755 A1 WO2015100755 A1 WO 2015100755A1 CN 2014070197 W CN2014070197 W CN 2014070197W WO 2015100755 A1 WO2015100755 A1 WO 2015100755A1
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signal line
thin film
liquid crystal
film transistor
crystal display
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French (fr)
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韩丙
王金杰
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/235,806 priority Critical patent/US20150185574A1/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to a thin film transistor liquid crystal display, and more particularly to a thin film transistor liquid crystal display device having a low impedance signal line and a signal line thereof.
  • Thin film transistor liquid crystal display Thin-Film Transistor Liquid Crystal Display, TFT-LCD is a type of display, and it has the advantages of low power consumption, thinness, high resolution, etc., and is currently the mainstream of displays.
  • the signal lines on the pixel array substrate of the thin film transistor liquid crystal display tend to cause RC delay due to the presence of parasitic resistance and parasitic capacitance (RC). Delay).
  • RC delay parasitic resistance and parasitic capacitance
  • the effect of RC delay on signal line data transmission speed is negligible.
  • the length of the signal line on the pixel array substrate also increases as the size of the liquid crystal display device becomes larger, so that the impedance of the signal line rises. As a result, the lag delay becomes more serious, which greatly affects the data transmission speed of the signal line.
  • the main object of the present invention is to provide a thin film transistor liquid crystal display device and a signal line thereof to solve the technical problem that the existing signal line affects the charging rate due to the resistance delay hysteresis.
  • the present invention provides a signal line for a thin film transistor liquid crystal display device, the structure comprising: a metal layer; an insulating layer covering the upper surface of the metal layer and having at least one via hole And exposing the metal layer; and a transparent conductive layer formed on the insulating layer and overlapping with the metal layer, wherein the transparent conductive layer is electrically connected to the metal layer through a through hole of the insulating layer .
  • the present invention further provides a thin film transistor liquid crystal display device having a plurality of pixel regions arranged in a matrix, wherein the pixel region is defined by a plurality of signal lines, the signal line structure comprising: a metal layer; an insulation a layer covering the upper surface of the metal layer and having at least one through hole exposing the metal layer; and a transparent conductive layer formed on the insulating layer and overlapping the metal layer, wherein the transparent conductive layer The through hole of the insulating layer is electrically connected to the metal layer.
  • the invention mainly comprises adding a transparent conductive layer above the metal line to form a signal line connecting the thin film transistors, and the multi-layer structure composed of the metal layer and the transparent conductive layer can effectively reduce the impedance of the whole signal line and reduce the resistance.
  • the hysteresis delay increases the charging rate and improves the color shift.
  • 1 is a waveform diagram of signal transmission of a conventional thin film transistor liquid crystal display.
  • FIG. 2 is a waveform diagram of a data line transmission signal of a conventional thin film transistor liquid crystal display.
  • FIG. 3 is a waveform diagram of a data line transmission signal of another conventional thin film transistor liquid crystal display.
  • FIG. 4 is a schematic diagram of a pixel array of a thin film transistor liquid crystal display according to a preferred embodiment of the present invention.
  • Figure 5 is a schematic illustration of signal lines constituting a pixel region in accordance with a preferred embodiment of the present invention.
  • Figure 6 is a cross-sectional view showing a signal line in accordance with a preferred embodiment of the present invention.
  • FIG. 7a is a waveform diagram of a data line transmission signal of a thin film transistor liquid crystal display according to a preferred embodiment of the present invention.
  • FIG. 7b is a waveform diagram of a data line transmission signal of a thin film transistor liquid crystal display according to another preferred embodiment of the present invention.
  • Figure 8 is a cross-sectional view showing a signal line of another preferred embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a pixel array of a thin film transistor liquid crystal display according to a preferred embodiment of the present invention.
  • the thin film transistor liquid crystal display basically comprises two oppositely disposed substrates and a liquid crystal layer disposed between the substrates.
  • a plurality of signal lines 10 are disposed on the surface thereof, including a plurality of scanning lines 100 and a plurality of data lines 101, wherein the scanning lines 100 extend in a horizontal direction and are spaced apart from each other.
  • the data lines 101 extend in the vertical direction, are spaced apart from each other and are vertically interlaced with the scan lines 100, thereby defining a plurality of pixel regions A arranged in a matrix.
  • a thin film transistor 102 is disposed in each of the pixel regions A, and one of the scan lines 100 and one of the data lines 101 and one of the pixel electrodes 103 are simultaneously connected.
  • the thin film transistor 102 can be turned on by accepting a scan signal of the scan line 100, so that the data signal of the data line 101 is then transmitted to the pixel electrode 103 through the thin film transistor 102.
  • the signal line 10 defining the pixel area A that is, the scan line 100 and the data line 101, at least one of them has a multi-layer structure.
  • the multi-layer structure mainly includes a metal layer 10a and a transparent conductive layer 10b stacked on the metal layer 10a and electrically connected to each other.
  • the metal layer 10a may be formed on the surface of a glass substrate by a photolithography process such as sputtering, etching, or the like, which is preferably a copper layer.
  • the transparent conductive layer 10b may be directly or indirectly formed on the upper surface of the metal layer 10a.
  • an insulating layer 10c is disposed between the metal layer 10a and the transparent conductive layer 10b, and the insulating layer 10c covers the upper surface of the metal layer 10a and has at least one through hole 104 for partial exposure.
  • the metal layer 10a The transparent conductive layer 10b is formed on the insulating layer 10c so as to overlap the metal layer 10a, and is electrically connected to the metal layer 10a through the through hole 104 of the insulating layer 10c.
  • the insulating layer 10c includes a plurality of spaced through holes 104. As shown in FIG. 5, the through holes 104 are spaced apart along the length direction of the signal line 10.
  • the signal line 10 when the signal line 10 is used as the scan line 100, the signal line 10 preferably includes two of the through holes 104 in the width range W of each of the pixel areas A; In other words, the scan line 100 has a section within the width range W of the pixel area A, and has two of the through holes 104 on the section.
  • the two through holes 104 can be away from each other and close to both sides of the pixel area A, respectively. The arrangement of the through holes 104 can effectively strengthen the electrical connection between the transparent conductive layer 10b and the metal layer 10a.
  • the transparent conductive layer 10b is overlapped and connected to the metal layer 10a to effectively reduce the impedance of the signal line 10.
  • the signal line 10 transmits the scan signal as the scan line 100, the phenomenon of retardation of the resistive capacitance can be improved, thereby improving the mischarge condition and increasing the charging rate of the pixel electrode.
  • the signal line 10 When the signal line 10 is used as the data line 101, in the length range L of each of the pixel areas A, the signal line 10 includes one of the through holes 104; in other words, the data line 101 has a section within the length range L of the pixel area A, and has one of the through holes 104 in the section.
  • the transparent conductive layer 10b overlaps and connects the metal layer 10a to effectively reduce the impedance of the signal line 10, when the signal line 10 transmits the data signal as the data line 101, as shown in FIG. 7a,
  • the phenomenon of RC delay can be improved, and the charging rate of the pixel electrode is effectively increased.
  • FIG. 7b when the adjacent two pixel units perform color mixing, the difference in charging between the two is also reduced due to the decrease in the RC delay, so that the color shift problem is also improved.
  • FIG. 8 is a cross-sectional view of a signal line according to another preferred embodiment of the present invention.
  • the thin film transistor liquid crystal display further has a color filter layer disposed on the pixel array formed by the pixel region, which can save the amount of material relative to the manner in which the color filter layer is generally disposed on another substrate. Therefore, in the embodiment, the insulating layer 10c includes at least one transparent insulating layer 110 and a color filter layer 111 formed of a photoresist.
  • the present invention adds a transparent conductive layer to form a signal line connecting the thin film transistors by means of via connection above the metal lines.
  • the multi-layer structure composed of the metal layer and the transparent conductive layer can effectively reduce the impedance of the overall signal line, reduce the resistance delay, thereby increasing the charging rate and improving the color shift phenomenon.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种薄膜晶体管液晶显示装置及其信号线（10）。信号线（10）包含一金属层（10a）与一堆叠于金属层（10a）上的透明导电层（10b），透明导电层（10b）电性连接金属层（10a）。金属层（10a）与透明导电层（10b）构成的复层结构可降低整体信号线（10）的阻抗，减小电路的阻容迟滞，增大充电率。

Description

薄膜晶体管液晶显示装置及其信号线 技术领域
本发明是有关于一种薄膜晶体管液晶显示器，特别是有关于一种具有低阻抗信号线的薄膜晶体管液晶显示装置及其信号线。
 背景技术
薄膜晶体管液晶显示器(Thin-Film Transistor Liquid Crystal Display, TFT-LCD)是显示器的一种，因为其具有低消耗功率、薄型化、高解析度等优点，故为目前显示器的主流。
薄膜晶体管液晶显示器的像素阵列基板上的信号线往往会因为寄生电阻与寄生电容的存在而造成阻容迟滞(RC delay)。对于小尺寸的液晶显示器来说，阻容迟滞对于信号线资料传输速度的影响尚可忽略。然而，随着液晶显示装置的尺寸越作越大，像素阵列基板上的信号线的长度也因为液晶显示装置尺寸的变大而增长，使得信号线的阻抗上升。如此一来，阻容迟滞变得更加严重，大大地影响了信号线资料传输速度。
以像素阵列基板的扫描线来说，如果扫描线的阻抗太大，其传输的电子信号波形会产生延迟，引起错充，如图1所示；同时也会造成像素单元的色偏程度不均。
如图2所示，以像素阵列基板的扫描线来说，当电子信号在高低电位切换时，资料线的阻抗太大会使真正的充电时间减少，影响充电率；再者，由于阻容迟滞，如图3所示，在混色画面下，后写入的像素单元由于其信号波形较前一个完美，前后两个画素单元充电差异较大引起了色偏现象。
故，有必要提供一种薄膜晶体管液晶显示装置及其信号线，以解决现有技术所存在的问题。
 技术问题
有鉴于现有技术的缺点，本发明的主要目的在于提供一种用于薄膜晶体管液晶显示装置及其信号线，以解决现有的信号线因阻容迟滞影响充电率的技术问题。
 技术解决方案
为达成本发明的前述目的，本发明提供一种用于薄膜晶体管液晶显示装置的信号线，其结构包含：一金属层；一绝缘层，覆盖所述金属层的上表面，并具有至少一通孔裸露所述金属层；以及一透明导电层，成形于所述绝缘层上而与所述金属层重叠设置，其中所述透明导电层通过所述绝缘层的通孔与所述金属层电性连接。
本发明另提供一种薄膜晶体管液晶显示装置，具有多个呈局阵排列的像素区，所述像素区有多条信号线定义而成，所述信号线的结构包括：一金属层；一绝缘层，覆盖所述金属层的上表面，并具有至少一通孔裸露所述金属层；以及一透明导电层，成形于所述绝缘层上而与所述金属层重叠设置，其中所述透明导电层通过所述绝缘层的通孔与所述金属层电性连接。
 有益效果
本发明主要是在金属线的上方增设一透明导电层来构成连接各薄膜晶体管的信号线，由所述金属层与透明导电层构成的复层结构可有效降低整体信号线的阻抗，减小阻容迟滞，进而增大充电率以及改善色偏现象。
 附图说明
图1是现有薄膜晶体管液晶显示器的信号传递的波形示意图。
图2是现有薄膜晶体管液晶显示器的资料线传递信号的波形示意图。
图3是另一现有薄膜晶体管液晶显示器的资料线传递信号的波形示意图。
图4是本发明一较佳实施例的薄膜晶体管液晶显示器的像素阵列的示意图。
图5是本发明一较佳实施例的构成像素区的信号线的示意图。
图6是本发明一较佳实施例的信号线的剖面示意图。
图7a是本发明一较佳实施例的薄膜晶体管液晶显示器的资料线传递信号的波形示意图。
图7b是本发明另一较佳实施例的薄膜晶体管液晶显示器的资料线传递信号的波形示意图。
图8是本发明另一较佳实施例的信号线的剖面示意图。
 本发明的最佳实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参考图4所示，图4是本发明一较佳实施例的薄膜晶体管液晶显示器的像素阵列的示意图。所述薄膜晶体管液晶显示器基本包含两相对设置的基板与设置于基板之间的液晶层。如图4所示，在其中一基板上，其表面会设有多条信号线10，包括多条扫描线100与多条资料线101，其中所述扫描线100沿水平方向延伸，彼此间间隔并排；所述资料线101则沿垂直方向延伸，彼此间隔并排并且与所述扫瞄线100垂直交错，因而定义出多个呈矩阵排列的像素区A。在每个像素区A内设有一薄膜晶体管102，其同时连接其中一条扫描线100与其中一条资料线101以及一像素电极103。所述薄膜晶体管102可接受扫描线100的扫描信号而开启，使得资料线101的资料信号随即通过所述薄膜晶体管102传输到所述像素电极103。
进一步参考图5与图6所示，定义所述像素区A的信号线10，即所述扫描线100和资料线101，至少其中之一是具有一复层结构。所述复层结构主要包括一金属层10a与一与该金属层10a堆叠且相互电性连接的透明导电层10b。
所述金属层10a可通过溅镀、蚀刻等光刻工艺的步骤形成于一玻璃基板的表面，其优选是铜层。
所述透明导电层10b可以是直接或间接地对应形成于该金属层10a的上表面。例如在本实施例中，所述金属层10a与所述透明导电层10b之间是设有一绝缘层10c，该绝缘层10c覆盖所述金属层10a的上表面并具有至少一通孔104以局部裸露所述金属层10a。所述透明导电层10b则成形于所述绝缘层10c上而与所述金属层10a重叠设置，并且通过所述绝缘层10c的通孔104与所述金属层10a电性连接。
在本实施例中，所述绝缘层10c包含多个间隔设置的通孔104。如图5所示，所述通孔104沿着所述信号线10的长度方向间隔设置。更详细来说，当所述信号线10是用于作为所述扫描线100时，在每一个像素区A的宽度范围W内，所述信号线10优选包含两个所述通孔104；换句话说，所述扫描线100在像素区A的宽度范围W内具有一区段，而该区段上具有两个所述通孔104。在本实施例中，所述两个通孔104可远离彼此而分别靠近该像素区A的两侧。所述通孔104的排列方式可以有效地强化所述透明导电层10b与所述金属层10a之间的电性连接。
所述透明导电层10b重叠并连接所述金属层10a可有效地降低所述信号线10的阻抗。当所述信号线10作为所述扫描线100而传递扫描信号时，阻容迟滞的现象可获得改善，进而改善错充情况，提高像素电极的充电率。
当所述信号线10是用于作为所述资料线101时，在每一个像素区A的长度范围L内，所述信号线10包含一个所述通孔104；换句话说，所述资料线101在像素区A的长度范围L内具有一区段，而该区段上具有一个所述通孔104。
由于所述透明导电层10b重叠并连接所述金属层10a有效地降低所述信号线10的阻抗，当所述信号线10作为所述资料线101而传递资料讯号时，如图7a所示，阻容迟滞的现象可获得改善，有效增大像素电极的充电率。同时如图7b所示，当相邻两像素单元进行混色时，两者的充电差异也因为阻容迟滞降低而缩小，使得色偏问题也获得改善。
请进一步参考图8所示，图8是本发明另一较佳实施例的信号线的剖面示意图。在本实施例中，所述薄膜晶体管液晶显示器进一步设置一彩色滤光层于所述像素区构成的像素阵列上，可相对于一般将彩色滤光层设置于另一基板的方式节省材料用量。因此，在本实施例中，所述绝缘层10c包含至少一透明绝缘层110与一由光刻胶形成的彩色滤光层111。
综上所述，相较于现有薄膜晶体管液晶显示器具有严重的阻容迟滞的问题，本发明在金属线的上方通过通孔连接的方式增设一透明导电层来构成连接各薄膜晶体管的信号线，由所述金属层与透明导电层构成的复层结构可有效降低整体信号线的阻抗，减小阻容迟滞，进而增大充电率以及改善色偏现象。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
 本发明的实施方式
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Claims (13)

  1. 一种用于薄膜晶体管液晶显示装置的信号线，所述薄膜晶体管液晶显示装置具有多条间隔并排的扫描线与多条间隔并排且与所述扫瞄线垂直交错的资料线，所述信号线用以作为所述扫描线与资料线并包含：
    一金属层；
    一绝缘层，覆盖所述金属层的上表面，并具有至少一通孔裸露所述金属层；以及
    一透明导电层，成形于所述绝缘层上而与所述金属层重叠设置，其中所述透明导电层通过所述绝缘层的通孔与所述金属层电性连接。
  2. 如权利要求1所述的用于薄膜晶体管液晶显示装置的信号线，其中：所述绝缘层包含多个间隔设置的通孔；所述通孔沿着所述信号线的长度方向间隔设置；在每一个像素区的宽度范围内，所述作为扫描线的信号线包含两个所述通孔。
  3. 如权利要求2所述的用于薄膜晶体管液晶显示装置的信号线，其中：在每一个像素区的长度范围内，所述作为资料线的信号线包含一个所述通孔。
  4. 一种用于薄膜晶体管液晶显示装置的信号线，其包含：
    一金属层；
    一绝缘层，覆盖所述金属层的上表面，并具有至少一通孔裸露所述金属层；以及
    一透明导电层，成形于所述绝缘层上而与所述金属层重叠设置，其中所述透明导电层通过所述绝缘层的通孔与所述金属层电性连接。
  5. 如权利要求4所述的用于薄膜晶体管液晶显示装置的信号线，其中：所述薄膜晶体管液晶显示装置具有多条间隔并排的扫描线与多条间隔并排且与所述扫瞄线垂直交错的资料线，所述扫描线与资料线构成多个呈矩阵排列的像素区；所述信号线是作为所述薄膜晶体管液晶显示装置的扫描线。
  6. 如权利要求5所述的用于薄膜晶体管液晶显示装置的信号线，其中：所述绝缘层包含多个间隔设置的通孔；所述通孔沿着所述信号线的长度方向间隔设置；在每一个像素区的宽度范围内，所述作为扫描线的信号线包含两个所述通孔。
  7. 如权利要求4所述的用于薄膜晶体管液晶显示装置的信号线，其中：所述薄膜晶体管液晶显示装置具有多条间隔并排的扫描线与多条间隔并排且与所述扫瞄线垂直交错的资料线，所述扫描线与资料线构成多个呈矩阵排列的像素区；所述信号线是作为所述薄膜晶体管液晶显示装置的资料线。
  8. 如权利要求7所述的用于薄膜晶体管液晶显示装置的信号线，其中：所述绝缘层包含多个间隔设置的通孔；所述通孔沿着所述信号线的长度方向间隔设置；在每一个像素区的长度范围内，所述作为资料线的信号线包含一个所述通孔。
  9. 如权利要求5所述的用于薄膜晶体管液晶显示装置的信号线，其中：所述绝缘层包含至少一透明绝缘层与一彩色滤光层。
  10. 一种薄膜晶体管液晶显示装置，具有多个呈局阵排列的像素区，所述像素区有多条信号线定义而成，其中所述信号线的结构包含：
    一金属层；
    一绝缘层，覆盖所述金属层的上表面，并具有至少一通孔裸露所述金属层；以及
    一透明导电层，成形于所述绝缘层上而与所述金属层重叠设置，其中所述透明导电层通过所述绝缘层的通孔与所述金属层电性连接。
  11. 如权利要求10所述的薄膜晶体管液晶显示装置，其中：所述信号线包括多条间隔并排的扫描线与多条间隔并排且与所述扫瞄线垂直交错的资料线。
  12. 如权利要求10所述的薄膜晶体管液晶显示装置，其中：所述绝缘层包含多个间隔设置的通孔；所述通孔沿着所述信号线的长度方向间隔设置。
  13. 如权利要求11所述的薄膜晶体管液晶显示装置，其中：在每一个像素区的宽度范围内，所述作为扫描线的信号线包含两个所述通孔；在每一个像素区的长度范围内，所述作为资料线的信号线包含一个所述通孔。
PCT/CN2014/070197 2013-12-30 2014-01-07 薄膜晶体管液晶显示装置及其信号线 Ceased WO2015100755A1 (zh)

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