WO2015096247A1 - 阵列基板的防静电结构 - Google Patents

阵列基板的防静电结构 Download PDF

Info

Publication number
WO2015096247A1
WO2015096247A1 PCT/CN2014/070966 CN2014070966W WO2015096247A1 WO 2015096247 A1 WO2015096247 A1 WO 2015096247A1 CN 2014070966 W CN2014070966 W CN 2014070966W WO 2015096247 A1 WO2015096247 A1 WO 2015096247A1
Authority
WO
WIPO (PCT)
Prior art keywords
shorting bar
gate
lines
array substrate
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/070966
Other languages
English (en)
French (fr)
Inventor
徐向阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/347,596 priority Critical patent/US9165950B2/en
Publication of WO2015096247A1 publication Critical patent/WO2015096247A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an antistatic structure of an array substrate. Background technique
  • Liquid Crystal Display has many advantages such as thin body, power saving, and no radiation, and has been widely used.
  • the liquid crystal display device on the market is mostly a backlight type liquid crystal display device, and includes a casing, a liquid crystal display panel disposed in the casing, and a backlight module disposed in the casing and disposed opposite to the liquid crystal display panel.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates, and apply driving voltages on the two glass substrates to control the rotation of the liquid crystal molecules, thereby folding the light of the backlight module to produce a picture.
  • ESD Electrostatic discharge
  • Process conditions such as a deposition process, a hoto process, an etch process, a strip process, and a clean process generate static electricity, and the raw materials used in the processes are also defective due to materials. Static electricity is generated.
  • the third is the design factor.
  • the quality of the product design directly affects the static electricity situation.
  • electrostatic protection work will be carried out in the production process of liquid crystal display panels.
  • the electrostatic protection work includes two categories: First, the internal device protection of the liquid crystal display panel, mainly designing an antistatic ring (ESD ring) at the beginning of the line (gate line and data line) of the liquid crystal display panel. Second, the peripheral circuit protection of the liquid crystal display panel is mainly to protect the array process and the damage of the static circuit on the peripheral circuit of the panel in the back-end process.
  • the film layer sequence is: the first metal layer
  • Gate/Com Gate Insulation
  • GI Active Layer
  • S/D Active Layer
  • PVX Passivation Layer
  • ITO Indium Tin Oxides
  • a simple test circuit that is, a shorting bar is set to realize the lighting of the box process, thereby reducing the electrostatic discharge phenomenon.
  • Current shorting bars are divided into two structures: a laser trimming structure and a switching structure.
  • the laser structure is to short the gate line and the data line directly to the short-circuit bar.
  • the switch structure is ⁇ Use a switch to input the shorting bar signal to the bridge and data lines.
  • An object of the present invention is to provide an antistatic structure of an array substrate, in which, in the manufacturing process of the array substrate, especially when the insulating protective layer and the active layer are subjected to a thousand laws (such as channel etching and via drying) It can well avoid the electrostatic damage caused by the abnormal discharge of plasma generated during the formation of via holes to the metal overlapping traces and via holes at the short-circuit bar, improve product quality, improve production efficiency, and reduce production cost.
  • a thousand laws such as channel etching and via drying
  • the present invention provides an antistatic structure of an array substrate, comprising: an effective region of the array substrate, a short gate line disposed on one side of the active region, and a bar disposed on the effective region a data line shorting bar on the other side, the effective area of the gate line shorting bar is adjacent to the other side of the set data line shorting bar, and the effective area of the array substrate is provided with a plurality of gates arranged in parallel with each other a line and a plurality of data lines arranged in parallel with each other, the gate line shorting bar is electrically connected to one end of the plurality of gate lines, and the data line shorting bar is electrically connected to the end of the plurality of data lines .
  • the plurality of gate lines and the plurality of data lines are perpendicular to each other, and each of the gate lines and the beginning end of each of the data lines are provided with an antistatic ring, and the antistatic rings are disposed around the effective area of the array substrate. All of the antistatic rings surrounding the active area of the array substrate are electrically connected together.
  • the antistatic structure of the array substrate further includes: a plurality of first fanout lines, a plurality of second fanout lines, a plurality of data line contact pads, and a plurality of *polar line contact pads, each of the first fanout lines One end is electrically connected to a data line, and the other end is electrically connected to a data line. One end of each of the second fan lines is electrically connected to a gate line contact pad, and the other end is respectively connected to a gate. Wire electrical connection.
  • the gate line shorting bar is electrically connected to each gate line contact pad to short all the gate lines; the data line shorting bar is electrically connected to each data line contact pad to connect all the data lines Short.
  • the gate line shorting bar includes: a substrate, a first metal layer formed on the substrate, a gate insulating layer covering the first metal layer and the substrate, and a passivation layer on the gate insulating layer.
  • the first metal layer of the gate line shorting bar is directly formed in the same layer as the plurality of gate lines, and the gate line shorting bar is electrically connected to the plurality of gate lines.
  • the data line shorting bar includes: a substrate, a gate insulating layer formed on the substrate, a second metal layer on the gate insulating layer, and a passivation layer overlying the second metal layer and the gate insulating layer.
  • the second metal layer of the data line shorting bar is directly formed in the same layer as the plurality of data lines, and the data line shorting bar is electrically connected to the plurality of data lines.
  • One end of the * pole line shorting bar is provided with a gate signal input pad for inputting a test signal; and one end of the data line shorting bar is provided with a data signal input pad for inputting a test signal.
  • the present invention also provides an antistatic structure of an array substrate, comprising: an effective area of the array substrate, a bridge line shorting bar disposed on one side of the effective area, and a data line disposed on the other side of the effective area a shorting bar, the active area is disposed adjacent to the other side of the set circuit shorting bar, and the effective area of the array substrate is provided with a plurality of mutually parallel bungee lines and a plurality of parallel lines Arranging data lines, the * pole line shorting bar is electrically connected to one end of the plurality of * pole lines, and the data line shorting bar is electrically connected to the plurality of data lines
  • the plurality of gate lines and the plurality of data lines are perpendicular to each other, and an antistatic ring is disposed at the beginning end of each of the gate lines and each of the data lines, and the antistatic rings are disposed around the effective area of the array substrate. ;
  • It also includes: a plurality of first fan outlets, a plurality of second fan outlets, and a plurality of data line contact pads. And a plurality of gate line contact pads, one end of each of the first fan-out lines is electrically connected to a data line contact pad, and the other end is electrically connected to a data line, and one end of each of the second fan-out lines is a gate
  • the line contact pad is electrically connected, and the other end is electrically connected to a gate line;
  • the gate line shorting bar is electrically connected to each of the *polar line contact pads to short all the drain lines;
  • the data line shorting bar is electrically connected to each of the data line contact pads to Shorted data line;
  • the gate line shorting bar includes: a substrate, a first metal layer formed on the substrate, a cabinet insulating layer covering the first metal layer and the substrate, and a passivation layer on the insulating layer of the cabinet.
  • the first metal layer of the gate line shorting bar is directly formed in the same layer as the plurality of gate lines, and the gate line shorting bar is electrically connected to the plurality of gate lines.
  • the data line shorting bar includes: a substrate, a gate insulating layer formed on the substrate, a second metal layer on the gate insulating layer, and a passivation layer overlying the second metal layer and the bridge insulating layer.
  • the second metal layer of the data line shorting bar is directly formed in the same layer as the plurality of data lines, and the data line shorting bar is electrically connected to the plurality of data lines.
  • One end of the * pole line shorting bar is provided with a gate signal input pad for inputting a test signal; and one end of the data line shorting bar is provided with a data signal input pad for inputting a test signal.
  • the antistatic structure of the array substrate of the present invention uses only one gate line shorting bar to short all the gate lines and one data line shorting bar to short all the data lines, thereby greatly simplifying the shorting bar circuit. Reducing the number of shorting bars, reducing the number of lighting signals in the process of forming the cartridge, and the first metal layer of the wire shorting bar is made in the same layer and directly connected to the plurality of gate wires, and then The gate line shorting bar is electrically connected to the plurality of gate lines, and the second metal layer of the data line shorting bar is directly formed in the same layer as the plurality of data lines, so that the array substrate is fabricated In the process, especially when the insulating protective layer and the active layer are dry etched (such as a channel and a thousand holes), the abnormal discharge of the plasma generated during the formation of the via hole can be well avoided. Electrostatic damage caused by metal traces and vias is better for electrostatic protection, improving product quality, increasing production efficiency, and reducing production costs.
  • the figure shows a schematic diagram of an antistatic structure of an array substrate in the prior art
  • FIG. 2 is a schematic view showing an antistatic structure of an array substrate according to the present invention
  • 3 is a partial enlarged view of a gate line shorting bar in an antistatic structure of an array substrate according to the present invention
  • FIG. 4 is a partially enlarged view of a data line shorting bar in an antistatic structure of the array substrate of the present invention
  • Figure 6 is a cross-sectional view of B B in Figure 4.
  • FIG. 7 is an equivalent circuit diagram of an antistatic ring in an antistatic structure of an array substrate of the present invention. detailed description
  • the present invention has been described in the VA type display mode, but is not limited to the VA type display mode.
  • the present invention provides an antistatic structure of an array substrate, which specifically includes: an effective region 20 of the array substrate, a gate line shorting bar 30 disposed on the active region 20 side, and a device
  • the data line short-circuiting bar 40 on the other side of the effective area 20, the effective area 20 of the array substrate is provided with a plurality of mutually parallel rows of dipole lines 22 and a plurality of data lines 24 arranged in parallel with each other.
  • the gate line shorting bar 30 is electrically connected to one end of the plurality of pole lines 22, and the number i line shorting bar 40 is electrically connected to one end of the plurality of data lines 24.
  • the present invention uses only one gate.
  • the line shorting bar 30 shorts all the gate lines 22 and one data line shorting bar 40 shorts all the data lines 24 to protect the peripheral circuits of the panel, greatly shortens the shorting bar circuit, reduces the number of shorting bars, and reduces the number of shorting bars.
  • the number of lighting signals in the box process Preferably, the plurality of cabinet lines 22 and the plurality of data lines 24 are perpendicular to each other, that is, the effective region 20 of the array substrate is disposed on one side of the ⁇ -pole shorting bar 30 and the other side of the data line shorting bar 40 is disposed. adjacent.
  • An antistatic ring 26 is disposed at the beginning end of each of the drain lines 22 and each of the data lines 24, and the antistatic rings 26 are disposed around the effective area 20 of the array substrate to achieve antistatic protection of the devices inside the panel.
  • all of the antistatic rings 26 surrounding the active area 20 of the array substrate are electrically connected together to achieve a better antistatic effect.
  • the equivalent circuit diagram of each anti-static ring 26 is shown in FIG. 7, and the anti-static ring 26 is composed of two capacitors, and the two capacitors are connected in parallel.
  • the antistatic structure of the array substrate further includes: a plurality of first fan-out lines 52, a plurality of second fan-out lines 54, a plurality of data line contact pads 62, and a plurality of gate line contact pads 64, each of the first One end of the fan-out line 52 is electrically connected to a data line contact pad 62, and the other end is electrically connected to a data line 24, and one end of each of the second fan-out lines 54 is electrically connected to a gate line contact pad 64. The other end is electrically connected to a gate line 22.
  • the gate line is short.
  • the bar 30 is electrically connected to each gate line contact pad 64 to short all the gate lines 22; the data line shorting bar 40 and each data line contact pad 62 are electrically connected.
  • the first fan The number of outgoing lines 52 and the number of data line contact pads 62 are equal to the number of data lines 24; the number of second fan outgoing lines 54 and the number of drain line contact pads 64 are all equal to the number of gate lines 22.
  • One end of the gate line shorting bar 30 is provided with a gate signal input pad 32 for inputting a test signal; the data line shorting bar 40 is provided with a data signal input pad 42 for inputting a test signal, and further Complete the box lighting test.
  • the antistatic structure of the array substrate further includes a PLG (Propel Link Gate) trace 70 disposed at the edge of the array substrate, and is mainly used for transmitting the signal output from the integrated circuit to the 4-pole line.
  • PLG Propel Link Gate
  • the gate line shorting bar 30 includes: a substrate 41 , a first metal layer 42 formed on the substrate 41 , a gate insulating layer 43 covering the first metal layer 42 and the substrate 41 , and A passivation layer 45 on the gate insulating layer 43.
  • the first metal layer 42 of the gate line shorting bar 30 is directly formed in the same layer as the gate line 22, and is easily processed, which is advantageous for improving processing speed and cost.
  • the data line shorting bar 40 includes: a substrate 41, an *insulating layer 43 formed on the substrate 41, a second metal layer 44 on the cabinet insulating layer 43, and a second metal layer. Layer 44 and passivation layer 45 on cabinet insulating layer 43.
  • the second metal layer 44 of the data line shorting bar 40 is directly formed in the same layer as the data line 24, and is convenient to process, which is advantageous for improving processing speed and cost.
  • etchings such as channel etching and over-hole etching
  • plasma generated during via formation can be well avoided.
  • Abnormal discharge acts on the metal traces and over-tie of the short-circuit bar to better protect against static electricity, improve product quality, increase production efficiency, and reduce production costs.
  • the gate insulating layer 43 is preferably formed by silicon deposition, and the substrate 41 is preferably a glass substrate.
  • the antistatic structure of the array substrate of the present invention uses a gate shorting bar to short all the gate lines and a data line shorting bar to short all the data lines, greatly shortening the shorting bar circuit, and reducing
  • the number of the shorting bars is reduced, and the number of lighting signals in the process of forming the cartridge is reduced, and the first metal layer of the gate wire shorting bar is directly connected to the plurality of the shed and the polar wires, and then
  • the gate line shorting bar is electrically connected to the plurality of gate lines, and the second metal layer of the data line shorting bar is directly formed in the same layer as the plurality of data lines, so that the array substrate is fabricated
  • etchings such as channel etching and over-hole etching

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板的防静电结构，包括：阵列基板的有效区域（20）、一条栅极线短路棒（30）以及一条数据线短路棒（40）,阵列基板的有效区域（20）设有数根栅极线（22）及数根数据线（24），栅极线短路棒（30）电性连接于栅极线（22）的一端，数据线短路棒（40）电性连接于数据线（24）的一端。采用一条栅极线短路棒（30）将所有栅极线（22）短接以及一条数据线短路棒（40）将所有数据线（24）短接以很好地避免过孔形成时产生的等离子体异常放电对短路棒处的金属走线和过孔造成的静电损伤。

Description

本发明涉及显示技术领域， 尤其涉及一种阵列基板的防静电结构。 背景技术
液晶显示装置 ( Liquid Crystal Display, LCD )具有机身薄、 省电、 无 辐射等众多优点， 得到了广泛的应用。 现有巿场上的液晶显示装置大部分 为背光型液晶显示装置， 其包括壳体、 设于壳体内的液晶显示面板及设于 壳体内并相对液晶显示面板设置的背光模组 ( backlight module ) 。 液晶显 示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子， 并在两玻 璃基板上施加驱动电压来控制液晶分子的旋转， 从而将背光模组的光线折 射出来产生画面
静电 ( Electro Static discharge , ESD )在半导体生产行业一直是一个 悬而未决的问题， 静电会导致产品良率降低、 成本增加、 产能下降。 在液 晶显示装置制造工艺中， 静电也一直影响着液晶显示装置的品质， 尤其是 液晶显示面板的生产工艺。 静电的产生主要分为三大因素：
一是颗粒 （particle ) ， 任何一种颗粒都有可能造成器件损伤， 甚至产 品报废， 因此半导体制造工艺中， 管控颗粒是一项重要的工作。
二是制程条件和原材料， 在液晶显示面板工艺制程中， 沉积
( deposition ) 工序、 曝光 ( hoto ) 工序、 刻 （ etch ) 工序、 剥离 ( strip ) 以及清洁 （clean ) 工序等的工艺条件都会产生静电， 同时， 在该 些制程中所用到的原材料由于材料缺陷也会产生静电。
三是设计因素， 产品设.计的好坏直接影响了静电的情况。
为了提高产品品质， 降低生产成本， 在液晶显示面板的生产工艺会进 行静电防护工作。 该静电防护工作包括两大类： 一是液晶显示面板内部器 件保护， 主要是在液晶显示面板的线路（栅极（Gate ) 线和数据 （Data ) 线） 的始末端设计防静电环 （ESD ring ) ； 二是液晶显示面板外围电路保 护， 主要是保护阵列制程以及后端制程中静电对面板外围电路的损伤。
在现有的 TFT 阵列基板结构中， 膜层顺序为： 第一金属层
( Gate/Com ) 柵绝缘层 （ GI ) 有源层 （ Active 第二金属层 ( S/D ) —钝化层（PVX ) —透明导电层（ Indium Tin Oxides , ITO ) , 为 了控制产品的成本和良率， 通常在成盒 （ Cell ) 段制程完成切割 ( cutting ) 以后要对面板进行点灯判级， 进而将合格的液晶显示面板 ( panel )投入模组。
为了实现在成盒段制程能够点灯， 同时又不影响模组段的正常点灯， 通常会在阵列基板制作过程中， 在柵极线 （Gate线）和数据线 （Data线） 的端子处增加一些简单的测试电路， 即设置短路棒（shorting bar ) , 进而 实现成盒段制程的点灯， 减少静电释放现象。 目前的短路棒分为两种结 构： 镭射 ( trimming ) 结构和开关 ( switching ) 结构。 镭射结构是将栅极 线和数据线直接短接到短路棒上， 在成盒测试完成后， 需要采用激光镭射 的方式将短路棒与 *极线和数据线的端子断开； 开关结构是釆用开关将短 路棒信号输入到橋极线和数据线上。
就镭射结构而言， 目前采用 5条短路棒分别与相应的信号线连接， 其 中 3条短路棒连接数据线 (分别连接 R、 G、 B数据线 ) , 2条短路棒连接 栅极线（分别连接奇、 偶柵极线） ， 这些短路棒 100均通过.过孔与柵极线 或数据线 200连接， 如图 i所示。 但该技术在液晶显示面板的绝缘保护层 和有源层的千法蚀刻工艺 （如沟道千刻和过孔千刻） 中， 等离子体 ( plasma )异常放电仍会对短路棒 00 处金属交叠走线造成静电损伤， 影 响产品品质。 发明内容
本发明的目的在于提供一种阵列基板的防静电结构， 在阵列基板制造 过程中， 尤其是对绝缘保护层和有源层进行千法独刻 （如沟道千刻和过孔 干刻） 时， 可以很好地避免过孔形成时产生的等离子体异常放电对短路棒 处金属交叠走线和过孔造成的静电损伤， 提高产品品质， 提高生产效率， 降低生产成本。
为实现上述目的， 本发明提供一种阵列基板的防静电结构， 包括： 阵 列基板的有效区域、 一条设于所述有效区域一侧的栅极线短.路棒以及一条 设于所述有效区域另一侧的数据线短路棒， 该有效区域设置栅极线短路棒 的一侧与设置数据线短路棒的另一侧相邻， 所述阵列基板的有效区域设有 数根相互平行排列的栅极线及数根相互平行排列的数据线， 所述柵极线短 路棒电性连接于所述数根柵极线的一端， 所述数据线短路棒电性连接于所 述数根数据线的 端。
所述数根柵极线与数根数据线相互垂直， 每一柵极线和每一数据线的 始末端均设有一防静电环， 该些防静电环围绕该阵列基板的有效区域设 所述围绕该阵列基板有效区域的所有防静电环均电性连接在一起。 所述阵列基板的防静电结构还包括： 数根第一扇出线、 数根第二扇出 线、 数个数据线接触垫、 以及数个 *极线接触垫， 每一所述第一扇出线的 一端与一数据线接融垫电性连接， 另一端与一数据线电性连接， 每一所述 第二扇出线的一端与一栅极线接触垫电性连接， 另一端分别与一栅极线电 性连接。
所述栅极线短路棒与每一栅极线接触垫电性连接， 以将所有栅极线短 接； 所述数据线短路棒与每一数据线接触垫电性连接， 以将所有数据线短 接。
所述柵极线短路棒包括： 基板、 形成于基板上的第一金属层、 覆盖于 第一金属层及基板上的柵绝缘层、 位于柵绝缘层上的钝化层。
所述栅极线短路棒的第一金属层与所述数根柵极线同层制作且直接相 连， 进而将所述栅极线短路棒与所述数根柵极线电性连接。
所述数据线短路棒包括： 基板、 形成于基板上的柵绝缘层、 位于栅绝 缘层上的第二金属层、 以及覆盖于第二金属层与柵绝缘层上的钝化层。
所述数据线短路棒的第二金属层与所述数根数据线同层制作且直接相 连， 进而将所述数据线短路棒与所述数根数据线电性连接。
所述 *极线短路棒一端设有柵极信号输入悍盘， 用于输入测试信号； 所述数据线短路棒一端设有数据信号输入焊盘， 用于输入测试信号。
本发明还提供一种阵列基板的防静电结构， 包括： 阵列基板的有效区 域、 一条设于所述有效区域一侧的橋极线短路棒以及一条设于所述有效区 域另一侧的数据线短路棒， 该有效区域设置櫥极线短路棒的一侧与设置数 据线短路棒的另一侧相邻， 所述阵列基板的有效区域设有数根相互平行排 列的槲极线及数根相互平行排列的数据线， 所述 *极线短路棒电性连接于 所述数根 *极线的一端， 所述数据线短路棒电性连接于所述数根数据线的
—端：
其中， 所述数根栅极线与数根数据线相互垂直, 每一栅极线和每一数 据线的始末端均设有一防静电环， 该些防静电环围绕该阵列基板的有效区 域设置；
其中， 所述围绕该阵列基板有效区域的所有防静电环均电性连接在一 起；
还包括： 数根第一扇出线、 数根第二扇出线、 数个数据线接触垫。 以 及数个柵极线接触垫， 每一所述第一扇出线的一端与一数据线接触垫电性 连接， 另一端与一数据线电性连接， 每一所述第二扇出线的一端与一柵极 线接触垫电性连接， 另一端与一栅极线电性连接；
其中， 所述栅极线短路棒与每一 *极线接触垫电性连接， 以将所有槲 极线短接； 所述数据线短路棒与每一数据线接触垫电性连接， 以将所有数 据线短接；
其中， 所述柵极线短路棒包括： 基板、 形成于基板上的第一金属层、 覆盖于第一金属层及基板上的櫥绝缘层、 位于櫥绝缘层上的钝化层。
所述栅极线短路棒的第一金属层与所述数根 *极线同层制作且直接相 连， 进而将所述栅极线短路棒与所述数根柵极线电性连接。
所述数据线短路棒包括： 基板、 形成于基板上的柵绝缘层、 位于栅绝 缘层上的第二金属层、 以及覆盖于第二金属层与橋绝缘层上的钝化层。
所述数据线短路棒的第二金属层与所述数根数据线同层制作且直接相 连， 进而将所述数据线短路棒与所述数根数据线电性连接。
所述 *极线短路棒一端设有柵极信号输入悍盘， 用于输入测试信号； 所述数据线短路棒一端设有数据信号输入焊盘， 用于输入测试信号。
本发明的有益效果： 本发明的阵列基板的防静电结构， 仅采用一条栅 极线短路棒将所有柵极线短接以及一条数据线短路棒将所有数据线短接， 大大简化短路棒电路， 减少短路棒的个数， 减少成盒段制程中点灯信号的 个数， 且， 所述櫥极线短路棒的第一金属层与所述数根栅极线同层制作且 直接相连， 进而将所述柵极线短路棒与所述数根栅极线电性连接， 所述数 据线短路棒的第二金属层与所述数根数据线同层制作且直接相连， 如此， 在阵列基板制造过程中， 尤其是对绝缘保护层和有源层进行干法蚀刻 （：如 沟道千刻和过孔千刻） 时， 可以很好地避免过孔形成时产生的等离子体异 常放电对短路棒处的金属走线和过孔造成的静电损伤， 更好地起到静电保 护的作用， 提高产品品质， 提高生产效率， 降低生产成本。
为了能更进一步了解本发明的特征以及技术内容， 请参阔以下有关本 发明的详细说明与附图， 然而附图仅提供参考与说明用， 并非用来对本发 明加以限制。 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 为现有技术中阵列基板的防静电结构示意图；
图 2为本发明中阵列基板的防静电结构示意图； 图 3为本发明阵列基板的防静电结构中的栅极线短路棒局部放大图； 图 4为本发明阵列基板的防静电结构中的数据线短路棒局部放大图； 图 5为图 3中 A A的断面图；
图 6为图 4中 B B的断面图；
图 7为本发明阵列基板的防静电结构中的防静电环的等效电路图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果， 以下结合本发明 的优选实施例及其附图进行详细描述。
本发明以 VA型显示模式来进行说明， 但不限于 VA型显示模式。
请参阅图 2 至图 4， 本发明提供一种阵列基板的防静电结构， 具体包 括： 阵列基板的有效区域 20、 一条设于所述有效区域 20—侧的栅极线短 路棒 30以及一条设于所述.有效区域 20另一側的数据线短路棒 40, 所述阵 列基板的有效区域 20设有数根相互平行棑列的槲极线 22及数根相互平行 排列的数据线 24, 所述栅极线短路棒 30电性连接于所述数根极极线 22的 一端， 所述数 i 线短路棒 40电性连接于所述数根数据线 24的一端， 本发 明仅采用一条柵极线短路棒 30将所有柵极线 22短接以及一条数据线短路 棒 40将所有数据线 24短接， 以实现面板外围电路的保护， 大大简化短路 棒电路， 减少短路棒的个数， 减少成盒段制程中点灯信号的个数。 优选 的， 所述数根櫥极线 22与数根数据线 24相互垂直， 即阵列基板的有效区 域 20设置楣 -极线短路棒 30 的一侧与设置数据线短路棒 40 的另一侧相 邻。 每一槲极线 22和每一数据线 24的始末端均设有一防静电环 26, 该些 防静电环 26围绕该阵列基板的有效区域 20设置， 以实现面板内部器件的 防静电保护。 在本实施例中， 所述围绕该阵列基板有效区域 20 的所有防 静电环 26 均电性连接在一起， 以达到更好的防静电效果。 其中， 每一防 静电环 26的等效电路图如图 7所示， 防静电环 26由两电容构成， 且该两 电容通过并联方式相连接
所述阵列基板的防静电结构还包括： 数根第一扇出线 52 数根第二扇 出线 54、 数个数据线接触垫 62、 以及数个栅极线接触垫 64, 每一所述第 一扇出线 52的一端与一数据线接触垫 62电性连接， 另一端与一数据线 24 电性连接， 每一所述第二扇出线 54 的一端与一栅极线接触垫 64 电性连 接， 另一端与一柵极线 22电性连接。 所述柵极线短.路棒 30与每一栅极线 接触垫 64电性连接， 以将所有栅极线 22短接； 所述数据线短路棒 40与 每一数据线接触垫 62电性连接， 以将所有数据线 24短接。 其中， 第一扇 出线 52的数量及数据线接触垫 62的数量都等于数据线 24的数量； 第二 扇出线 54的数量及櫪极线接触垫 64的数量都等于栅极线 22的数量。 所 述柵极线短路棒 30一端设有柵极信号输入焊盘 32, 用于输入测试信号； 所述数据线短路棒 40 —端设有数据信号输入焊盘 42， 用于输入测试信 号， 进而完成成盒点灯测试。
所述阵列基板的防静电结构还包括一设置在阵列基板边缘的 PLG ( Propel Link Gate, 连接櫪极. )走线 70， 主要用于将集成电路输出的信号 传递至 4册极线。
请结合参阔图 5 , 所述栅极线短路棒 30 包括： 基板 41、 形成于基板 41 上的第一金属层 42、 覆盖于第一金属层 42 及基板 41 上的柵绝缘层 43、 位于柵绝缘层 43 上的钝化层 45。 在本实施例中， 所述栅极线短路棒 30的第一金属层 42与柵极线 22同层制作且直接相连， 加工方便, 有利于 提高加工速度及节省成本。 同样， 请结合参阅图 6, 所述数据线短路棒 40 包括： 基板 41、 形成于基板 41上的 *绝缘层 43、 位于櫥绝缘层 43上的 第二金属层 44、 以及覆盖于第二金属层 44 与櫥绝缘层 43 上的钝化层 45。 在本实施例中， 所述数据线短路棒 40 的第二金属层 44 与数据线 24 同层制作且直接相连， 加工方便， 有利于提高加工速度及节省成本。 如 此， 在阵列基板制造过程中， 尤其是对绝缘保护层和有源层进行千法蚀刻 (如沟道千刻和过孔千刻） 时， 可以很好地避免过孔形成时产生的等离子 体异常放电对短路棒处的金属走线和过扎造成的静电损伤， 更好地起到静 电保护的作用， 提高产品品质， 提高生产效率， 降低生产成本。
所述栅绝缘层 43 优选采用硅沉积形成， 所述基板 41 优选为玻璃基 板。
综上所述， 本发明的阵列基板的防静电结构， 采用一条槲极线短路棒 将所有柵极线短接以及一条数据线短路棒将所有数据线短接， 大大筒化短 路棒电路， 减少短路棒的个数， 减少成盒段制程中点灯信号的个数， 且， 所述栅极线短路棒的第一金属层与所述数根棚 ·极线同层制作且直接相连， 进而将所述栅极线短路棒与所述数根栅极线电性连接， 所述数据线短路棒 的第二金属层与所述数根数据线同层制作且直接相连， 如此， 在阵列基板 制造过程中， 尤其是对绝缘保护层和有源层进行千法蚀刻 （如沟道千刻和 过孔千刻） 时， 可以很好地避免过孔形成时产生的等离子体异常放电对短 路棒处的金属走线和过孔造成的静电损伤， 更好地起到静电保护的作用， 提高产品品质， 提高生产效率， 降低生产成本。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

权 利 要 求 一种阵列基板的防静电结构， 包括： 阵列基板的有效区域、 一条 设于所述有效区域一侧的橋极线短路棒以及一条设于所述有效区域另一倒 的数据线短路棒， 该有效区域设置柵极线短路棒的一侧与设置数据线短路 棒的另一侧相邻， 所述阵列基板的有效区域设有数根相互平行排列的栅极 线及数根相互平行排列的数据线， 所述 *极线短路棒电性连接于所述数根 耱极线的一端， 所述数据线短路棒电性连接于所述数根数据线的-端。
2、 如权利要求 所述的阵列基板的防静电结构， 其中， 所述数根栅 极线与数根数据线相互垂直， 每一橋极线和每一数据线的始末端均设有一 防静电环， 该些防静电环围绕该阵列基板的有效区域设置。
3、 如权利要求 2 所述的阵列基板的防静电结构， 其中， 所述围绕该 阵列基板有效区域的所有防静电环均电性连接在一起。
4、 如权利要求 1 所述的阵列基板的防静电结构， 还包括： 数根第一 扇出线、 数根第二扇出线、 数个数据线接触垫、 以及数个栅极线接触垫， 每一所述第一扇出线的一端与一数据线接触垫电性连接， 另一端与一数据 线电性连接， 每一所述第二扇出线的一端与一 *极线接触垫电性连接， 另 一端与一櫥极线电性连接。
5、 如权利要求 4 所述的阵列基板的防静电结构， 其中， 所述栅极线 短路棒与每一栅极线接触垫电性连接， 以将所有柵极线短接； 所述数据线 短路棒与每一数据线接触垫电性连接， 以将所有数据线短接。
6 如权利要求 i 所述的阵列基板的防静电结构， 其中， 所述栅极线 短路棒包括： 基板、 形成于基板上的第一金属层， 覆盖于第一金属层及基 板上的栅绝缘层、 位于栅绝缘层上的钝化层。
7、 如权利要求 6 所述的阵列基板的防静电结构， 其中， 所述栅极线 短路棒的第一金属层与所述数根棚 ·极线同层制作且直接相连， 进而将所述 柵极线短路棒与所述数根柵极线电性连接。
8、 如权利要求 1 所述的阵列基板的防静电结构， 其中， 所述数据线 短路棒包括： 基板、 形成于基板上的栅绝缘层、 位于櫥绝缘层上的第二金 属层、 以及覆盖于第二金属层与栅绝缘层上的钝化层。
9、 如权利要求 8 所述的阵列基板的防静电结构， 其中， 所述数据线 短路棒的第二金属层与所述数根数据线同层制作且直接相连， 进而将所述 数据线短路棒与所述数根数据线电性连接。 10、 如权利要求 1 所述的阵列基板的防静电结构， 其中， 所述槲极线 短路棒一端设有柵极信号输入焊盘， 用于输入测试信号； 所述数据线短路 棒一端设有数据信号输入焊盘， 用于输入测试信号。
】1、 一种阵列基板的防静电结构， 包括： 阵列基板的有效区域、 一条 设于所述有效区域一侧的棚'极线短路棒以及一条设于所述有效区域另一倒 的数据线短路棒， 该有效区域设置柵极线短路棒的一侧与设置数据线短路 棒的另一侧相邻， 所述阵列基板的有效区域设有数根相互平行排列的栅极 线及数根相互平行排列的数据线， 所述 *极线短路棒电性连接于所述数根 耱极线的- 端， 所述数据线短路棒电性连接于所述数根数据线的-端； 其中， 所述数根栅极线与数根数据线相互垂直, 每一栅极线和每一数 据线的始末端均设有一防静电环， 该些防静电环围绕该阵列基板的有效区 域设置；
其中， 所述围绕该阵列基板有效区域的所有防静电环均电性连接在一
4己it，,
还包括： 数根第一扇出线、 数根第二扇出线、 数个数据线接触垫。 以 及数个柵极线接触垫， 每一所述第一扇出线的一端与一数据线接触垫电性 连接， 另一端与一数据线电性连接， 每一所述第二扇出线的一端与一柵极 线接触垫电性连接， 另一端与一栅极线电性连接；
其中， 所述柵极线短路棒与每一栅极线接触垫电性连接， 以将所有柵 极线短接； 所述数据线短路棒与每一数据线接触垫电性连接， 以将所有数 据线短接；
其中， 所述柵极线短路棒包括： 基板、 形成于基板上的第一金属层、 覆盖于第一金属层及基板上的櫥绝缘层、 位于櫥绝缘层上的钝化层。
12 , 如权利要求 11 所述的阵列基板的防静电结构， 其中， 所述栅极 线短路棒的第一金属层与所述数根 *极线同层制作且直接相连， 进而将所 述栅极线短路棒与所述数根栅极线电性连接。
13、 如权利要求 1 1 所述的阵列基板的防静电结构， 其中， 所述数据 线短路棒包括： 基板， 形成于基板上的柵绝缘层、 位于柵绝缘层上的第二 金属层、 以及覆盖于第二金属层与櫥绝缘层上的钝化层。
14、 如权利要求 13 所述的阵列基板的防静电结构， 其中， 所述数据 线短路棒的第二金属层与所述数根数据线同层制作且直接相连， 进而将所 述数据线短路棒与所述数根数据线电性连接。
】5、 如权利要求 11 所述的阵列基板的防静电结构， 其中， 所述栅极 线短路棒一端设有柵极信号输入焊盘， 用于输入测试信号； 所述数据线短 端设有数据信号输入焊盘， 用于输入测试信号
PCT/CN2014/070966 2013-12-26 2014-01-21 阵列基板的防静电结构 Ceased WO2015096247A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/347,596 US9165950B2 (en) 2013-12-26 2014-01-21 Anti-static structure of array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310733696.4 2013-12-26
CN201310733696.4A CN103676255B (zh) 2013-12-26 2013-12-26 阵列基板的防静电结构

Publications (1)

Publication Number Publication Date
WO2015096247A1 true WO2015096247A1 (zh) 2015-07-02

Family

ID=50314307

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/070966 Ceased WO2015096247A1 (zh) 2013-12-26 2014-01-21 阵列基板的防静电结构

Country Status (3)

Country Link
US (1) US9165950B2 (zh)
CN (1) CN103676255B (zh)
WO (1) WO2015096247A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104035217B (zh) * 2014-05-21 2016-08-24 深圳市华星光电技术有限公司 显示器阵列基板的外围测试线路以及液晶显示面板
CN104049392B (zh) * 2014-06-10 2017-01-18 京东方科技集团股份有限公司 防止显示面板异常放电的装置和显示面板制备系统
CN105427823A (zh) * 2016-01-04 2016-03-23 京东方科技集团股份有限公司 一种栅极驱动电压的调节方法、调节装置及显示装置
CN106782243B (zh) * 2016-12-30 2020-12-04 上海天马微电子有限公司 一种显示基板、显示面板及显示装置
CN109064902B (zh) * 2018-09-20 2020-12-11 武汉天马微电子有限公司 一种显示面板及显示装置
CN110112169B (zh) * 2019-04-22 2021-04-27 Tcl华星光电技术有限公司 显示面板及其制作方法
CN110187575B (zh) 2019-05-28 2020-12-18 昆山国显光电有限公司 阵列基板及阵列基板母板
CN110767131B (zh) * 2019-10-15 2023-03-24 Tcl华星光电技术有限公司 液晶显示面板的点灯检测方法、点灯治具
CN112018086B (zh) * 2020-07-27 2022-03-22 惠科股份有限公司 短接棒及其制作方法、阵列基板和显示装置
CN112259563B (zh) * 2020-10-28 2023-02-28 武汉华星光电技术有限公司 显示面板及显示装置
CN115167021B (zh) * 2022-08-05 2023-07-25 苏州华星光电技术有限公司 显示面板的检测方法及检测装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060015176A (ko) * 2004-08-13 2006-02-16 삼성전자주식회사 박막 트랜지스터 표시판
CN1928681A (zh) * 2005-09-05 2007-03-14 中华映管股份有限公司 薄膜晶体管阵列基板、其静电放电保护元件及其制造方法
CN101135820A (zh) * 2006-09-01 2008-03-05 北京京东方光电科技有限公司 一种tft lcd面板静电放电保护电路
US8575617B2 (en) * 2011-06-27 2013-11-05 Samsung Display Co., Ltd. Thin film transistor array having improved connectivity between shorting bar and data lines

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL194873C (nl) * 1992-08-13 2003-05-06 Oki Electric Ind Co Ltd Dunnefilmtransistorenreeks en daarvan gebruikmakende vloeibare kristalweergeefinrichting.
TW440736B (en) * 1997-10-14 2001-06-16 Samsung Electronics Co Ltd Liquid crystal displays and manufacturing methods thereof
KR20060018312A (ko) * 2004-08-24 2006-03-02 삼성전자주식회사 표시기판 및 이를 갖는 표시장치
US20070030408A1 (en) * 2005-08-08 2007-02-08 Kuang-Hsiang Lin Liquid crystal display panel, thin film transistor array substrate and detection methods therefor
KR101542395B1 (ko) * 2008-12-30 2015-08-06 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
KR101614900B1 (ko) * 2009-10-27 2016-04-25 삼성디스플레이 주식회사 표시 패널
CN102967978B (zh) * 2012-12-18 2015-08-26 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060015176A (ko) * 2004-08-13 2006-02-16 삼성전자주식회사 박막 트랜지스터 표시판
CN1928681A (zh) * 2005-09-05 2007-03-14 中华映管股份有限公司 薄膜晶体管阵列基板、其静电放电保护元件及其制造方法
CN101135820A (zh) * 2006-09-01 2008-03-05 北京京东方光电科技有限公司 一种tft lcd面板静电放电保护电路
US8575617B2 (en) * 2011-06-27 2013-11-05 Samsung Display Co., Ltd. Thin film transistor array having improved connectivity between shorting bar and data lines

Also Published As

Publication number Publication date
CN103676255B (zh) 2016-02-24
CN103676255A (zh) 2014-03-26
US9165950B2 (en) 2015-10-20
US20150187801A1 (en) 2015-07-02

Similar Documents

Publication Publication Date Title
WO2015096247A1 (zh) 阵列基板的防静电结构
CN106783842B (zh) 一种静电保护电路、阵列基板、显示面板及显示装置
CN103500741B (zh) 阵列基板的防静电结构
WO2014153854A1 (zh) 触控显示屏及触控显示装置
CN106206746B (zh) 薄膜晶体管、goa电路、显示基板和显示装置
WO2017071233A1 (zh) 制作阵列基板的方法和阵列基板
CN109727972B (zh) 显示母板及其制备方法、显示基板及显示装置
WO2015039389A1 (zh) 阵列基板及其制作方法、显示装置
CN114639686B (zh) 一种阵列基板及其制备方法、显示面板、显示装置
US12615842B2 (en) Thin-film transistor and arrangement thereof and method for manufacturing same
CN103441119B (zh) 一种制造esd器件的方法、esd器件和显示面板
CN103926769A (zh) 一种阵列基板、显示面板及显示器
WO2024109061A1 (zh) 一种显示面板及显示装置
CN108170317A (zh) 阵列基板
WO2014176876A1 (zh) 显示面板及其制作方法、液晶显示器
WO2021056549A1 (zh) 阵列基板及其制作方法、母板以及显示装置
CN108257974B (zh) 阵列基板、显示装置以及制备阵列基板的方法
CN202421683U (zh) 一种tft阵列基板的中间产品、阵列基板及显示器件
CN101350356A (zh) 主动元件阵列基板
JP5279574B2 (ja) 液晶表示装置
CN209119104U (zh) 一种阵列基板、柔性显示面板、拼接屏
CN111710301A (zh) 一种显示面板及其制备方法和修复方法、显示装置
CN106653746B (zh) 一种阵列基板和显示装置
CN110187579A (zh) 一种显示面板和显示装置
WO2014180051A1 (zh) 液晶显示面板的短接条结构及液晶显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14347596

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14873227

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14873227

Country of ref document: EP

Kind code of ref document: A1