WO2015081672A1 - 电极结构及制备方法、阵列基板及制备方法和显示装置 - Google Patents

电极结构及制备方法、阵列基板及制备方法和显示装置 Download PDF

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Publication number
WO2015081672A1
WO2015081672A1 PCT/CN2014/078534 CN2014078534W WO2015081672A1 WO 2015081672 A1 WO2015081672 A1 WO 2015081672A1 CN 2014078534 W CN2014078534 W CN 2014078534W WO 2015081672 A1 WO2015081672 A1 WO 2015081672A1
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Prior art keywords
electrode
electrode structure
isolation layer
via hole
display area
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PCT/CN2014/078534
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English (en)
French (fr)
Inventor
张敏
金玟秀
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to US14/429,971 priority Critical patent/US9448445B2/en
Publication of WO2015081672A1 publication Critical patent/WO2015081672A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an electrode structure and a preparation method, an array substrate, a preparation method, and a display device. Background technique
  • Liquid crystal display (LCD: Li qui d Crystal Di splay) has become a mainstream product in flat panel displays due to its small size, low power consumption, and no radiation. At present, with the wide application of high-resolution small-size liquid crystal displays, low-power liquid crystal displays have become the trend.
  • the array substrate is an important part of the liquid crystal display and is also a key component for display. With the development of technology, in order to reduce the power consumption of liquid crystal displays, many improvements have been made to the array substrate.
  • HADS Hi gh Advanced Super
  • the array substrate is subjected to signal testing after preparation.
  • the signal test structure is formed in the non-display area of the array substrate and is prepared along with the display structure in the display area of the array substrate.
  • the partial layer structure in the display area also extends to the non-display area, such as: an organic insulating layer, a gate insulating layer, a passivation layer, etc., so that no additional process steps are added during preparation, and the non-display area is reduced.
  • the gap of the display area facilitates the exchange of signals between the non-display area and the display area.
  • the signal test includes the gate line signal test and the data line signal test, that is, the pass
  • the over-test structure adds a gate line test signal to the gate line, and a data line test signal is added to the data line to detect whether the array substrate can operate normally.
  • the gate line test signal is added through the gate line signal input electrode 21 disposed in the non-display area 02, and the data line test signal passes through the data line signal input electrode 22 disposed in the non-display area 02.
  • the gate line signal input electrode 21 is disposed in the same layer as the gate line.
  • the gate line signal input electrode 21 is sequentially provided with a gate insulating layer 8 extending from the display area 01, an organic insulating layer 9 and a passivation layer 10, on the passivation layer 10.
  • a first lead-in electrode 61 is formed, and the first lead-in electrode 61 is electrically connected to the gate line signal input electrode 21 through a via hole 010 penetrating through the gate insulating layer 8, the organic insulating layer 9, and the passivation layer 10;
  • the data line signal input electrode 22 is disposed in the same layer as the data line, and an organic insulating layer 9 and a passivation layer 10 extending from the display area 01 are sequentially disposed above the data line signal input electrode 22, and a second lead-in electrode 62 is formed on the passivation layer 10, the first The second lead-in electrode 62 is electrically connected to the data line signal input electrode 22 through a via 020 extending through the organic insulating layer 9 and the passivation layer 10.
  • an organic insulating layer via hole is first formed in the organic insulating layer 9;
  • a passivation layer via hole is formed in the passivation layer 10 and a gate insulating layer via hole is formed in the gate insulating layer 8 by a dry etching process. Due to the opening diameter of the passivation layer 10 corresponding to the exposed developing portion where the via is to be formed (ie, the passivation layer)
  • the opening diameter r) of the via hole in 10 is larger than the opening diameter R of the via hole of the organic insulating layer, so when the pattern of the passivation layer via hole and the gate insulating layer via hole is formed by a dry etching process, the organic insulating layer is easily passed.
  • the walls of the holes are again partially etched away to form a notch 14 in the via of the insulating layer of the machine as shown in FIG. This may cause a virtual connection or disconnection with the gate line signal input electrode 21 when the first lead-in electrode 61 extends into the via hole of the organic insulating layer during the subsequent preparation of the first lead-in electrode 61, thereby further As a result, the test signal cannot be input, and the array substrate cannot be tested normally.
  • the present invention provides an electrode for the above technical problems existing in the prior art. Structure and preparation method, array substrate, preparation method and display device.
  • the electrode structure completely covers the hole wall of the second via hole in the second isolation layer, so that the hole wall of the second via hole in the second isolation layer is not damaged, thereby ensuring introduction
  • the electrode and the body electrode can be electrically connected well, ensuring the normal introduction of the signal.
  • the present invention provides an electrode structure including an introduction electrode and a body electrode, a first isolation layer and a second isolation layer are disposed between the introduction electrode and the body electrode, and the first isolation layer is provided with a first a second via hole is defined in the second isolation layer, and the hole axis of the first via hole and the hole axis of the second via hole are on the same straight line passing through the body electrode, thereby passing through the first
  • the via hole and the second via hole expose a portion of the body electrode, the lead-in electrode being electrically connected to the body electrode through the portion of the body electrode exposed by the first via hole and the second via hole, wherein
  • the diameter of the first via hole is smaller than the diameter of the second via hole, and the first isolation layer further extends to completely cover the hole wall of the second via hole.
  • a third isolation layer is further disposed between the body electrode and the second isolation layer, and a third via hole is defined in the third isolation layer, and a hole axis of the third via hole is
  • the hole axes of the second via holes are on the same straight line, and the diameter of the third via holes is less than or equal to the diameter of the first via holes, thereby exposing the part of the body electrodes through the third via holes,
  • the first isolation layer also extends to cover an upper surface of the third isolation layer exposed by the second via.
  • the second isolation layer is formed of a polyimide epoxy material
  • the first isolation layer and the third isolation layer are formed of a silicon nitride material
  • the introduction electrode is made of indium tin oxide or doped Indium zinc oxide material is formed.
  • the present invention also provides an array substrate, including a substrate substrate and a plurality of electrode structures disposed above the substrate substrate, the array substrate includes a display area and a non-display area, and the electrode structure adopts the above electrode structure.
  • the electrode structure is disposed in the display area and
  • the array substrate further includes a plurality of intersecting gate lines and data lines, the gate lines and the data lines dividing the display area into a plurality of pixel areas, and each of the pixel areas is provided with a thin film transistor
  • the thin film transistor includes a gate, a gate insulating layer, a source and a drain, the gate is electrically connected to the gate line, and the source is electrically connected to the data line
  • an organic insulating layer and a passivation layer are further disposed above the thin film transistor, and a common electrode is further disposed above the passivation layer, and the gate insulating layer, the organic insulating layer, and the passivation layer are further At the same time extending to the non-display area.
  • the electrode structure is disposed in the non-display area, and the electrode structure includes a first electrode structure and a second electrode structure, and the gate line is electrically connected to the body electrode in the first electrode structure, and extends The passivation layer to the non-display area as a first isolation layer in the first electrode structure, the organic insulating layer extending to the non-display area as a second in the first electrode structure a spacer layer extending to the gate insulating layer of the non-display area as a third isolation layer in the first electrode structure, and a lead-in electrode in the first electrode structure is used for introducing a gate line test signal; and / Or the data line is electrically connected to the body electrode in the second electrode structure, and the passivation layer extending to the non-display area serves as a first isolation layer in the second electrode structure, extending to the The organic insulating layer of the non-display area serves as a second isolation layer in the second electrode structure, and the lead-in electrode in the second electrode structure is used to introduce
  • the electrode structure is disposed in the display area as a third electrode structure, and the base substrate is further provided with a common electrode line, and the common electrode line serves as a body electrode in the third electrode structure.
  • the passivation layer serves as a first isolation layer in the third electrode structure
  • the organic insulation layer serves as a second isolation layer in the third electrode structure
  • the gate insulation layer serves as the third electrode structure a third isolation layer
  • the common electrode serves as an introduction electrode in the third electrode structure
  • the introduction electrode is used to access a common reference voltage.
  • the invention also provides a display device comprising the above array substrate.
  • the invention also provides a preparation method of an electrode structure, comprising the steps of:
  • first isolation layer Forming a first isolation layer on the first substrate substrate on which the body electrode and the second isolation layer are formed, and forming a first via hole in the first isolation layer by a patterning process, so that the first The hole axis of the via hole is on the same line as the hole axis of the second via hole, and The diameter of the first via hole is smaller than the diameter of the second via hole to expose a portion of the body electrode through the first via hole and the second via hole, and the first isolation layer is opposite to the first via layer
  • the walls of the two via holes are completely covered;
  • the step of forming the first via hole in the first isolation layer by using a patterning process further comprises: forming a third via hole in the third isolation layer while forming the first via hole by one patterning process, so that The diameter of the third via hole is less than or equal to the diameter of the first via hole, thereby exposing the portion of the body electrode through the third via hole, and the first isolation layer is further separated from the third via hole The layer is completely covered by the upper surface exposed by the second via.
  • the present invention also provides a method for fabricating an array substrate, the array substrate comprising a display region and a non-display region, wherein a plurality of electrodes are formed in the display region and/or the non-display region by using the preparation method of the electrode structure described above. structure.
  • a gate and a gate line are formed in the display area;
  • a source/drain metal layer including a source, a drain, and a data line
  • the gate insulating layer, the organic insulating layer and the passivation layer are simultaneously extended to the non-display area.
  • the electrode structure is formed in the non-display area, and the electrode structure includes a first electrode structure and a second electrode structure, wherein the body electrode in the first electrode structure is electrically connected to the gate line,
  • the passivation layer extending to the non-display area as a first isolation layer in the first electrode structure, and the organic insulating layer extending to the non-display area as a first in the first electrode structure
  • Two isolation layers extending to the non-display area
  • the gate insulating layer also serves as a third isolation layer in the first electrode structure, the lead-in electrode in the first electrode structure is used to introduce a gate line test signal; and/or, in the second electrode structure
  • the body electrode is electrically connected to the data line, and the passivation layer extending to the non-display area is used as a first isolation layer in the second electrode structure, and extends to the organic insulating layer of the non-display area As a second isolation layer in the second electrode structure, a lead-in electrode in the second electrode structure is used to
  • the gate line is formed of the same material as the body electrode in the first electrode structure and formed in the same patterning process, and/or the data line and the body electrode in the second electrode structure The same material is used and formed in the same patterning process.
  • the electrode structure is formed as a third electrode structure in the display area, and a common electrode line is formed in the display area, and the common electrode line is used as a body electrode in the third electrode structure, a passivation layer as a first isolation layer in the third electrode structure, the organic insulation layer as a second isolation layer in the third electrode structure, the gate insulation layer as a third electrode structure A third isolation layer, the common electrode serves as an introduction electrode in the third electrode structure for accessing a common reference voltage.
  • the common electrode line and the gate are made of the same material and are formed in the same patterning process; the lead-in electrode in the third electrode structure and the common electrode are made of the same material and are in the same composition Formed in the process.
  • the electrode structure provided by the present invention by completely covering the first isolation layer with the hole wall of the second via hole in the second isolation layer, thereby making the hole wall of the second via hole in the second isolation layer It will not be damaged, and thus ensure that the lead-in electrode and the body electrode can be electrically connected well, ensuring the normal introduction of the signal.
  • the array substrate with the electrode structure can normally introduce test signals and display signals through the electrode structure, so that the array substrate can be normally tested and displayed, which not only improves the test stability of the array substrate, but also improves the display effect of the array substrate. .
  • the display device using the array substrate can not only perform the test normally, but also improve the display effect.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a schematic structural view showing a defect in a test portion of a gate line signal in FIG. 1; 3 is a schematic structural view of an electrode structure according to Embodiment 1 of the present invention; FIG. 4 is a schematic structural view of an electrode structure according to Embodiment 2 of the present invention;
  • Embodiment 3 is a schematic structural view of an array substrate in Embodiment 3 of the present invention.
  • Figure 6 is a schematic structural view of an array substrate in Embodiment 5 of the present invention.
  • the patterning process includes a photolithography process and an auxiliary process such as printing, inkjet, etc., wherein the photolithography process refers to etching using a photoresist, a mask, an exposure machine, etc., including exposure, development, etching, and the like.
  • the photolithography process refers to etching using a photoresist, a mask, an exposure machine, etc., including exposure, development, etching, and the like.
  • This embodiment provides an electrode structure, as shown in FIG. 3, including the lead-in electrode 6 and the body electrode 2.
  • the first electrode layer 2 is disposed on the first substrate 1 , and the first isolation layer 5 and the second isolation layer 4 are disposed between the introduction electrode 6 and the body electrode 2 .
  • a second via 41 is opened in the second isolation layer 4.
  • the hole axis of the first via hole 51 and the hole axis of the second via hole 41 are on the same straight line passing through the body electrode 2, thereby exposing a part of the body electrode 2 through the first via hole 51 and the second via hole 41.
  • the lead-in electrode 6 passes through a portion of the body electrode 2 exposed by the first via 51 and the second via 41 It is electrically connected to the body electrode 2.
  • the diameter of the first via 51 is smaller than the diameter of the second via 41, and the first isolation layer 5 also extends to the wall of the hole covering the second via 41.
  • the second isolation layer 4 may be formed of a polyimide epoxy material
  • the first isolation layer 5 may be formed of a silicon nitride material
  • the introduction electrode 6 may be formed of indium tin oxide or an indium-doped zinc oxide material.
  • the embodiment further provides a method for preparing the above electrode structure, and the specific steps of the preparation method are as follows:
  • Step S1 The body electrode 2 is formed on the first base substrate 1 by a patterning process.
  • the second via 41 is exposed using a mask, and the corresponding pattern for forming the second via 41 on the mask is circular and has a diameter R. Accordingly, the diameter of the second via hole 41 formed is also R.
  • Step S3 A first isolation layer 5 is formed on the first substrate 1 on which the step S2 is completed. Specifically, the first isolation layer 5 is coated on the first substrate 1 and the first via 51 is formed in the first isolation layer 5 by a patterning process, so that the hole axis of the first via 51 and the first The hole axes of the two via holes 41 are on the same straight line.
  • the first via 51 is exposed using a mask, and the corresponding pattern for forming the first via 51 on the mask is circular with a diameter r (r ⁇ R).
  • the first via 51 formed is also of diameter r.
  • the first via 51 is formed such that the first isolation layer 5 covers the hole wall of the second via hole 41 while exposing a circular portion having a diameter r in the upper surface of the body electrode 2.
  • Step S4 forming the lead-in electrode 6 on the first base substrate 1 on which the step S3 is completed, so that the lead-in electrode passes through the upper surface of a part of the body electrode 2 exposed by the first via 51 and the second via 41, and the body The electrodes 2 are electrically connected.
  • This embodiment provides an electrode structure.
  • the electrode structure in this embodiment is further provided with a third isolation layer 3 between the body electrode 2 and the second isolation layer 4.
  • the third isolation layer 3 is provided with a third via hole 31 such that the hole axis of the third via hole 31 and the hole axis of the second via hole 41 are on the same straight line, and the diameter thereof is less than or equal to the diameter R of the first via hole 51.
  • a portion of the body electrode 2 is also exposed through the third via 31, and the first isolation layer 5 also extends to cover the upper surface of the third isolation layer 3 exposed by the second via 41.
  • the third isolation layer 3 is formed of a silicon nitride material.
  • the preparation steps of the electrode structure in the embodiment further include:
  • step S1 further includes: step S1': depositing or coating the third isolation layer 3 on the first substrate 1 on which the step S1 is completed.
  • Step S3 further includes: forming a third via 31 in the third spacer layer 3 while forming the first via 51 in the first spacer layer 5 by using one patterning process.
  • the first via 51 and the third via 31 are formed in one etching process. That is, after the first via 51 is exposed by the mask, the first via 51 and the third via 31 are simultaneously formed by one etching. Therefore, the first via 51 and the third via 31 have the same diameter, that is, both have a diameter of ⁇ .
  • the diameter of the third via 31 is generally slightly smaller than the diameter of the first via 51 due to operational reasons in the actual fabrication process.
  • the present embodiment provides an array substrate, as shown in FIG. 5, comprising a base substrate 1 1 and a plurality of electrode structures disposed above the base substrate 11 .
  • the array substrate includes a display area 01 and a non-display area 02, and the plurality of electrode structures disposed in the non-display area 02 employ the electrode structures of the embodiments 1 and 2, respectively.
  • a plurality of intersecting gate lines and data lines (not shown in FIG. 5) divide the display area 01 into a plurality of pixel regions, and each of the pixel regions is provided with a thin film transistor 7, and the thin film transistor 7 includes A gate electrode 71, a gate insulating layer 8, an active layer 74, a source electrode 72, and a drain electrode 73.
  • a gate insulating layer 8 is disposed between the gate 71 and the source 72 to isolate the gate 71 from the source 72.
  • the gate electrode 71 is electrically connected to the gate line and disposed in the same layer.
  • the source electrode 72 is electrically connected to the data line and disposed in the same layer.
  • the thin film transistor 7 is further provided with an organic insulating layer 9 and a passivation layer 10, which are passivated.
  • a common electrode 12 is also disposed above the layer 10.
  • the gate insulating layer 8, the organic insulating layer 9, and the passivation layer 10 also extend to the non-display area 02 at the same time.
  • the electrode structure is disposed in the non-display area 02, and the electrode structure includes the first electrode structure 001 and the second electrode structure 002.
  • the first electrode structure 001 adopts the electrode structure in Embodiment 2
  • the second electrode structure 002 adopts the electrode structure in Embodiment 1.
  • the gate line is electrically connected to the body electrode (ie, the gate line signal input electrode 21) in the first electrode structure 001
  • the passivation layer 10 also extends to the non-display area 02 and serves as the first isolation layer in the first electrode structure 001
  • organic The insulating layer 9 also extends to the non-display area 02 and serves as a second isolation layer in the first electrode structure 001.
  • the gate insulating layer 8 also extends to the non-display area 02 and serves as a third isolation layer in the first electrode structure 001. Electrode (ie the first incoming electricity Pole 61) is used to introduce the gate line test signal.
  • the data line is electrically connected to the body electrode (ie, the data line signal input electrode 22) in the second electrode structure 002, and the passivation layer 10 also extends to the non-display area 02 and serves as the first isolation layer in the second electrode structure 002, organic
  • the insulating layer 9 also extends to the non-display area 02 and serves as a second isolation layer in the second electrode structure 002, and the introduction electrode (i.e., the second introduction electrode 62) is used to introduce a data line test signal.
  • the body electrode in the first electrode structure 001 (ie, the gate line signal input electrode 21) and the gate electrode 71 in the display area 01 are made of the same material and formed in the same patterning process, that is, in the first electrode structure 001.
  • the body electrode is formed in the same layer of the array substrate as the gate 71 and the gate line in the display region 01.
  • the substrate substrate 11 of the array substrate in this embodiment corresponds to the first substrate substrate 1 of the electrode structure of the embodiment 2 shown in Fig. 4.
  • the body electrode (ie, the data line signal input electrode 22) in the second electrode structure 002 is made of the same material as the source 72 in the display region 01, and is formed in the same patterning process, that is, the body electrode in the second electrode structure 002.
  • the source 72 and the data line in the display area 01 are formed in the same layer of the array substrate.
  • the substrate substrate 1 1 in which the gate insulating layer 8 is provided in the array substrate of this embodiment corresponds to the first substrate substrate 1 of the electrode structure of the embodiment 1 shown in Fig. 3.
  • the lead-in electrode of the first electrode structure 001 (ie, the first lead-in electrode 61) and the lead-in electrode of the second electrode structure 002 (ie, the second lead-in electrode 62) are made of the same material and are the same as the common electrode 12 in the display region 01. Formed in the patterning process, that is, the lead-in electrode in the first electrode structure 001 and the lead-in electrode in the second electrode structure 002 are formed in the same layer as the common electrode 12 in the array substrate.
  • the arrangement is such that the first electrode structure 001 and the second electrode structure 002 disposed in the non-display area 02 of the array substrate can follow the display structures (such as the thin film transistor 7, the gate line and the data line) in the display area 01 on the array substrate.
  • the preparation is prepared together without adding additional process steps, and is advantageous for reducing the gap between the non-display area 02 and the display area 01, and facilitating the exchange of signals between the non-display area 02 and the display area 01.
  • first lead-in electrode 61 of the first electrode structure 001 and the second lead-in electrode 62 of the second electrode structure 002 and the common electrode 12 are formed in the same layer of the array substrate, the first electrode structure 001 An introduction electrode 61, any of the second lead-in electrode 62 of the second electrode structure 002 and the common electrode 12 are not connected to each other, that is, electrically isolated from each other. The reason is that the common electrode 12 is used to input a common reference voltage during display.
  • the signal, the first lead-in electrode 61 of the first electrode structure 001 is used to input the gate line test signal, and the second lead-in electrode 62 of the second electrode structure 002 is used to input the data line test signal during the test.
  • the common voltage signal at the time of display and the gate line test signal and the data line test signal at the time of test are separately provided without mutual interference.
  • the first electrode structure 001 and the second electrode structure 002 each include a plurality of, and the plurality of first electrode structures 001 or the plurality of second electrode structures 002 are disposed at a certain interval from each other.
  • Each of the first electrode structures 001 corresponds to one gate line, and the lead-in electrodes of the plurality of first electrode structures 001 (ie, the first lead-in electrodes 61) are electrically connected to each other.
  • Such a setting facilitates the introduction of the gate line test signal, that is, as long as the gate line test signal is input on the first lead-in electrode 61 of the first electrode structure 001, all the body electrodes in the first electrode structure 001 (ie, the gate line signal)
  • the input electrode 21) can obtain the gate line test signal through the first lead-in electrodes 61 connected to each other, so that it is not necessary to input the gate line test signal on each of the first electrode structures 001.
  • Each of the second electrode structures 002 corresponds to one data line, and the lead-in electrodes of the plurality of second electrode structures 002 (ie, the second lead-in electrodes 62) are electrically connected to each other.
  • the arrangement is also advantageous for the introduction of the data line test signal, that is, as long as the data line test signal is input on the second lead-in electrode 62 of a second electrode structure 002, the body electrodes (ie, the data lines) of all the second electrode structures 002
  • the signal input electrode 22 can obtain the data line test signal through the second lead-in electrodes 62 connected to each other, so that it is not necessary to input the data line test signal on each of the second electrode structures 002.
  • FIG. 5 is only a schematic structural diagram of the array substrate in the embodiment, and the thin film transistor 7, the first electrode structure 001 and the second electrode structure 002 of the actual array substrate cannot be simultaneously cut out on one cutting plane.
  • Figure 5 is only a schematic representation of these structures in a diagram so that the structural relationship between them can be more clearly explained.
  • the embodiment further provides a method for preparing the above array substrate, comprising forming the first electrode structure 001 and the second electrode structure 002 in the non-display area 02 by using the electrode structure preparation method in Embodiment 1 or 2.
  • the method further includes: forming a gate electrode 71 and a gate line in the display region 01; forming a gate insulating layer 8 and extending the gate insulating layer 8 to the non-display region 02 as a third isolation layer of the first electrode structure 001; Source and drain metal layers of the source 72, the drain 73 and the data lines, and the active layer 74 are formed; the organic insulating layer 9 and the passivation layer 10 are formed, and the organic insulating layer is formed The layer 9 and the passivation layer 10 extend to the non-display area 02 to serve as the second isolation layer and the first isolation layer of the first electrode structure 001 and the second electrode structure 002, respectively; the common electrode 12 is formed.
  • the body electrode (ie, the gate line signal input electrode 21) in the first electrode structure 001 is formed of the same material as the gate electrode 71 and formed in the same patterning process; the body electrode (ie, the data line) in the second electrode structure 002
  • the signal input electrode 22) is made of the same material as the source 72 and formed in the same patterning process.
  • the gate line is electrically connected to the body electrode of the first electrode structure 001, and the data line is electrically connected to the body electrode of the second electrode structure 002.
  • the preparation step of the first electrode structure 001 adopts the preparation step of the electrode structure in Embodiment 2
  • the preparation step of the second electrode structure 002 adopts the preparation step of the electrode structure in Embodiment 1.
  • the gate line test signal is input to the lead-in electrode of the first electrode structure 001 (ie, the first lead-in electrode 61), and the lead-in electrode of the second electrode structure 002 is introduced (ie, The second lead-in electrode 62) inputs the data line test signal, and can test the entire array substrate to find defects of the tested array substrate.
  • the non-display area includes the first electrode structure formed in the manner of the second embodiment and the second electrode structure formed in the manner of the first embodiment, it should be understood.
  • the electrode structure disposed in the non-display area may also include only one of the first electrode structure and the second electrode structure.
  • the array substrate in this embodiment is provided with a first electrode structure, so that when the passivation layer and the gate insulating layer are once etched to form via holes, the hole walls of the via holes formed in the organic insulating layer are not engraved. Corrosion damage, and/or, by providing a second electrode structure such that the passivation layer is etched to form via holes, etching damage is not caused to the via walls of the via holes formed in the organic insulating layer, thereby The first electrode structure and/or the second electrode structure disposed in the non-display area can normally introduce test signals to test the array substrate, thereby improving test stability.
  • Example 4 The embodiment provides an array substrate. The difference from the embodiment 3 is that, as shown in FIG.
  • an electrode structure 003 is additionally disposed in the display area 01, and the electrode structure 003 adopts the embodiment 2 The electrode structure in the middle.
  • a common electrode line 13 is disposed on the base substrate 11 as a body electrode in the electrode structure 003, and the passivation layer 10 serves as the first isolation in the electrode structure 003.
  • the common electrode line 13 and the gate electrode 71 are made of the same material and formed in the same layer in the same patterning process. That is, the common electrode line 13 and the gate electrode 71 are formed in the same layer of the array substrate.
  • the base substrate 1 1 corresponds to the first base substrate 1 of the electrode structure of the embodiment 2 shown in Fig. 4.
  • the lead-in electrode and the common electrode 12 are formed of the same material and in the same patterning process. That is, the lead-in electrode and the common electrode 12 are formed in the same layer of the array substrate, and the common electrode 12 serves as both the common electrode and the lead-in electrode of the electrode structure 003.
  • the common electrode 12 is electrically connected as the lead-in electrode to the common electrode line 13, so that the area of the common electrode 12 at the junction can be increased, thereby reducing the resistance of the common electrode 12.
  • the electrode structure 003 disposed in the display area 01 may include a plurality of electrode structures 003 disposed at a certain interval from each other, and each of the electrode structures 003 corresponds to one common electrode line 13, and the lead-in electrodes of the plurality of electrode structures 003 are electrically connected to each other. With this arrangement, the electric resistance of the common electrode 12 can be greatly reduced, thereby greatly reducing the power consumption of the common electrode 12 itself, while also making the common reference voltage input to the common electrode 12 more uniform.
  • the preparation steps of the electrode structure 003 in the array substrate are the same as those in the second embodiment.
  • the preparation method of the other structures in the display area of the array substrate is the same as that in the embodiment 3, and details are not described herein again.
  • Embodiment 4 The array substrate in Embodiment 4 is provided by using the inventive scheme in the display region to set the electrode structure such that the passivation layer and the gate insulating layer are once When the via is formed by etching, etching damage is not caused to the hole walls of the via holes formed in the organic insulating layer, so that the electrode structure disposed in the display region can normally introduce a common reference voltage while reducing the resistance of the common electrode. Therefore, the power consumption of the common electrode during display is reduced while ensuring the stability of the connection, and the display effect of the array substrate is improved.
  • Example 5 Example 5:
  • the embodiment provides a display device comprising the array substrate of any of embodiments 3-4. Since the above array substrate is used, not only the display device can be normally tested, but also the stability of the test is ensured, and the display effect of the display device can be improved.
  • the display device can be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Advantageous Effects of Invention The electrode structure provided by the present invention, by completely covering the first isolation layer with the hole wall of the second via hole in the second isolation layer, thereby making the hole wall of the second via hole in the second isolation layer It will not be damaged, and thus ensure that the lead-in electrode and the body electrode can be electrically connected well, ensuring the normal introduction of the signal.
  • the array substrate with the electrode structure can normally introduce test signals and display signals through the electrode structure, so that the array substrate can be normally tested and displayed, which not only improves the test stability of the array substrate, but also improves the display effect of the array substrate. .
  • the display device using the array substrate can not only perform the test normally, but also improve the display effect.

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Abstract

一种电极结构及制备方法、阵列基板及制备方法和显示装置。电极结构包括引入电极（6）和本体电极（2）。引入电极（6）与本体电极（2）之间设置有第一隔离层（5）和第二隔离层（4）。第一隔离层（5）中开设有第一过孔（51）。第二隔离层（4）中开设有第二过孔（41）。第一过孔（51）的孔轴和第二过孔（41）的孔轴在同一直线。引入电极（6）依次通过第一过孔（51）和第二过孔（41）与本体电极（2）电连接。第一过孔（51）的直径小于第二过孔（41）的直径。第一隔离层（5）延伸至覆盖第二过孔（41）的孔壁。电极结构通过使第一隔离层（5）将第二隔离层（4）中第二过孔（41）的孔壁完全覆盖，从而使第二隔离层（4）中第二过孔（41）的孔壁不会遭到损坏，进而确保引入电极（6）与本体电极（2）能够很好地电连接，保证了信号的正常引入。

Description

电极结构及制备方法、 阵列基板及制备方法和显示装置 技术领域
本发明属于显示技术领域， 具体地， 涉及一种电极结构及制备 方法、 阵列基板及制备方法和显示装置。 背景技术
液晶显示器 （LCD : Li qui d Crystal Di splay ) 因其体积小、 功 耗低、 无辐射等特点已成为目前平板显示器中的主流产品。 目前， 随 着高分辨率小尺寸液晶显示器的广泛应用，低功耗的液晶显示器成为 大势所趋。
阵列基板是液晶显示器的重要组成部分， 也是用于显示的关键 组件。 随着技术的发展， 为了降低液晶显示器的功耗， 人们尝试着对 阵列基板进行了诸多改进。
如针对高级超维场转换技术 （HADS : Hi gh Advanced Super
Dimens i on Swi tch ) 模式的液晶显示器的阵列基板， 如图 1所示， 由 于公共电极设置在数据线的上方，且公共电极与数据线在空间位置上 存在相互重叠的部分， 使得在显示时， 该阵列基板中的公共电极与数 据线之间会形成电容。该电容的电容值越大， 阵列基板的功耗就会越 大。为了降低阵列基板乃至整个显示器的功耗， 通常在阵列基板的公 共电极和数据线之间增设有机绝缘层。有机绝缘层使得公共电极与数 据线之间的距离加大， 能够减小公共电极与数据线之间的电容， 从而 使阵列基板的功耗降低。
一般情况下， 阵列基板在制备完成后都要进行信号测试。 通常， 信号测试结构形成在阵列基板的非显示区内，且与阵列基板显示区内 的显示结构一同制备完成。 显示区内的部分层结构还延伸至非显示 区， 例如： 有机绝缘层、 栅绝缘层和钝化层等， 这样既不会在制备时 增加额外的工艺步骤， 又有利于减少非显示区与显示区的断差， 便于 非显示区与显示区的信号交换。
一般的， 信号测试包括栅线信号测试和数据线信号测试， 即通 过测试结构在栅线上加入栅线测试信号，在数据线上加入数据线测试 信号， 以检测该阵列基板是否能正常运行。 在现有技术中， 如图 1 所示， 栅线测试信号通过设置在非显示区 02的栅线信号输入电极 21 加入， 数据线测试信号通过设置在非显示区 02的数据线信号输入电 极 22加入。栅线信号输入电极 21与栅线同层设置， 栅线信号输入电 极 21上方依次设置有从显示区 01延伸过来的栅绝缘层 8、有机绝缘 层 9和钝化层 10， 钝化层 10上形成有第一引入电极 61， 该第一引入 电极 61通过贯穿栅绝缘层 8、有机绝缘层 9和钝化层 10的过孔一 010 与栅线信号输入电极 21 电连接；数据线信号输入电极 22与数据线同 层设置，数据线信号输入电极 22上方依次设置有从显示区 01延伸过 来的有机绝缘层 9和钝化层 10，钝化层 10上形成有第二引入电极 62， 该第二引入电极 62通过贯穿有机绝缘层 9和钝化层 10的过孔二 020 与数据线信号输入电极 22电连接。其中， 第一引入电极 61和第二引 入电极 62的作用是将测试信号分别引入至栅线信号输入电极 21和数 据线信号输入电极 22上。
在上述阵列基板的制备过程中， 如图 2 所示， 例如： 在形成栅 线信号输入电极 21上方所对应的过孔一 010时， 首先在有机绝缘层 9 中形成有机绝缘层过孔； 然后通过一次干刻工艺同时在钝化层 10 中形成钝化层过孔和在栅绝缘层 8中形成栅绝缘层过孔。由于钝化层 10 的对应于将要形成过孔的被曝光显影部分的开口直径（即钝化层
10中过孔的开口直径 r)比有机绝缘层过孔的开口直径 R大， 所以在 通过一次干刻工艺形成钝化层过孔和栅绝缘层过孔的图形时，容易将 有机绝缘层过孔的孔壁再次部分刻蚀掉，从而形成如图 2中所示的机 绝缘层过孔中的缺口 14。这会导致在后续的第一引入电极 61的制备 过程中， 第一引入电极 61延伸至有机绝缘层过孔中时发生与栅线信 号输入电极 21之间的虚接或者断开， 由此进一步导致测试信号无法 输入， 阵列基板无法正常测试。 发明内容
本发明针对现有技术中存在的上述技术问题， 提供了一种电极 结构及制备方法、 阵列基板及制备方法和显示装置。该电极结构通过 使第一隔离层对第二隔离层中的第二过孔的孔壁完全覆盖，从而使第 二隔离层中的第二过孔的孔壁不会遭到损坏，进而确保引入电极与本 体电极能够很好地电连接， 保证了信号的正常引入。
本发明提供一种电极结构， 包括引入电极和本体电极， 所述引 入电极与所述本体电极之间设置有第一隔离层和第二隔离层，所述第 一隔离层中开设有第一过孔， 所述第二隔离层中开设有第二过孔， 所 述第一过孔的孔轴和所述第二过孔的孔轴在同一条穿过本体电极的 直线上， 从而通过第一过孔和第二过孔暴露出一部分本体电极， 所述 引入电极通过被所述第一过孔和所述第二过孔暴露出的所述一部分 本体电极来与所述本体电极电连接， 其中， 所述第一过孔的直径小于 所述第二过孔的直径，所述第一隔离层还延伸至完全覆盖所述第二过 孔的孔壁。
优选的， 所述本体电极与所述第二隔离层之间还设置有第三隔 离层， 所述第三隔离层中开设有第三过孔， 所述第三过孔的孔轴与所 述第二过孔的孔轴在同一直线上，且所述第三过孔的直径小于等于所 述第一过孔的直径，从而还通过所述第三过孔暴露出所述一部分本体 电极，所述第一隔离层还延伸至覆盖所述第三隔离层被所述第二过孔 暴露出来的上表面。
优选的， 所述第二隔离层采用聚酰亚胺环氧树脂材料形成， 所 述第一隔离层和所述第三隔离层采用氮化硅材料形成，所述引入电极 采用氧化铟锡或掺铟氧化锌材料形成。
本发明还提供一种阵列基板， 包括衬底基板以及设置于所述衬 底基板上方的多个电极结构， 所述阵列基板包括显示区和非显示区， 所述电极结构采用上述电极结构，所述电极结构设置于所述显示区和
/或所述非显示区。
优选的， 所述阵列基板还包括多条交叉设置的栅线和数据线， 所述栅线和数据线将所述显示区划分为多个像素区域，每个所述像素 区域内设置有薄膜晶体管， 所述薄膜晶体管包括栅极、 栅绝缘层、 源 极和漏极， 所述栅极与所述栅线电连接， 所述源极与所述数据线电连 接， 所述薄膜晶体管的上方还设置有有机绝缘层和钝化层， 所述钝化 层的上方还设置有公共电极， 所述栅绝缘层、所述有机绝缘层和所述 钝化层还同时延伸至所述非显示区。
优选的， 所述电极结构设置于所述非显示区， 且所述电极结构 包括第一电极结构和第二电极结构，所述栅线与所述第一电极结构中 的本体电极电连接，延伸至所述非显示区的所述钝化层作为所述第一 电极结构中的第一隔离层，延伸至所述非显示区的所述有机绝缘层作 为所述第一电极结构中的第二隔离层，延伸至所述非显示区的所述栅 绝缘层作为所述第一电极结构中的第三隔离层，所述第一电极结构中 的引入电极用于引入栅线测试信号； 和 /或， 所述数据线与所述第二 电极结构中的本体电极电连接，延伸至所述非显示区的所述钝化层作 为所述第二电极结构中的第一隔离层，延伸至所述非显示区的所述有 机绝缘层作为所述第二电极结构中的第二隔离层，所述第二电极结构 中的引入电极用于引入数据线测试信号。
优选的， 所述电极结构设置于所述显示区内作为第三电极结构， 所述衬底基板上还设置有公共电极线，所述公共电极线作为所述第三 电极结构中的本体电极，所述钝化层作为所述第三电极结构中的第一 隔离层， 所述有机绝缘层作为所述第三电极结构中的第二隔离层， 所 述栅绝缘层作为所述第三电极结构中的第三隔离层，所述公共电极作 为所述第三电极结构中的引入电极，所述引入电极用于接入公共参考 电压。
本发明还提供一种显示装置， 包括上述阵列基板。
本发明还提供一种电极结构的制备方法， 包括步骤：
在第一衬底基板上， 采用构图工艺形成本体电极；
在形成了所述本体电极的所述第一衬底基板上， 形成第二隔离 层，并采用构图工艺在第二隔离层中对应于本体电极的位置处形成第 二过孔；
在形成了所述本体电极及所述第二隔离层的所述第一衬底基板 上形成第一隔离层， 并采用构图工艺在第一隔离层中形成第一过孔， 使得所述第一过孔的孔轴与所述第二过孔的孔轴在同一直线上，且所 述第一过孔的直径小于所述第二过孔的直径，以通过所述第一过孔和 所述第二过孔暴露出一部分本体电极，并且使得所述第一隔离层对所 述第二过孔的孔壁完全覆盖； 以及
在形成了所述本体电极、 所述第二隔离层及所述第一隔离层的 所述第一衬底基板上形成引入电极，使所述引入电极通过被所述第一 过孔和所述第二过孔暴露出的所述一部分本体电极来与所述本体电 极电连接。
优选的， 在形成所述第二隔离层的步骤之前， 在形成了所述本 体电极的所述第一衬底基板上形成第三隔离层；
并且所述采用构图工艺在第一隔离层中形成所述第一过孔的步 骤还包括：通过一次构图工艺在形成第一过孔的同时还在第三隔离层 中形成第三过孔，使得所述第三过孔的直径小于等于所述第一过孔的 直径， 从而还通过所述第三过孔暴露出所述一部分本体电极， 且所述 第一隔离层还对所述第三隔离层被所述第二过孔暴露出的上表面完 全覆盖。
本发明还提供一种阵列基板的制备方法， 所述阵列基板包括显 示区和非显示区，通过采用上述电极结构的制备方法来在所述显示区 和 /或所述非显示区形成多个电极结构。
优选的， 在所述显示区， 形成栅极和栅线；
形成栅绝缘层；
形成包括源极、 漏极和数据线的源漏金属层；
形成有机绝缘层和钝化层；
形成公共电极，
其中所述栅绝缘层、 所述有机绝缘层和所述钝化层还同时延伸 至所述非显示区。
优选的， 在所述非显示区形成所述电极结构， 且所述电极结构 包括第一电极结构和第二电极结构，其中所述第一电极结构中的本体 电极与所述栅线电连接，延伸至所述非显示区的所述钝化层作为所述 第一电极结构中的第一隔离层，延伸至所述非显示区的所述有机绝缘 层作为所述第一电极结构中的第二隔离层，延伸至所述非显示区的所 述栅绝缘层还并作为所述第一电极结构中的第三隔离层，所述第一电 极结构中的引入电极用于引入栅线测试信号； 和 /或， 所述第二电极 结构中的本体电极与所述数据线电连接，延伸至所述非显示区的所述 钝化层作为所述第二电极结构中的第一隔离层，延伸至所述非显示区 的所述有机绝缘层作为所述第二电极结构中的第二隔离层，所述第二 电极结构中的引入电极用于引入数据线测试信号。
优选的， 所述栅线与所述第一电极结构中的本体电极采用相同 的材料、 且在同一构图工艺中形成， 和 /或， 所述数据线与所述第二 电极结构中的本体电极采用相同的材料、 且在同一构图工艺中形成。
优选的， 在所述显示区形成所述电极结构作为第三电极结构， 所述显示区内还形成有公共电极线，所述公共电极线作为所述第三电 极结构中的本体电极，所述钝化层作为所述第三电极结构中的第一隔 离层， 所述有机绝缘层作为所述第三电极结构中的第二隔离层， 所述 栅绝缘层作为所述第三电极结构中的第三隔离层，所述公共电极作为 所述第三电极结构中的引入电极以用于接入公共参考电压。
优选的， 所述公共电极线与所述栅极采用相同的材料、 且在同 一构图工艺中形成；所述第三电极结构中的引入电极与所述公共电极 采用相同的材料、 且在同一构图工艺中形成。
本发明的有益效果： 本发明所提供的电极结构， 通过使第一隔 离层对第二隔离层中第二过孔的孔壁完全覆盖，从而使第二隔离层中 第二过孔的孔壁不会遭到损坏，进而确保引入电极与本体电极能够很 好地电连接， 保证了信号的正常引入。 采用该电极结构的阵列基板， 能够通过该电极结构正常引入测试信号和显示信号，从而使阵列基板 能正常进行测试和显示， 不仅提高了阵列基板的测试稳定性， 还提高 了阵列基板的显示效果。采用该阵列基板的显示装置， 不仅能正常进 行测试， 而且能提高其显示效果。 附图说明
图 1为现有技术中阵列基板的结构示意图；
图 2为图 1中栅线信号测试部分存在缺陷时的结构示意图; 图 3为本发明实施例 1中电极结构的结构示意图； 图 4为本发明实施例 2中电极结构的结构示意图；
图 5为本发明实施例 3中阵列基板的结构示意图；
图 6为本发明实施例 5中阵列基板的结构示意图。
其中的附图标记说明：
1.第一衬底基板； 2.本体电极； 21.栅线信号输入电极； 22.数 据线信号输入电极； 3.第三隔离层； 31.第三过孔； 4.第二隔离层； 41.第二过孔； 5.第一隔离层； 51.第一过孔； 6.引入电极； 61.第一 引入电极； 62.第二引入电极； 7.薄膜晶体管； 71.栅极； 72.源极； 73.漏极； 74.有源层； 8.栅绝缘层； 9.有机绝缘层； 10.钝化层； 1 1. 衬底基板； 12.公共电极； 13.公共电极线； 14.缺口； 01.显示区； 02. 非显示区； 001.第一电极结构； 002.第二电极结构； 003.电极结构； 010.过孔一； 020.过孔二。 具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案， 下面结 合附图和具体实施方式对本发明一种电极结构及制备方法、阵列基板 及制备方法和显示装置作进一步详细描述。
本发明中， 构图工艺包括光刻工艺以及打印、 喷墨等辅助工艺， 其中光刻工艺是指包括曝光、 显影、 刻蚀等工艺过程的利用光刻胶、 掩模板、 曝光机等进行刻蚀以形成预定图形的工艺。 实施例 1 :
本实施例提供一种电极结构， 如图 3所示， 包括引入电极 6和 本体电极 2。 本体电极 2设置在第一衬底基板 1上， 引入电极 6与本 体电极 2之间设置有第一隔离层 5和第二隔离层 4， 第一隔离层 5中 开设有第一过孔 51、 第二隔离层 4中开设有第二过孔 41。 第一过孔 51的孔轴和第二过孔 41的孔轴在同一条穿过本体电极 2的直线上， 从而通过第一过孔 51和第二过孔 41暴露出一部分本体电极 2。 引入 电极 6通过被第一过孔 51和第二过孔 41暴露出的一部分本体电极 2 来与本体电极 2电连接。第一过孔 51的直径小于第二过孔 41的直径， 第一隔离层 5还延伸至覆盖第二过孔 41的孔壁。
其中， 第二隔离层 4 可以采用聚酰亚胺环氧树脂材料形成， 第 一隔离层 5可以采用氮化硅材料形成，引入电极 6可以采用氧化铟锡 或掺铟氧化锌材料形成。
本实施例还提供一种上述电极结构的制备方法， 该制备方法的 具体步骤为：
步骤 S 1 : 采用构图工艺在第一衬底基板 1上形成本体电极 2。 步骤 S2 :在完成了步骤 S 1的第一衬底基板 1上形成第二隔离层 4。 具体来说， 在第一衬底基板 1 上涂敷第二隔离层 4， 并采用一次 构图工艺在第二隔离层 4中的对应于本体电极 2的位置处形成第二过 孔 41， 以暴露本体电极 2的上表面中直径为 R的圆形部分。
在该步骤中， 采用掩模板对第二过孔 41进行曝光， 掩模板上对 应的用于形成第二过孔 41 的图形为圆形， 其直径为 R。 相应地， 所 形成的第二过孔 41的直径也为 R。
步骤 S3 :在完成了步骤 S2的第一衬底基板 1上形成第一隔离层 5。 具体来说， 在第一衬底基板 1 上涂敷第一隔离层 5， 并采用一次 构图工艺在第一隔离层 5中形成第一过孔 51， 使第一过孔 51的孔轴 与第二过孔 41的孔轴在同一直线上。
在该步骤中， 采用掩模板对第一过孔 51进行曝光， 掩模板上对 应的用于形成第一过孔 51 的图形为圆形， 其直径为 r ( r< R ) 。 相 应地， 形成的第一过孔 51的直径也为 r。 BP , 第一过孔 51被形成为 使得第一隔离层 5覆盖第二过孔 41的孔壁并同时暴露本体电极 2的 上表面中直径为 r的圆形部分。
步骤 S4 :在完成了步骤 S3的第一衬底基板 1上形成引入电极 6， 使引入电极通过被第一过孔 51和第二过孔 41暴露出的一部分本体电 极 2的上表面来与本体电极 2电连接。
至此， 本实施例中的电极结构制备完成。
由于 r< R， 当通过刻蚀第一隔离层 5以形成第一过孔 51时， 在 第二过孔 41中， 通过调节掩模板的对应尺寸， 使得紧贴第二过孔 41 孔壁的 R-r厚度的第一隔离层 5不会被刻蚀掉，且这部分第一隔离层 5对第二过孔 41的孔壁完全覆盖，所以不会对已形成于第二隔离层 4 中的第二过孔 41的孔壁造成刻蚀损坏， 从而使引入电极 6与本体电 极 2能够接触良好，不会造成引入电极 6与本体电极 2之间虚接或断 开， 进而使引入电极 6能够将电信号正常引入至本体电极 2上。 实施例 2 :
本实施例提供一种电极结构。 如图 4所示， 与实施例 1 不同的 是， 在实施例 1 的基础上， 本实施例中的电极结构， 在本体电极 2 与第二隔离层 4之间还设置有第三隔离层 3。第三隔离层 3中开设有 第三过孔 31， 使第三过孔 31 的孔轴与第二过孔 41 的孔轴在同一直 线上、 且其直径小于等于第一过孔 51 的直径 R， 从而还通过第三过 孔 31暴露出一部分本体电极 2， 第一隔离层 5还延伸至覆盖第三隔 离层 3被第二过孔 41暴露出的上表面。
其中， 第三隔离层 3采用氮化硅材料形成。
在实施例 1 中电极结构的制备步骤的基础上， 本实施例中电极 结构的制备步骤还包括：
在步骤 S 1 和步骤 S2 之间还包括： 步骤 S 1 ' ： 在完成步骤 S 1 的第一衬底基板 1上沉积或涂敷第三隔离层 3。
步骤 S3还进一步包括： 在采用一次构图工艺在第一隔离层 5中 形成第一过孔 51的同时， 在第三隔离层 3中形成第三过孔 31。
在该步骤中， 第一过孔 51和第三过孔 31在一次刻蚀工艺中形 成。 即采用掩模板对第一过孔 51进行曝光后， 通过一次刻蚀同时形 成第一过孔 51和第三过孔 31。 因此， 第一过孔 51与第三过孔 31的 直径相同， 也即， 二者的直径均为 ^。
这里需要说明的是， 由于实际制备工艺中的操作原因， 第三过 孔 31的直径一般会略小于第一过孔 51的直径。
本实施例中电极结构的其他制备步骤与实施例 1 中相同。 此处 不再赘述。
由于 r< R， 且第一隔离层 5—直延伸至覆盖第三隔离层 3被第 二过孔 41暴露出的上表面， 当通过一次刻蚀第一隔离层 5和第三隔 离层 3以同时形成第一过孔 51和第三过孔 31时， 同样地， 在第二过 孔 41中， 通过调节掩模板的对应尺寸， 使得紧贴第二过孔 41孔壁的 -r厚度的第一隔离层 5不会被刻蚀掉， 且这部分第一隔离层 5对第 二过孔 41 的孔壁完全覆盖， 所以不会对已形成于第二隔离层 4中的 第二过孔 41 的孔壁造成刻蚀损坏， 从而使引入电极 6与本体电极 2 能够接触良好， 不会造成引入电极 6与本体电极 2之间虚接或断开， 进而使引入电极 6能够将电信号正常引入至本体电极 2上。 实施例 3 :
本实施例提供一种阵列基板， 如图 5所示， 包括衬底基板 1 1 以 及设置于衬底基板 1 1上方的多个电极结构。 阵列基板包括显示区 01 和非显示区 02， 其中设置于非显示区 02中的多个电极结构分别采用 实施例 1和 2中的电极结构。
该阵列基板中， 多条交叉设置的栅线和数据线 （图 5 中均未示 出） 将显示区 01划分为多个像素区域， 每个像素区域内设置有薄膜 晶体管 7， 薄膜晶体管 7包括栅极 71、 栅绝缘层 8、 有源层 74、 源极 72和漏极 73。栅绝缘层 8设置在栅极 71与源极 72之间以将栅极 71 与源极 72隔离。 栅极 71与栅线电连接且设置在同一层中， 源极 72 与数据线电连接且设置在同一层中，薄膜晶体管 7的上方还设置有有 机绝缘层 9和钝化层 10， 钝化层 10的上方还设置有公共电极 12。栅 绝缘层 8、 有机绝缘层 9和钝化层 10还同时延伸至非显示区 02。
在本实施例中， 电极结构设置于非显示区 02， 且电极结构包括 第一电极结构 001和第二电极结构 002。 其中， 第一电极结构 001采 用实施例 2中的电极结构，第二电极结构 002采用实施例 1中的电极 结构。栅线与第一电极结构 001中的本体电极（即栅线信号输入电极 21 ) 电连接， 钝化层 10还延伸至非显示区 02 并作为第一电极结构 001 中的第一隔离层， 有机绝缘层 9还延伸至非显示区 02并作为第 一电极结构 001 中的第二隔离层， 栅绝缘层 8还延伸至非显示区 02 并作为第一电极结构 001中的第三隔离层， 引入电极（即第一引入电 极 61 ) 用于引入栅线测试信号。 数据线与第二电极结构 002 中的本 体电极 （即数据线信号输入电极 22 ) 电连接， 钝化层 10还延伸至非 显示区 02并作为第二电极结构 002 中的第一隔离层， 有机绝缘层 9 还延伸至非显示区 02并作为第二电极结构 002中的第二隔离层， 引 入电极 （即第二引入电极 62 ) 用于引入数据线测试信号。
其中， 第一电极结构 001 中的本体电极 （即栅线信号输入电极 21 )与显示区 01中的栅极 71采用相同的材料、且在同一构图工艺中 形成， 即第一电极结构 001 中的本体电极与显示区 01 中的栅极 71 以及栅线形成在阵列基板的同一层中。本实施例中阵列基板的衬底基 板 1 1相当于图 4所示实施例 2中电极结构的第一衬底基板 1。 第二 电极结构 002 中的本体电极 （即数据线信号输入电极 22 ) 与显示区 01中的源极 72采用相同的材料、 且在同一构图工艺中形成， 即第二 电极结构 002中的本体电极与显示区 01中的源极 72以及数据线形成 在阵列基板的同一层中。本实施例阵列基板中设置有栅绝缘层 8的衬 底基板 1 1相当于图 3所示实施例 1 中电极结构的第一衬底基板 1。 第一电极结构 001 的引入电极 （即第一引入电极 61 ) 和第二电极结 构 002的引入电极 （即第二引入电极 62 ) 与显示区 01中的公共电极 12采用相同的材料、且在同一构图工艺中形成， 即第一电极结构 001 中的引入电极和第二电极结构 002中的引入电极均与公共电极 12形 成在阵列基板的同一层中。
如此设置， 使得设置在阵列基板的非显示区 02中的第一电极结 构 001和第二电极结构 002能够随阵列基板上显示区 01 内显示结构 (如薄膜晶体管 7、 栅线和数据线） 的制备一同制备而成， 不会增加 额外的工艺步骤， 而且有利于减少非显示区 02与显示区 01的断差， 便于非显示区 02与显示区 01的信号交换。
需要说明的是， 虽然第一电极结构 001的第一引入电极 61和第 二电极结构 002的第二引入电极 62与公共电极 12形成在阵列基板的 同一层中， 但第一电极结构 001 的第一引入电极 61、 第二电极结构 002的第二引入电极 62和公共电极 12中任意两者之间不互相连接， 即相互电隔离。 原因是公共电极 12用于在显示时输入公共参考电压 信号， 第一电极结构 001 的第一引入电极 61用于在测试时输入栅线 测试信号， 第二电极结构 002的第二引入电极 62用于在测试时输入 数据线测试信号。显示时的公共电压信号和测试时的栅线测试信号及 数据线测试信号分别独立提供， 互不干扰。
本实施例中， 第一电极结构 001和第二电极结构 002均分别包 括多个，多个第一电极结构 001或多个第二电极结构 002之间彼此设 置一定间隔。每个第一电极结构 001对应一条栅线， 多个第一电极结 构 001 的引入电极 （即第一引入电极 61 ) 相互电连接。 如此设置， 有利于栅线测试信号的引入，即只要在一个第一电极结构 001的第一 引入电极 61上输入栅线测试信号， 所有的第一电极结构 001中的本 体电极 （即栅线信号输入电极 21 ) 都能通过互相连接在一起的第一 引入电极 61获得该栅线测试信号，因此不必在每个第一电极结构 001 上都输入栅线测试信号。每个第二电极结构 002对应一条数据线， 多 个第二电极结构 002的引入电极 （即第二引入电极 62 ) 相互电连接。 如此设置， 同样有利于数据线测试信号的引入， 即只要在一个第二电 极结构 002的第二引入电极 62上输入数据线测试信号， 所有的第二 电极结构 002 中的本体电极 （即数据线信号输入电极 22 ) 都能通过 互相连接在一起的第二引入电极 62获得该数据线测试信号， 因此不 必在每个第二电极结构 002上都输入数据线测试信号。
需要说明的是， 图 5仅为本实施例中阵列基板的示意性结构图， 实际阵列基板的薄膜晶体管 7、第一电极结构 001和第二电极结构 002 并不能在一个剖切面上同时剖出，图 5只是将这几个结构示意性地放 到一个图中进行说明， 以便能更清楚地说明它们之间的结构关系。
本实施例还提供一种针对上述阵列基板的制备方法， 包括利用 实施例 1或 2中的电极结构制备方法来在非显示区 02形成第一电极 结构 001和第二电极结构 002。
该方法还包括： 在显示区 01 形成栅极 71和栅线； 形成栅绝缘 层 8， 并使栅绝缘层 8延伸至非显示区 02 以作为第一电极结构 001 的第三隔离层； 形成包括源极 72、 漏极 73和数据线的源漏金属层， 以及形成有源层 74 ; 形成有机绝缘层 9和钝化层 10， 并使有机绝缘 层 9和钝化层 10延伸至非显示区 02 以分别作为第一电极结构 001 和第二电极结构 002的第二隔离层和第一隔离层； 形成公共电极 12。
其中， 第一电极结构 001 中的本体电极 （即栅线信号输入电极 21 ) 与栅极 71采用相同的材料、 且在同一构图工艺中形成； 第二电 极结构 002中的本体电极 （即数据线信号输入电极 22 ) 与源极 72采 用相同的材料、 且在同一构图工艺中形成。
栅线与第一电极结构 001 中的本体电极电连接， 数据线与第二 电极结构 002中的本体电极电连接。
本实施例中， 第一电极结构 001 的制备步骤采用实施例 2 中电 极结构的制备步骤，第二电极结构 002的制备步骤采用实施例 1中电 极结构的制备步骤。
本实施例中， 当需要对阵列基板进行测试时， 向第一电极结构 001的引入电极（即第一引入电极 61 )输入栅线测试信号， 并且向第 二电极结构 002 的引入电极 （即第二引入电极 62 ) 输入数据线测试 信号， 就能够对整个阵列基板进行测试， 从而发现被测试阵列基板的 缺陷。
尽管上述对本实施例的描述中例举了非显示区中包括采用第 2 实施例中的方式形成的第一电极结构以及采用第 1 实施例中的方式 形成的第二电极结构， 然而应当理解的是， 对于本实施例的阵列基板 而言，设置于非显示区的电极结构也可以只包括第一电极结构和第二 电极结构之一。
本实施例中的阵列基板通过设置第一电极结构， 使得对钝化层 和栅绝缘层进行一次刻蚀形成过孔时，不会对已形成于有机绝缘层中 的过孔的孔壁造成刻蚀损坏， 和 /或， 通过设置第二电极结构， 使得 对钝化层进行刻蚀形成过孔时，不会对已形成于有机绝缘层中的过孔 的孔壁造成刻蚀损坏， 从而使设置在非显示区的第一电极结构和 /或 第二电极结构能够正常引入测试信号来对该阵列基板进行测试，从而 提高了测试稳定性。 实施例 4 : 本实施例提供一种阵列基板， 与实施例 3不同的是， 如图 6所 示， 本实施例中， 在显示区 01 中另外设置了电极结构 003， 且该电 极结构 003采用了实施例 2 中的电极结构。 具体来说， 在显示区 01 内， 衬底基板 1 1上还设置有公共电极线 13， 公共电极线 13作为电 极结构 003中的本体电极， 钝化层 10作为电极结构 003中的第一隔 离层， 有机绝缘层 9作为电极结构 003中的第二隔离层， 栅绝缘层 8 作为第三电极结构 003中的第三隔离层， 公共电极 12作为电极结构 003中的引入电极， 该引入电极用于接入公共参考电压。
阵列基板显示区 01内的其他结构与实施例 3的显示区中的结构 相同， 这里不再赘述。
本实施例的电极结构 003 中， 公共电极线 13与栅极 71采用相 同的材料、 且在同一构图工艺中形成在同一层。 即公共电极线 13与 栅极 71形成在阵列基板的同一层中。衬底基板 1 1相当于图 4所示实 施例 2 中电极结构的第一衬底基板 1。 引入电极与公共电极 12采用 相同的材料、 且在同一构图工艺中形成。 即引入电极与公共电极 12 形成在阵列基板的同一层中， 公共电极 12既作为公共电极， 又作为 电极结构 003的引入电极。
需要说明的是， 电极结构 003中， 公共电极 12作为引入电极与 公共电极线 13电连接， 能够使公共电极 12在连接处的面积增大， 从 而减小了公共电极 12 的电阻。 设置在显示区 01 内的电极结构 003 可以包括多个， 多个电极结构 003彼此相距一定间隔设置， 每个电极 结构 003对应一条公共电极线 13， 多个电极结构 003 的引入电极相 互电连接。 如此设置， 能够大大减小公共电极 12的电阻， 从而大大 降低公共电极 12本身的功耗，同时还使输入至公共电极 12上的公共 参考电压更加均匀。
本实施例中， 阵列基板中电极结构 003 的制备步骤与实施例 2 中电极结构的制备步骤相同，阵列基板显示区内其它结构的制备方法 与实施例 3中相同， 此处不再赘述。
实施例 4 的有益效果： 实施例 4 中的阵列基板通过在显示区内 采用本发明方案来设置电极结构，使得对钝化层和栅绝缘层进行一次 刻蚀形成过孔时，不会对已形成于有机绝缘层中的过孔的孔壁造成刻 蚀损坏， 使得设置在显示区的电极结构能够正常引入公共参考电压， 同时减小公共电极的电阻，从而在保证连接稳定性的同时降低公共电 极在显示时的功耗， 提高阵列基板显示效果。 实施例 5 :
本实施例提供一种显示装置， 包括实施例 3-4 中任一的阵列基 板。 由于采用上述阵列基板， 不仅使得显示装置能够正常进行测试， 保证了测试的稳定性， 而且还能够提高显示装置的显示效果。
该显示装置可以为液晶面板、 电子纸、 0LED面板、 手机、 平板 电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有 显示功能的产品或部件。 本发明的有益效果： 本发明所提供的电极结构， 通过使第一隔 离层对第二隔离层中第二过孔的孔壁完全覆盖，从而使第二隔离层中 第二过孔的孔壁不会遭到损坏，进而确保引入电极与本体电极能够很 好地电连接， 保证了信号的正常引入。 采用该电极结构的阵列基板， 能够通过该电极结构正常引入测试信号和显示信号，从而使阵列基板 能正常进行测试和显示， 不仅提高了阵列基板的测试稳定性， 还提高 了阵列基板的显示效果。采用该阵列基板的显示装置， 不仅能正常进 行测试， 而且能提高其显示效果。 可以理解的是， 以上实施方式仅仅是为了说明本发明的原理而 采用的示例性实施方式， 然而本发明并不局限于此。对于本领域内的 普通技术人员而言， 在不脱离本发明的精神和实质的情况下， 可以做 出各种变型和改进， 这些变型和改进也视为本发明的保护范围。

Claims

权利要求
1. 一种电极结构， 包括引入电极和本体电极， 所述引入电极与 所述本体电极之间设置有第一隔离层和第二隔离层，所述第一隔离层 中开设有第一过孔， 所述第二隔离层中开设有第二过孔， 所述第一过 孔的孔轴和所述第二过孔的孔轴在同一条穿过本体电极的直线上，从 而通过所述第一过孔和所述第二过孔暴露出一部分本体电极，所述引 入电极通过被所述第一过孔和所述第二过孔暴露出的所述一部分本 体电极来与所述本体电极电连接， 所述电极结构的特征在于： 所述第 一过孔的直径小于所述第二过孔的直径，所述第一隔离层还延伸至完 全覆盖所述第二过孔的孔壁。
2. 根据权利要求 1所述的电极结构， 其特征在于， 所述本体电 极与所述第二隔离层之间还设置有第三隔离层，所述第三隔离层中开 设有第三过孔，所述第三过孔的孔轴与所述第二过孔的孔轴在同一直 线上， 且所述第三过孔的直径小于等于所述第一过孔的直径， 从而还 通过所述第三过孔暴露出所述一部分本体电极，所述第一隔离层还延 伸至覆盖所述第三隔离层被所述第二过孔暴露出来的上表面。
3. 根据权利要求 2所述的电极结构， 其特征在于， 所述第二隔 离层采用聚酰亚胺环氧树脂材料形成，所述第一隔离层和所述第三隔 离层采用氮化硅材料形成，所述引入电极采用氧化铟锡或掺铟氧化锌 材料形成。
4. 一种阵列基板， 包括衬底基板以及设置于所述衬底基板上方 的如权利要求 1-3中任意一项所述的电极结构。
5. 根据权利要求 4所述的阵列基板， 其中所述阵列基板包括显 示区和非显示区， 所述电极结构设置于所述显示区和 /或所述非显示 区。
6. 根据权利要求 5所述的阵列基板， 其特征在于， 还包括多条 交叉设置的栅线和数据线，所述栅线和数据线将所述显示区划分为多 个像素区域， 每个所述像素区域内设置有薄膜晶体管， 所述薄膜晶体 管包括栅极、 栅绝缘层、 源极和漏极， 所述栅极与所述栅线电连接， 所述源极与所述数据线电连接，所述薄膜晶体管的上方还设置有有机 绝缘层和钝化层， 所述钝化层的上方还设置有公共电极， 所述栅绝缘 层、 所述有机绝缘层和所述钝化层还同时延伸至所述非显示区。
7. 根据权利要求 6所述的阵列基板， 其特征在于， 所述电极结 构设置于所述非显示区，且所述电极结构包括第一电极结构和第二电 极结构， 其中， 所述栅线与所述第一电极结构中的本体电极电连接， 延伸至所述非显示区的所述钝化层作为所述第一电极结构中的第一 隔离层，延伸至所述非显示区的所述有机绝缘层作为所述第一电极结 构中的第二隔离层，延伸至所述非显示区的所述栅绝缘层作为所述第 一电极结构中的第三隔离层，所述第一电极结构中的引入电极用于引 入栅线测试信号； 和 /或， 所述数据线与所述第二电极结构中的本体 电极电连接，延伸至所述非显示区的所述钝化层作为所述第二电极结 构中的第一隔离层，延伸至所述非显示区的所述有机绝缘层作为所述 第二电极结构中的第二隔离层，所述第二电极结构中的引入电极用于 引入数据线测试信号。
8. 根据权利要求 6所述的阵列基板， 其特征在于， 所述电极结 构设置于所述显示区内作为第三电极结构，所述衬底基板上还设置有 公共电极线， 所述公共电极线作为所述第三电极结构中的本体电极， 所述钝化层作为所述第三电极结构中的第一隔离层，所述有机绝缘层 作为所述第三电极结构中的第二隔离层，所述栅绝缘层作为所述第三 电极结构中的第三隔离层，所述公共电极作为所述第三电极结构中的 引入电极， 所述引入电极用于接入公共参考电压。
9. 一种显示装置， 其特征在于， 包括权利要求 4-8中任意一项 所述的阵列基板。
10. 一种电极结构的制备方法， 其特征在于， 包括步骤： 在第一衬底基板上， 采用构图工艺形成本体电极；
在形成了所述本体电极的所述第一衬底基板上， 形成第二隔离 层，并采用构图工艺在第二隔离层中对应于本体电极的位置处形成第 二过孔；
在形成了所述本体电极及所述第二隔离层的所述第一衬底基板 上形成第一隔离层， 并采用构图工艺在第一隔离层中形成第一过孔， 使得所述第一过孔的孔轴与所述第二过孔的孔轴在同一直线上，且所 述第一过孔的直径小于所述第二过孔的直径，以通过所述第一过孔和 所述第二过孔暴露出一部分本体电极，并且使得所述第一隔离层对所 述第二过孔的孔壁完全覆盖； 以及
在形成了所述本体电极、 所述第二隔离层及所述第一隔离层的 所述第一衬底基板上形成引入电极，使所述引入电极通过被所述第一 过孔和所述第二过孔暴露出的所述一部分本体电极来与所述本体电 极电连接。
1 1 . 根据权利要求 10所述的制备方法， 其特征在于，
在形成所述第二隔离层的步骤之前， 在形成了所述本体电极的 所述第一衬底基板上形成第三隔离层；
并且所述采用构图工艺在第一隔离层中形成所述第一过孔的步 骤还包括：通过一次构图工艺在形成第一过孔的同时还在第三隔离层 中形成第三过孔，使得所述第三过孔的直径小于等于所述第一过孔的 直径， 从而还通过所述第三过孔暴露出所述一部分本体电极， 且所述 第一隔离层还对所述第三隔离层被所述第二过孔暴露出来的上表面 完全覆盖。
12 . 一种阵列基板的制备方法， 其特征在于， 采用如权利要求 10或 1 1所述的制备方法来制备所述阵列基板中的电极结构。
13. 根据权利要求 12所述的制备方法， 所述阵列基板包括显示 区和非显示区， 其中所述电极结构形成在所述显示区和 /或所述非显 示区。
14. 根据权利要求 13所述的制备方法， 其特征在于，
在所述显示区， 形成栅极和栅线；
形成栅绝缘层；
形成包括源极、 漏极和数据线的源漏金属层；
形成有机绝缘层和钝化层；
形成公共电极，
其中所述栅绝缘层、 所述有机绝缘层和所述钝化层还同时延伸 至所述非显示区。
15. 根据权利要求 14所述的制备方法， 其特征在于， 在所述非 显示区形成所述电极结构，且所述电极结构包括第一电极结构和第二 电极结构， 其中所述第一电极结构中的本体电极与所述栅线电连接， 延伸至所述非显示区的所述钝化层作为所述第一电极结构中的第一 隔离层，延伸至所述非显示区的所述有机绝缘层作为所述第一电极结 构中的第二隔离层，延伸至所述非显示区的所述栅绝缘层还并作为所 述第一电极结构中的第三隔离层，所述第一电极结构中的引入电极用 于引入栅线测试信号； 和 /或， 所述第二电极结构中的本体电极与所 述数据线电连接，延伸至所述非显示区的所述钝化层作为所述第二电 极结构中的第一隔离层，延伸至所述非显示区的所述有机绝缘层作为 所述第二电极结构中的第二隔离层，所述第二电极结构中的引入电极 用于引入数据线测试信号。
16. 根据权利要求 15所述的制备方法， 其特征在于， 所述栅线 与所述第一电极结构中的本体电极采用相同的材料、且在同一构图工 艺中形成， 和 /或， 所述数据线与所述第二电极结构中的本体电极采 用相同的材料、 且在同一构图工艺中形成。
17. 根据权利要求 14所述的制备方法， 其特征在于， 在所述显 示区形成所述电极结构作为第三电极结构，所述显示区内还形成有公 共电极线， 所述公共电极线作为所述第三电极结构中的本体电极， 所 述钝化层作为所述第三电极结构中的第一隔离层，所述有机绝缘层作 为所述第三电极结构中的第二隔离层，所述栅绝缘层作为所述第三电 极结构中的第三隔离层，所述公共电极作为所述第三电极结构中的引 入电极以用于接入公共参考电压。
18. 根据权利要求 17所述的制备方法， 其特征在于， 所述公共 电极线与所述栅极采用相同的材料、且在同一构图工艺中形成； 所述 第三电极结构中的引入电极与所述公共电极采用相同的材料、且在同 一构图工艺中形成。
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