WO2015017487A1 - Amplificateurs avec inductances de contre-réaction de source couplées mutuellement configurables - Google Patents

Amplificateurs avec inductances de contre-réaction de source couplées mutuellement configurables Download PDF

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Publication number
WO2015017487A1
WO2015017487A1 PCT/US2014/048764 US2014048764W WO2015017487A1 WO 2015017487 A1 WO2015017487 A1 WO 2015017487A1 US 2014048764 W US2014048764 W US 2014048764W WO 2015017487 A1 WO2015017487 A1 WO 2015017487A1
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WIPO (PCT)
Prior art keywords
inductors
coupled
transistor
source degeneration
inductor
Prior art date
Application number
PCT/US2014/048764
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English (en)
Inventor
Zhang Jin
Ahmed A Youssef
Li-Chung Chang
Original Assignee
Qualcomm Incorporated
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Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to KR1020167004709A priority Critical patent/KR101650846B1/ko
Priority to CN201480042528.3A priority patent/CN105409116B/zh
Priority to JP2016525604A priority patent/JP6110034B2/ja
Priority to EP14752968.9A priority patent/EP3028381A1/fr
Publication of WO2015017487A1 publication Critical patent/WO2015017487A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics

Definitions

  • the present disclosure relates generally to electronics, and more specifically to amplifiers.
  • a wireless device in a wireless communication system may transmit and receive data for two-way communication.
  • the wireless device may include a transmitter for data transmission and a receiver for data reception.
  • the transmitter may modulate a local oscillator (LO) signal with data to obtain a modulated signal, amplify the modulated signal to obtain an output radio frequency (RF) signal having the proper transmit power level, and transmit the output RF signal via an antenna to a base station.
  • LO local oscillator
  • RF radio frequency
  • the receiver may obtain a received RF signal via the antenna and may amplify and process the received RF signal to recover data sent by the base station.
  • a wireless device may include amplifiers of different types for different purposes.
  • a wireless device may include a low noise amplifier (LNA) in a receiver, a power amplifier (PA) in a transmitter, and a variable gain amplifier (VGA) in the receiver and/or transmitter.
  • LNA low noise amplifier
  • PA power amplifier
  • VGA variable gain amplifier
  • An amplifier may need to meet various requirements related to gain, linearity, etc.
  • FIG. 1 shows a wireless device communicating with wireless systems.
  • FIG. 2 shows a block diagram of the wireless device in FIG. 1.
  • FIG. 3 shows an LNA with a fixed source degeneration inductor.
  • FIG. 4 shows an LNA with configurable mutually-coupled source degeneration inductors.
  • FIGS. 5A and 5B show amplifiers with mutually-coupled source degeneration inductors having positive and negative coupling coefficients, respectively.
  • FIG. 6 shows two source degeneration inductors with little mutual coupling.
  • FIGS. 7A and 7B show two mutually -coupled source degeneration inductors with positive and negative coupling coefficients, respectively.
  • FIG. 8 shows a portion of a receiver supporting carrier aggregation.
  • FIGS. 9A to 9D show LNAs with multiple outputs and configurable mutually- coupled source degeneration inductors.
  • FIG. 10 shows a process for performing amplification.
  • Amplifiers with configurable mutually-coupled source degeneration inductors are disclosed herein. Such an amplifier includes multiple mutually-coupled inductors that may be configured to obtain different source degeneration inductances for the amplifier. A configurable source degeneration inductance may improve the performance of the amplifier and provide other advantages. Amplifiers with configurable mutually-coupled source degeneration inductors may be used for various electronic devices such as wireless communication devices.
  • FIG. 1 shows a wireless device 1 10 communicating with wireless communication systems 120 and 122.
  • Each wireless system may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a wireless local area network (WLAN) system, or some other wireless system.
  • a CDMA system may implement Wideband CDMA (WCDMA), CDMA IX, Time Division Synchronous CDMA (TD- SCDMA), or some other version of CDMA.
  • WCDMA Wideband CDMA
  • CDMA IX CDMA IX
  • TD- SCDMA Time Division Synchronous CDMA
  • FIG. 1 shows wireless system 120 including two base stations 130 and 132 and one system controller 140, and wireless system 122 including one base station 134.
  • a wireless system may include any number of base stations and any set of network entities.
  • a base station may also be referred to as a Node B, an evolved Node B (eNB), an access point, etc.
  • eNB evolved
  • Wireless device 1 10 may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc.
  • Wireless device 1 10 may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, etc.
  • Wireless device 110 may communicate with wireless system 120 and/or 122.
  • Wireless device 1 10 may also receive signals from broadcast stations, signals from satellites (e.g., a satellite 150) in one or more global navigation satellite systems (GNSS), etc.
  • Wireless device 1 10 may support one or more radio technologies for wireless communication such as LTE, WCDMA, CDMA IX, TD-SCDMA, GSM, 802.11, etc.
  • FIG. 2 shows a block diagram of an exemplary design of wireless device 110 in
  • wireless device 110 includes a transceiver 220 coupled to a primary antenna 210, a transceiver 222 coupled to a secondary antenna 212, and a data processor/controller 280.
  • Transceiver 220 includes an antenna interface circuit 224, K LNAs 230a to 230k, receive circuits 240, transmit circuits 250, and K power amplifiers (PAs) 260a to 260k, where K may be any integer value.
  • Transceiver 222 includes an antenna interface circuit 226, M LNAs 232a to 232m, receive circuits 242, transmit circuits 252, and M PAs 262a to 262m, where M may be any integer value.
  • Transceivers 220 and 222 may support multiple frequency bands, carrier aggregation, multiple radio technologies, multiple wireless systems, receive diversity, transmit diversity, multiple-input multiple-output (MIMO) transmission from multiple transmit antennas to multiple receive antennas, etc., or any combination thereof.
  • MIMO multiple-input multiple-output
  • antenna 210 receives signals from base stations and/or other transmitter stations and provides a received RF signal to antenna interface circuit 224.
  • Antenna interface circuit 224 provides one or more input RF signals to one or more selected LNAs 230.
  • Antenna interface circuit 224 may include switches, duplexers, diplexers, transmit filters, receive filters, matching circuits, directional couplers, etc.
  • Each selected LNA 230 amplifies its input RF signal and provides one or more amplified RF signals to receive circuits 240.
  • Receive circuits 240 downconvert each amplified RF signal from RF to baseband, filter and amplify the downconverted signal, and provide an input baseband signal to data processor 280.
  • Receive circuits 240 may include mixers, filters, amplifiers, matching circuits, oscillators, LO generators, phase locked loops (PLLs), etc.
  • data processor 280 processes (e.g., encodes and modulates) data to be transmitted and provides one or more output baseband signals to transmit circuits 250.
  • Transmit circuits 250 amplify, filter, and upconvert each output baseband signal from baseband to RF and provide a resultant modulated signal to a selected PA 260.
  • Transmit circuits 250 may include amplifiers, filters, mixers, matching circuits, oscillators, LO generators, PLLs, etc.
  • Each selected PA 260 amplifies its modulated signal and provides an output RF signal having the proper transmit power level.
  • the output RF signal from each selected PA 260 is routed through antenna interface circuit 224 and transmitted via antenna 210.
  • LNAs 232, receive circuits 242, transmit circuits 252, and PAs 262 within transceiver 222 may operate in similar manner as LNAs 230, receive circuits 240, transmit circuits 250, and PAs 260 within transceiver 220.
  • Transceivers 220 and 222 may include other circuits not shown in FIG. 2. All or a portion of transceivers 220 and 222 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.
  • ICs analog integrated circuits
  • RFICs RF ICs
  • mixed-signal ICs etc.
  • LNAs 230 and receive circuits 240 may be implemented on one module, which may be an RFIC, etc.
  • the circuits in transceivers 220 and 222 may also be implemented in other manners.
  • Data processor/controller 280 may perform various functions for wireless device
  • data processor 280 may perform processing for data being received via receiver circuits 240 and 242 and data being transmitted via transmit circuits 250 and 252. Controller 280 may control the operation of various circuits within transceivers 220 and 222.
  • a memory 282 may store program codes and data for data processor/controller 280.
  • Data processor/controller 280 may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs.
  • ASICs application specific integrated circuits
  • FIG. 2 shows an exemplary design of wireless device 1 10 with two transceivers
  • a wireless device may include any number of transceivers for any number of antennas.
  • Each transceiver may include any number of LNAs and any number of PAs to support any number of frequency bands, any number of carriers for carrier aggregation, any number of wireless systems, any number of radio technologies, etc.
  • LNAs 230 and 232 in FIG. 2 may be implemented with various circuit designs and with transistors of various types. Some exemplary circuit designs of LNAs implemented with N-channel metal oxide semiconductor (NMOS) transistors are described below.
  • NMOS N-channel metal oxide semiconductor
  • FIG. 3 shows a schematic diagram of an LNA 330 with a fixed source degeneration inductor.
  • LNA 330 includes a source degeneration inductor 332, a gain transistor 334, and a cascode transistor 336.
  • An input matching circuit 312 has one end receiving an input RF signal (RFin) and the other end coupled to the gate of gain transistor 334.
  • Gain transistor 334 has its source coupled to one end of inductor 332 and its drain coupled to the source of cascode transistor 336. The other end of inductor 332 is coupled to circuit ground.
  • Cascode transistor 336 has its gate receiving a control signal (Vb) and its drain coupled to a load circuit 380.
  • Gain transistor 334 and cascode transistor 336 may be implemented with NMOS transistors, as shown in FIG. 3, or with transistors of other types.
  • LNA 330 Within LNA 330, gain transistor 334 amplifies the RFin signal and provides an amplified signal. Cascode transistor 336 buffers the amplified signal and provides an output RF signal (RFout) to load circuit 380.
  • Source degeneration inductor 332 performs several functions. First, inductor 332 enables LNA 330 to obtain good dynamic range (e.g., low noise figure) and achieve high sensitivity for a receiver with low power consumption. Second, inductor 332 helps with input matching of LNA 330.
  • An LNA may include a fixed source degeneration inductor having an inductance that is selected to obtain good performance, e.g., high dynamic range, good linearity, and good input matching.
  • the LNA may have a configurable gain and/or other configurable characteristics.
  • a fixed source degeneration inductor may be unable to provide good performance for different possible settings of the LNA.
  • an amplifier includes a programmable source degeneration inductor that is implemented with multiple mutually-coupled inductors.
  • the mutually-coupled inductors may be configured to obtain different source degeneration inductances for the amplifier.
  • the amplifier may support multiple operating modes.
  • the amplifier may be configured with a suitable source degeneration inductance for each operating mode in order to obtain good performance for the amplifier.
  • FIG. 4 shows a schematic diagram of an exemplary design of an LNA 430 with configurable mutually-coupled source degeneration inductors.
  • LNA 430 may be used for any of LNAs 230 and 232 in FIG. 2.
  • LNA 430 includes a programmable inductor 432, a gain transistor 434, and a cascode transistor 436.
  • An input matching circuit 412 has one end receiving an input RF signal (RFin) and the other end coupled to the gate of gain transistor 434.
  • Input matching circuit 412 may comprise (i) an inductor coupled between the input and output of input matching circuit 412 and/or (ii) other circuit components.
  • Gain transistor 434 has its source coupled to one end of inductor 432 and its drain coupled to the source of cascode transistor 436. Inductor 432 is further coupled to circuit ground.
  • Cascode transistor 436 has its gate receiving a control signal (Vb) and its drain coupled to a load circuit 480.
  • Gain transistor 434 and cascode transistor 436 may be implemented with NMOS transistors, as shown in FIG. 4, or with transistors of other types.
  • load circuit 480 includes a transformer
  • a load circuit may include an inductor and possibly a capacitor coupled between the VDD supply and the drain of a cascode transistor.
  • a load circuit may include a P-channel metal oxide semiconductor (PMOS) transistor having its source coupled to the VDD supply and its drain coupled to the drain of a cascode transistor (e.g., cascode transistor 436). The PMOS transistor may provide an active load for the cascode transistor.
  • PMOS P-channel metal oxide semiconductor
  • programmable inductor 432 includes two configurable mutually-coupled source degeneration inductors 442 and 444 coupled in parallel.
  • Inductor 442 has one end coupled to the source of gain transistor 434 and the other end coupled to circuit ground.
  • Inductor 444 has one end coupled to the source of gain transistor 434 and the other end coupled to the drain of a transistor 446.
  • Transistor 446 has its source coupled to circuit ground and its gate receiving a mode control signal (Mode).
  • Mode mode control signal
  • Inductor 444 and transistor 446 are coupled in series, and the series combination is coupled in parallel with inductor 442.
  • Transistor 446 operates as a switch that may be either (i) closed to couple inductor 444 in parallel with inductor 442 or (ii) opened to disconnect inductor 444 from the parallel combination with inductor 442.
  • Inductor 442 has an inductance of LI
  • inductor 444 has an inductance of L2.
  • LNA 430 may support multiple operating modes, which may be associated with different configurations of programmable inductor 432.
  • transistor 446 is turned OFF, and only inductor 442 is coupled between the source of gain transistor 434 and circuit ground.
  • the source degeneration inductance may be expressed as:
  • Loff Ll , Eq (l) where Loff is the source degeneration inductance with transistor 446 turned OFF.
  • transistor 446 is turned ON, and both inductors 442 and 444 are coupled between the source of transistor 434 and circuit ground. Inductors 442 and 444 are mutually coupled. The amount of mutual coupling may be quantified by a coupling coefficient K.
  • the source degeneration inductance may be expressed as:
  • M K * VL1 * L2 , Eq (3) where Lon is the source degeneration inductance with transistor 446 turned ON, and M is a mutual inductance of inductors 442 and 444 due to mutual coupling.
  • the Lon inductance is equal to the parallel combination of (i) the LI inductance plus the mutual inductance M and (ii) the L2 inductance plus the mutual inductance M.
  • the coupling coefficient K may have a positive sign ( K > 0 ) or a negative sign
  • the sign of the coupling coefficient may be dependent on the orientation and/or layout of conductors used to implement inductors 442 and 444.
  • the mutual coupling is greater than zero ( M > 0 )
  • the Lon inductance is greater than the Lparallel inductance ( Lon > Lparallel) .
  • the mutual coupling is less than zero ( M ⁇ 0 )
  • the Lon inductance is less than the Lparallel inductance ( Lon ⁇ Lparallel) .
  • FIG. 5A shows an exemplary design of an amplifier 530a with mutually- coupled source degeneration inductors having a positive coupling coefficient.
  • Amplifier 530a includes a gain transistor 534, a cascode transistor 536, and a programmable inductor 532a for source degeneration. In the exemplary design shown in FIG.
  • programmable inductor 532a includes two configurable mutually-coupled inductors 542 and 544.
  • Inductor 542 is coupled between the source of gain transistor 534 and node A.
  • Inductor 544 is coupled in series with a switch 546, and the series combination is coupled between the source of gain transistor 534 and node A.
  • Inductors 542 and 544 have a positive coupling coefficient (+K or K > 0 ).
  • FIG. 5A assumes a direct connection (e.g., negligible parasitic inductance) between node A and circuit ground.
  • Table 1 shows inductances for different possible positive coupling coefficients.
  • Column 3 lists the LI, L2, M, Lon and Loff inductances and the Loff/Lon ratio for a second case with a positive coupling coefficient of 0.3 between inductors 542 and 544.
  • Column 4 lists the LI, L2, M, Lon and Loff inductances and the Loff/Lon ratio for a third case with a positive coupling coefficient of 0.6 between inductors 542 and 544.
  • the same Loff inductance of 1.5 nanoHenries (nH) and the same Lon inductance of 0.75 nH may be obtained for all three cases.
  • the Lon inductance of 0.75 nH may be obtained with (i) a nominal L2 inductance of 1.5 nH for inductor 544 with no mutual coupling, or (ii) a smaller L2 inductance of 0.9 nH for inductor 544 with a coupling coefficient of 0.3, or (iii) an even smaller L2 inductance of 0.6 nH for inductor 544 with a coupling coefficient of 0.6.
  • a positive coupling coefficient may thus be used to reduce the size of inductor 544 for a given Lon inductance.
  • FIG. 5B shows an exemplary design of an amplifier 530b with mutually- coupled source degeneration inductors having a negative coupling coefficient.
  • Amplifier 530b includes gain transistor 534, cascode transistor 536, and a programmable inductor 532b for source degeneration.
  • programmable inductor 532b includes two configurable mutually-coupled inductors 552 and 554.
  • Inductor 552 is coupled between the source of gain transistor 534 and node B.
  • Inductor 554 is coupled in series with a switch 556, and the series combination is coupled between the source of gain transistor 534 and node B.
  • Inductors 552 and 554 have a negative coupling coefficient (-K or K ⁇ 0 ).
  • a parasitic inductor 558 is coupled between node B and circuit ground. Inductor 558 may be due to a routing trace from the ends of inductors 552 and 554 to circuit ground. This routing trace may be relatively long and may result in a non-negligible inductance of Lgnd for inductor 558.
  • the source degeneration inductance may be expressed as:
  • parasitic inductor 558 effectively increases the source degeneration inductance.
  • the source degeneration inductance may be expressed as:
  • the mutual inductance M in equation (5) may be determined as shown in equation (3).
  • Table 2 shows inductances for different possible negative coupling coefficients.
  • Column 3 lists the LI, L2, Lgnd, M, Lon, Loff, Ldegen_on and Ldegen off inductances for a second case with a negative coupling coefficient of -0.3 between inductors 552 and 554.
  • Column 4 lists the LI, L2, Lgnd, M, Lon, Loff, Ldegen_on and Ldegen off inductances for a third case with a negative coupling coefficient of -0.6 between inductors 552 and 554.
  • a progressively more negative mutual inductance M may be obtained with a progressive more negative coupling coefficient. This results in progressively smaller Lon and Ldegen_on inductances for a progressive more negative coupling coefficient.
  • a negative coupling coefficient may be used to reduce the Lon inductance to account or compensate for the Lgnd inductance, so that a desired Ldegen on inductance may be obtained in the presence of the Lgnd inductance.
  • Source degeneration inductors for an LNA may be implemented in various manners. Multiple inductors may have a particular coupling coefficient, which may be selected to obtain the desired Lon and Loff source degeneration inductances. The magnitude and sign of the coupling coefficient may be dependent on the layout and orientation of the inductors.
  • FIG. 6 shows an exemplary design of two source degeneration inductors 642 and 644 with little mutual coupling.
  • Inductor 642 is implemented with a conductor 652
  • inductor 644 is implemented with a conductor 654.
  • Conductors 652 and 654 are formed side-by-side on the same metal layer and have one end coupled together and to the source of a gain transistor (not shown in FIG. 6).
  • the other end of conductor 652 is coupled to circuit ground.
  • the other end of conductor 654 is coupled to a transistor 646, which operates as a switch.
  • the exemplary design in FIG. 6 utilizes twice the circuit area to implement inductors 642 and 644.
  • FIG. 7A shows an exemplary design of two mutually-coupled source degeneration inductors 742 and 744 with a positive coupling coefficient K.
  • Inductor 742 is implemented with a conductor 752
  • inductor 744 is implemented with a conductor 754.
  • Conductor 754 is formed inside of conductor 752.
  • Conductors 752 and 754 are formed in the same direction (which is clockwise in FIG. 7A) to obtain a positive K.
  • Conductors 752 and 754 may be formed on the same metal layer (e.g., as shown in FIG. 7 A) or on different metal layers.
  • FIG. 7B shows an exemplary design of two mutually-coupled source degeneration inductors 742 and 744 with a negative coupling coefficient K.
  • Inductor 742 is implemented with a conductor 762
  • inductor 744 is implemented with a conductor 764.
  • Conductors 762 and 764 are formed in opposite direction to obtain a negative K.
  • Conductors 762 and 764 may be formed on the same metal layer (e.g., as shown in FIG. 7B) or on different metal layers.
  • FIGS. 7A and 7B show exemplary layouts of mutually-coupled inductors.
  • the mutually-coupled inductors may be implemented in other manners.
  • mutually-coupled inductors may be implemented on different metal layers.
  • Wireless device 1 10 may support operation on multiple frequency bands (or simply, "bands"). Each band may cover a range of frequencies. For example, LTE Release 1 1 defines 35 bands, which are referred to as LTE/UMTS bands and are listed in a publicly available document 3 GPP TS 36.101. Wireless device 1 10 may support one or more LTE/UMTS bands and/or other bands.
  • bands or simply, “bands”
  • LTE Release 1 1 defines 35 bands, which are referred to as LTE/UMTS bands and are listed in a publicly available document 3 GPP TS 36.101.
  • Wireless device 1 10 may support one or more LTE/UMTS bands and/or other bands.
  • Wireless device 1 10 may support carrier aggregation, which is operation on multiple carriers.
  • Carrier aggregation may also be referred to as multi-carrier operation.
  • a carrier may refer to a range of frequencies used for communication and may be associated with certain characteristics. For example, a carrier may be associated with system information and/or control information describing operation on the carrier.
  • a carrier may also be referred to as a component carrier (CC), a frequency channel, a cell, etc.
  • CC component carrier
  • a band may include one or more carriers.
  • Each carrier may cover up to 20 MHz in LTE.
  • Wireless device 1 10 may be configured with up to 5 carriers in one or two bands in LTE Release 11.
  • Wireless device 110 may concurrently receive multiple transmitted signals at different frequencies.
  • wireless device 110 may support dual SIM/dual standby (DSDS) and/or dual SIM/dual-active (DSD A) and may be able to concurrently communicate with multiple wireless systems such as LTE and GSM systems, or TD-SCDMA and GSM systems, or CDMA and GSM systems, etc.
  • DSDS dual SIM/dual standby
  • DSD A dual SIM/dual-active
  • FIG. 8 shows a block diagram of an exemplary design of a portion of a receiver
  • Receiver 820 supporting carrier aggregation on multiple bands.
  • Receiver 820 includes multiple (K) LNAs 830a to 830k and multiple (M) load circuits 880a to 880m, where K and M may each be any integer greater than one.
  • the K LNAs 830a to 830k may support K bands Bi to ⁇ _, respectively, and may receive K input RF signals RFinl to RFinK, respectively, for the K bands.
  • Each LNA 830 may receive an input RF signal for a specific band and may have up to M outputs coupled to up to M load circuits 880a to 880m.
  • Each load circuit 880 may have its input coupled to one output of each LNA 830 and its output coupled to a respective downconverter (not shown in FIG. 8).
  • the M load circuits 880a to 880m may be coupled to M downconverters, which may be used to concurrently receive downlink signals sent on M sets of carriers, e.g., for carrier aggregation.
  • any number of LNAs may be used to support any number of bands.
  • Each LNA may include one or more inputs for one or more bands and one or more outputs coupled to one or more load circuits.
  • the LNAs may have (i) the same or different numbers of inputs and (ii) the same or different numbers of outputs.
  • the LNAs may be coupled to any number of load circuits.
  • FIG. 9A shows a schematic diagram of an exemplary design of a single-input multiple-output (SIMO) LNA 930a with configurable mutually-coupled source degeneration inductors.
  • LNA 930a may be used for any of LNAs 230 and 232 in FIG. 2 or any of LNAs 830 in FIG. 8.
  • LNA 930a includes a programmable inductor 932, a gain transistor 934, and two cascode transistors 936 and 938.
  • An input matching circuit 912 has one end receiving an input RF signal (RFin) and the other end coupled to the gate of gain transistor 934.
  • Gain transistor 934 has its source coupled to one end of inductor 932 and its drain coupled to the sources of cascode transistors 936 and 938. Inductor 932 is further coupled to circuit ground.
  • Cascode transistor 936 has its gate receiving a first control signal (Venl) and its drain coupled to a load circuit 980.
  • Cascode transistor 938 has its gate receiving a second control signal (Ven2) and its drain coupled to a load circuit 990.
  • Gain transistor 934 and cascode transistors 936 and 938 may be implemented with NMOS transistors, as shown in FIG. 9A, or with transistors of other types.
  • programmable inductor 932 includes two configurable mutually-coupled source degeneration inductors 942 and 944 coupled in parallel.
  • Inductor 942 is coupled between the source of gain transistor 934 and circuit ground.
  • Inductor 944 is coupled in series with a transistor 946, and the series combination is coupled between the source of gain transistor 934 and circuit ground.
  • Transistor 946 operates as a switch that may be closed or opened.
  • Inductor 942 has an inductance of LI
  • inductor 944 has an inductance of L2.
  • FIG. 9A shows SIMO LNA 930a including two cascode transistors 936 and 938 to provide up to two output RF signals to up to two load circuits 980 and 990, e.g., for up to two sets of carriers being received concurrently for carrier aggregation.
  • a SIMO LNA may include N cascode transistors coupled to N load circuits to provide up to N output RF signals, where N may be any integer value greater than one.
  • SIMO LNA 930a may operate in a single-output mode or a multi-output mode at any given moment.
  • LNA 930a receives an input RF signal comprising at least one transmitted signal (e.g., on one set of carriers) and provides one output RF signal via one cascode transistor 936 or 938 to one downconverter circuit.
  • LNA 930a receives an input RF signal comprising at least two transmitted signals (e.g., on two sets of carriers) and provides two output RF signals via two cascode transistors 936 or 938 to two downconverter circuits (e.g., one output RF signal for each set of carriers). Each downconverter downconverts its output RF signal with a separate LO signal at the proper frequency.
  • the nominal bias current may be selected to obtain a desired dynamic range for LNA 930a in the single- output mode.
  • the higher bias current may be selected to obtain a desired dynamic range for LNA 930a in the multi-output mode.
  • the higher bias current may be selected to obtain similar dynamic range for LNA 930a in the multi-output mode as in the single-output mode.
  • Increasing (e.g., doubling) the bias current of gain transistor 934 would reduce the gain of LNA 930a in the multi-output mode. Furthermore, increasing the bias current may degrade input matching of LNA 930a in the multi-output mode. It may not be possible to input match LNA 930a with a single matching circuit component, e.g., an inductor.
  • the gain, dynamic range, and input matching of an LNA in the multi-output mode may be preserved by using a programmable source degeneration inductor.
  • the gain of the LNA may be reduced in the multi-output mode due to the use of higher bias current to maintain the desired dynamic range.
  • the source degeneration inductor may be reduced in the multi-output mode in order to boost the gain of the LNA. Reducing the source degeneration inductor may also improve input matching of the LNA in the multi-output mode.
  • LNA 930a may operate with (i) a nominal source degeneration inductance of Loff in the single-output mode or (ii) a smaller source degeneration inductance of Lon in the multi-output mode, where Lon ⁇ Loff .
  • transistor 946 may be turned OFF via a low voltage on the Mode signal, only inductor 942 may be coupled between the source of gain transistor 934 and circuit ground, inductor 944 may be disconnected from circuit ground, and the nominal source degeneration inductance may be provided by only inductor 942.
  • Inductor 942 may be designed to provide a desired source degeneration inductance of Loff in the single-output mode, where Loff may be given as shown in equation (1).
  • transistor 946 may be turned ON via a high voltage on the Mode signal, both inductors 942 and 944 may be coupled between the source of gain transistor 934 and circuit ground, and a smaller source degeneration inductance may be provided by the parallel combination of mutually -coupled inductors 942 and 944.
  • Inductors 942 and 944 may be designed with the proper inductances and coupling coefficient to obtain a desired source degeneration inductance of Lon in the multi-output mode, where Lon may be given as shown in equation (2).
  • LNA 930a may support multiple gain settings in the single-output mode and/or the multi-output mode. For example, a high-gain setting and a low-gain setting may be supported in the multi-output mode.
  • the high-gain setting may be used to obtain higher gain with a smaller source degeneration inductance, which may be obtained by turning ON transistor 946.
  • the low-gain setting may be used to obtain a lower gain with a larger source degeneration inductance, which may be obtained by turning OFF transistor 946.
  • Different gains may also be supported in each gain setting of each mode by varying the bias current of gain transistor 934.
  • FIG. 9B shows a schematic diagram of an exemplary design of a SIMO LNA
  • LNA 930b with configurable mutually-coupled source degeneration inductors.
  • LNA 930b may be used for any of LNAs 230 and 232 in FIG. 2 or any of LNAs 830 in FIG. 8.
  • LNA 930b includes all of the circuit components in LNA 930a in FIG. 9A.
  • LNA 930b further includes a second gain transistor 954, a second programmable inductor 952, and cascode transistors 956 and 958.
  • Gain transistor 954 has its gate coupled to the output of input matching circuit 912, its source coupled to programmable inductor 952, and its drain coupled to the sources of cascode transistors 956 and 958.
  • Programmable inductor 952 is further coupled to circuit ground.
  • Cascode transistor 956 has its gate receiving a third control signal (Ven3) and its drain coupled to load circuit 980.
  • Cascode transistor 958 has its gate receiving a fourth control signal (Ven4) and its drain coupled to load circuit 990.
  • programmable inductor 952 includes two configurable mutually-coupled source degeneration inductors 962 and 964 coupled in parallel.
  • Inductor 962 is coupled between the source of gain transistor 954 and circuit ground.
  • Inductor 964 is coupled in series with a transistor 966, and the series combination is coupled between the source of gain transistor 954 and circuit ground.
  • Transistor 956 operates as a switch that may be closed or opened.
  • each gain transistor is coupled to a separate programmable inductor.
  • one gain transistor e.g., gain transistor 934
  • the other gain transistor may be coupled to a fixed inductor.
  • one gain transistor e.g., gain transistor 934
  • the other gain transistor may be coupled directly to circuit ground.
  • SIMO LNA 930b may operate in a single-output mode or a multi-output mode at any given moment.
  • both gain transistors 934 and 954 may be enabled, and two cascode transistors may be enabled.
  • Cascode transistors 936 and 956 may be enabled to generate a first output RF signal (RFoutl) for load circuit 980, and cascode transistors 938 and 958 may be disabled.
  • cascode transistors 938 and 958 may be enabled to generate a second output RF signal (RFout2) for load circuit 990, and cascode transistors 936 and 956 may be disabled.
  • one gain transistor 934 or 954 may be enabled, and one cascode transistor may be enabled.
  • one or both source degeneration inductors may be selected for each gain transistor that is enabled in order to obtain the desired dynamic range, gain, and input matching for LNA 930b in the single-output mode.
  • both gain transistors 934 and 954 may be enabled.
  • Cascode transistors 936 and 958 may be enabled to generate the RFoutl and RFout2 signals for load circuits 980 and 990, respectively, and cascode transistors 938 and 956 may be disabled. Alternatively, all four cascode transistors 936, 938, 956 and 958 may be enabled. One or both source degeneration inductors may be selected for each gain transistor in order to obtain the desired dynamic range, gain, and input matching for LNA 930b in the multi-output mode.
  • FIG. 9C shows a schematic diagram of an exemplary design of a SIMO LNA
  • LNA 930c with configurable mutually-coupled source degeneration inductors.
  • LNA 930c may be used for any of LNAs 230 and 232 in FIG. 2 or any of LNAs 830 in FIG. 8.
  • LNA 930c includes all of the circuit components in LNA 930b in FIG. 9B, except for programmable inductor 952, which is omitted from LNA 930c.
  • Gain transistors 934 and 944 have their sources coupled together and to programmable inductor 932, which is further coupled to circuit ground.
  • SIMO LNA 930c may operate in a single-output mode or a multi-output mode at any given moment.
  • One or more gain transistors and one or more cascode transistors may be enabled for each mode, as described above for FIG. 9B.
  • In the single-output mode only inductor 942 may be selected, and inductor 944 may be disconnected by turning OFF transistor 946.
  • In the multi-output mode both inductors 942 and 944 may be selected by turning ON transistor 946.
  • Inductor 942 may be designed to provide the desired gain, dynamic range, and input matching for LNA 930c in the single-output mode.
  • Inductors 942 and 944 may be designed to provide the desired gain, dynamic range, and input matching for LNA 930c in the multi-output mode.
  • FIG. 9D shows a schematic diagram of an exemplary design of a MIMO LNA
  • LNA 930d with configurable mutually-coupled source degeneration inductors.
  • LNA 930d may be used for any of LNAs 230 and 232 in FIG. 2 or any of LNAs 830 in FIG. 8.
  • LNA 930d includes all of the circuit components in LNA 930b in FIG. 9B.
  • gain transistors 934 and 954 are not coupled together as in LNA 930b. Instead, gain transistors 934 and 954 receive different input RF signals, e.g., for different bands.
  • Gain transistor 934 has its gate coupled to input matching circuit 912, which receives a first input RF signal (RFinl).
  • Input matching circuit 912 may perform input matching for LNA 93 Od for a first band.
  • Gain transistor 954 has its gate coupled to an input matching circuit 916, which receives a second input RF signal (RFin2).
  • Input matching circuit 916 may perform input matching for LNA 930d for a second band.
  • MIMO LNA 930d may operate in a single-output mode, a SIMO mode, or a
  • one input RF signal (e.g., RFinl or RFin2) may be amplified by one gain transistor (e.g., gain transistor 934 or 954) and buffered by one cascode transistor (e.g., cascode transistor 936, 938, 956 or 958) to obtain one output RF signal (e.g., RFoutl or RFout2) for one load circuit (e.g., load circuit 980 or 990).
  • one gain transistor e.g., gain transistor 934 or 95
  • cascode transistor e.g., cascode transistor 936, 938, 956 or 95
  • one input RF signal (e.g., RFinl or RFin2) may be amplified by one gain transistor (e.g., gain transistor 934 or 954) and buffered by two cascode transistors (e.g., cascode transistors 936 and 938 or cascode transistors 956 and 958) to obtain two output RF signals (e.g., RFoutl and RFout2) for two load circuits (e.g., load circuits 980 and 990).
  • one gain transistor e.g., gain transistor 934 or 954
  • cascode transistors e.g., cascode transistors 936 and 938 or cascode transistors 956 and 948
  • two input RF signals may be amplified by two gain transistors (e.g., gain transistors 934 and 954) and buffered by two cascode transistor (e.g., cascode transistors 936 and 956 or cascode transistors 938 and 958) to obtain two output RF signals (e.g., RFoutl and RFout2) for two load circuits (e.g., load circuits 980 and 990).
  • two gain transistors e.g., gain transistors 934 and 954
  • cascode transistor e.g., cascode transistors 936 and 956 or cascode transistors 938 and 95
  • Programmable inductors 932 and 952 may be operated to provide good performance in the single-output mode, the SIMO mode, and the MIMO mode.
  • programmable inductor 932 When gain transistor 934 is enabled in the single-output mode or the MIMO mode, programmable inductor 932 may be set (e.g., by turning OFF transistor 946) such that inductor 942 provides a nominal source degeneration inductance.
  • programmable inductor 932 may be set (e.g., by turning ON transistor 946) such that inductors 942 and 944 provide a smaller source degeneration inductance.
  • programmable inductor 952 may be set (e.g., by turning OFF transistor 966) such that inductor 962 provides a nominal source degeneration inductance.
  • programmable inductor 952 may be set (e.g., by turning ON transistor 966) such that inductors 962 and 964 provide a smaller source degeneration inductance.
  • FIGS. 4, 5A-5B, and 9A-9D show some exemplary circuit designs of LNAs with configurable mutually-coupled source degeneration inductors.
  • An LNA with configurable mutually-coupled source degeneration inductors may also be implemented in other manners.
  • an LNA may include a feedback circuit coupled between an output and an input of the LNA.
  • the feedback circuit may comprise a resistor, a capacitor, a transistor, some other circuit component, or a combination thereof.
  • the feedback circuit may help with input matching and may also improve linearity of the LNA.
  • an LNA may include a cascode circuit in place of each cascode transistor.
  • the cascode circuit may include (i) a first cascode transistor coupled between the drain of a gain transistor and an intermediate node, (ii) a second cascode transistor coupled between the intermediate node and an output of the LNA, and (iii) a shunt transistor coupled between the intermediate node and circuit ground.
  • the first and second cascode transistors may be turned ON to provide an output RF signal via the LNA output, and the shunt transistor may be turned OFF.
  • the first and second cascode transistors may be turned OFF to provide no output RF signal at the LNA output, and the shunt transistor may be turned ON to pull the intermediate node to circuit ground and provide better isolation between the LNA output and the gain transistor. Better isolation may be especially desirable when the same load circuit is reused by multiple gain transistors for different LNAs.
  • Amplifiers with configurable mutually-coupled source degeneration inductors may provide various advantages.
  • these amplifiers may support multiple operating modes such as, e.g., a single-output mode and a multi-output mode for carrier aggregation.
  • the amplifiers may also provide good performance (e.g., good dynamic range, gain, input matching, etc.) for all supported operating modes.
  • the amplifiers may support multiple gain states such as, e.g., a low-gain state and a high-gain state. Different gain states may be applicable for different operating scenarios. For example, the low-gain state may be selected to improve linearity when jammers are present in an input RF signal.
  • the mutually-coupled inductors may be efficiently implemented in a smaller circuit area, e.g., as shown in FIGS. 7A and 7B. There may be other advantages to the amplifiers disclosed herein.
  • an apparatus may include a gain transistor and a plurality of inductors, which may implement an amplifier or some other circuit.
  • the gain transistor e.g., gain transistor 434 in FIG. 4
  • the plurality of inductors may be mutually coupled, may be coupled to the gain transistor, and may provide a programmable source degeneration inductance for the gain transistor.
  • the plurality of inductors may include first and second inductors.
  • the first inductor e.g., inductor 442 may be coupled between the source of the gain transistor and circuit ground.
  • the second inductor e.g., inductor 444) may be coupled in series with a switch (e.g., transistor 446) and between the source of the gain transistor and circuit ground.
  • the first and second inductors may have a positive coupling coefficient and, when the switch is closed, may provide a source degeneration inductance (Lon) that is larger than the parallel combination of the first and second inductors.
  • the first and second inductors may have a negative coupling coefficient and, when the switch is closed, may provide a source degeneration inductance that is smaller than the parallel combination of the first and second inductors.
  • an inductor e.g., inductor 558 in FIG. 5B
  • This inductor may be a parasitic inductor.
  • the negative coupling coefficient may reduce the source degeneration inductance observed by the gain transistor when the switch is closed.
  • the first inductor may be formed by a first conductor
  • the second inductor may be formed by a second conductor (e.g., conductor 754 in FIG. 7A or conductor 764 in FIG. 7B) having a second spiral pattern.
  • the second conductor may be located within the first spiral pattern of the first conductor, e.g., as shown in FIGS. 7A and 7B.
  • the first and second spiral patterns may be formed in same direction to obtain a positive coupling coefficient for the first and second inductors, e.g., as shown in FIG. 7A.
  • the first and second spiral patterns may be formed in opposite direction to obtain a negative coupling coefficient for the first and second inductors, e.g., as shown in FIG. 7B.
  • the apparatus may further include first and second cascode transistors, e.g., for a SIMO LNA.
  • the first cascode transistor e.g., cascode transistor 936 in FIG. 9A
  • the second cascode transistor e.g., cascode transistor 938
  • Either the first or second cascode transistor may be enabled in a first operating mode, e.g., a single-output mode.
  • the first and second cascode transistors may both be enabled in a second operating mode, e.g., a multi-output mode.
  • the plurality of inductors may provide a first source degeneration inductance in the first operating mode or a second source degeneration inductance in the second operating mode.
  • the second source degeneration inductance may be less than the first source degeneration inductance.
  • the apparatus may further include a second gain transistor, third and fourth cascode transistors, and a second plurality of inductors, e.g., for a SIMO LNA or a MIMO LNA.
  • the second gain transistor e.g., gain transistor 954 in FIG. 9B or 9D
  • the second plurality of inductors may receive the input signal (e.g., for a SIMO LNA) or a second input signal (e.g., for a MIMO LNA) and may provide a second amplified signal.
  • the second plurality of inductors e.g., inductors 962 and 964 in FIG.
  • the third cascode transistor (e.g., cascode transistor 956 in FIG. 9B or 9D) may be coupled to the second gain transistor and, when enabled, may receive the second amplified signal and provide the first output signal.
  • the fourth cascode transistor (e.g., cascode transistor 958) may be coupled to the second gain transistor and, when enabled, may receive the second amplified signal and provide the second output signal.
  • FIG. 10 shows an exemplary design of a process 1000 for performing amplification.
  • An input signal may be amplified with a gain transistor to obtain an amplified signal (block 1012).
  • a programmable source degeneration inductance may be provided for the gain transistor with a plurality of mutually-coupled inductors (block 1014).
  • the plurality of mutually-coupled inductors may include first and second inductors.
  • a first source degeneration inductance may be provided for the gain transistor based on the first inductor.
  • a second source degeneration inductance may be provided for the gain transistor based on a parallel combination of the first and second inductors.
  • the first and second inductors may have a positive coupling coefficient, and the second source degeneration inductance may be larger than the parallel combination of the first and second inductors.
  • the first and second inductors may have a negative coupling coefficient, and the second source degeneration inductance may be smaller than the parallel combination of the first and second inductors.
  • the amplifiers with configurable mutually-coupled source degeneration inductors described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronic device, etc.
  • the amplifiers may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), NMOS, PMOS, bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.
  • CMOS complementary metal oxide semiconductor
  • NMOS NMOS
  • PMOS bipolar junction transistor
  • BiCMOS bipolar-CMOS
  • SiGe silicon germanium
  • GaAs gallium arsenide
  • HBTs heterojunction bipolar transistors
  • HEMTs high electron mobility transistors
  • An apparatus implementing the amplifiers described herein may be a stand-alone device or may be part of a larger device.
  • a device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.
  • RFR RF receiver
  • RTR RF transmitter/receiver
  • MSM mobile station modem
  • the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
  • Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage media may be any available media that can be accessed by a computer.
  • such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
  • any connection is properly termed a computer-readable medium.
  • the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
  • the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.
  • Disk and disc includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

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Abstract

L'invention concerne des amplificateurs à inductances de contre-réaction de source couplées mutuellement configurables. Dans un exemple de conception, un appareil (par exemple, un dispositif sans fil ou un circuit intégré) comprend un transistor à gain et une pluralité d'inductances, qui peuvent mettre en œuvre un amplificateur. Le transistor à gain reçoit un signal d'entrée et fournit un signal amplifié. La pluralité d'inductances est couplée mutuellement, est couplée au transistor à gain, et fournit une inductance de contre-réaction de source programmable pour le transistor à gain. Les inductances peuvent avoir un coefficient de couplage positif et peuvent fournir une plus grande inductance de contre-réaction de source. Alternativement, les inductances peuvent avoir un coefficient de couplage négatif et peuvent fournir une plus petite inductance de contre-réaction de source.
PCT/US2014/048764 2013-08-01 2014-07-30 Amplificateurs avec inductances de contre-réaction de source couplées mutuellement configurables WO2015017487A1 (fr)

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KR1020167004709A KR101650846B1 (ko) 2013-08-01 2014-07-30 구성가능한 상호 커플링된 소스 디제너레이션 인덕터들을 갖는 증폭기들
CN201480042528.3A CN105409116B (zh) 2013-08-01 2014-07-30 具有可配置的相互耦合的源极退化电感器的放大器
JP2016525604A JP6110034B2 (ja) 2013-08-01 2014-07-30 構成可能な相互結合ソースディジェネレーションインダクタを持つ増幅器
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US11476819B2 (en) 2016-08-31 2022-10-18 Skyworks Solutions, Inc. Providing a constant impedance at an input of a signal amplifier for different gain modes

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CN105409116A (zh) 2016-03-16
CN105409116B (zh) 2017-07-28
EP3028381A1 (fr) 2016-06-08
US9154087B2 (en) 2015-10-06
US20150035600A1 (en) 2015-02-05
JP6110034B2 (ja) 2017-04-05
JP2016524432A (ja) 2016-08-12
KR101650846B1 (ko) 2016-08-24
KR20160028492A (ko) 2016-03-11

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