WO2015014282A1 - 绝缘栅双极型晶体管的制造方法 - Google Patents

绝缘栅双极型晶体管的制造方法 Download PDF

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Publication number
WO2015014282A1
WO2015014282A1 PCT/CN2014/083278 CN2014083278W WO2015014282A1 WO 2015014282 A1 WO2015014282 A1 WO 2015014282A1 CN 2014083278 W CN2014083278 W CN 2014083278W WO 2015014282 A1 WO2015014282 A1 WO 2015014282A1
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Prior art keywords
semiconductor substrate
gate bipolar
bipolar transistor
insulated gate
layer
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PCT/CN2014/083278
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English (en)
French (fr)
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邓小社
芮强
张硕
王根毅
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无锡华润上华半导体有限公司
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Publication of WO2015014282A1 publication Critical patent/WO2015014282A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors

Definitions

  • the invention belongs to the technical field of power semiconductor devices, and relates to an insulated gate bipolar transistor (IGBT), in particular to a field-stop insulated gate bipolar transistor ( Preparation method of FS-IGBT).
  • IGBT insulated gate bipolar transistor
  • Preparation method of FS-IGBT Preparation method of FS-IGBT
  • IGBT Insulated Gate Bipolar Transistor, insulated gate bipolar transistor
  • VDMOS Very Double-diffused MOSFET, vertical double-diffused field effect transistor
  • the FS-IGBT Field-Off Insulated Gate Bipolar Transistor
  • PT-IGBT Pass-In Insulated Gate Bipolar Transistor
  • NPT-IGBT Non-Passed Insulated Gate Bipolar Transistor
  • FS-IGBT Utilizing an N-type field stop layer to make the electric field distribution by NPT
  • the triangular distribution of the type is converted to a trapezoidal distribution, which shortens the thickness of the device and greatly reduces the conduction voltage drop and loss of the device. However, this adds difficulty to the process. At present, it is usually used to do the frontal process, and the back sheet is back-injected to introduce FS.
  • FS-IGBT planar field-off insulated gate bipolar transistor
  • the traditional FS-IGBT process flow is shown in Figure 12.
  • the N+ buffer layer compensates for the inadequacy of the NPT-IGBT with a thicker pressure-resistant layer N-zone.
  • PT In the structure, there is an N+ buffer layer between the N-base region and the P+ emitter region, and the N-type doping concentration of the layer is much higher than that of the N-base region, and the electric field between them is trapezoidal at right angles, and the thickness of the base region is thin.
  • its temperature coefficient of resistance is not ideal, which is not conducive to the realization of self-average flow effect of multi-chip parallel connection.
  • FS Buffer layer doping concentration ratio PT in type structure
  • the N+ concentration of the buffer layer is low, but higher than the N-concentration of the base region, so the distribution of the electric field is obliquely trapezoidal, and the base region can be significantly thinned, but the characteristics of the positive temperature coefficient can be retained. Of course, this kind of production is more difficult.
  • FS-IGBT The buffer layer is formed by ion implantation and then annealed, before the surface of the metal-oxide-semiconductor field (metal-oxide-semiconductor field)
  • MOSFET metal-oxide-semiconductor field
  • the annealing time is too long after ion implantation, the temperature is too high, which will inevitably lead to surface MOSFET.
  • the depth of each p-n junction in the structure changes, and the surface MOSFET has been fabricated
  • the aluminum layer of the structure limits the annealing temperature to be below 500 °C. Therefore, considering this point, the N+ buffer layer of the FS-IGBT can only be made to 1 ⁇ m. Left and right. However, it is very unsafe to use such a thin buffer layer to make a strong electric field stop layer, so the process requirements are high.
  • a method of fabricating an insulated gate bipolar transistor comprising: providing a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first major surface and a second major surface; and a second major surface of the semiconductor substrate Forming a field stop layer of a first conductivity type; selectively forming a base region of a second conductivity type on a first major surface of the semiconductor substrate; a first host of the semiconductor substrate on which the base region is formed Forming the first main surface structure of the insulated gate bipolar transistor; and continuing to form the remaining of the insulated gate bipolar transistor on the second main surface of the semiconductor substrate on which the field stop layer is formed The second main surface structure.
  • the forming the first main surface structure of the insulated gate bipolar transistor on the first main surface of the semiconductor substrate on which the base region is formed includes: forming Forming a gate oxide layer on the first main surface of the semiconductor substrate of the base region; depositing a polysilicon layer on the gate oxide layer; selectively performing photolithography on the gate oxide layer and the polysilicon layer An etching process produces an active region implantation window, and implants impurities of a first conductivity type into the base region from the active region implantation window to form an active region; forming a dielectric on the polysilicon layer etched with the implantation window a layer of selective lithography on the dielectric layer, etching a contact hole in contact with the active region and the base region; forming a metal layer on the dielectric layer to form the insulated gate bipolar The first electrode of the transistor.
  • the remaining second main surface structure of the insulated gate bipolar transistor continues to be formed on the second main surface of the semiconductor substrate on which the field stop layer is formed.
  • a second main surface of the semiconductor substrate is implanted with impurities of a second conductivity type to form an implantation region; a metal layer is formed on the implantation region to form a second electrode of the insulated gate bipolar transistor.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the active region is an N+ active region
  • the implantation region is a P+ collector region
  • the first electrode is an emission.
  • the second electrode is a collector.
  • a field stop layer of a first conductivity type is formed on the second major surface of the semiconductor substrate by ion implantation, a high temperature push-well, and an activation process.
  • the base region of the second conductivity type is selectively formed on the first major surface of the semiconductor substrate by ion implantation, high temperature push-well, and activation process.
  • the gate oxide layer is formed by thermal oxidation.
  • the step of forming the gate oxide layer by thermal oxidation comprises:
  • the silicon wafer is dry oxygened at 800 ° C ⁇ 850 ° C for 5 min;
  • the dose of ion implantation when forming the field stop layer of the first conductivity type is from 1E12/cm 2 to 1E14/cm 2 .
  • the field stop layer has a thickness of 15 ⁇ m to 30 ⁇ m.
  • the above-described method of manufacturing the insulated gate bipolar transistor advances the FS region of the back surface and the second type well region of the front surface before the formation of the gate oxide layer. Since the thicker FS is formed first, the device characteristics such as the front surface MOSFET of the silicon wafer to be fabricated are not affected. The high temperature process of the front device of the silicon wafer has little effect on the FS region of 20 ⁇ m to 30 ⁇ m thick. Before the formation of the gate oxide layer, the second type of well region is formed, which simplifies the subsequent process and is less likely to cause a latch-up effect, thereby improving the reliability of the product; meanwhile, the second type impurity is required for the backside ion implantation of the collector region, and the back surface is collected.
  • the activation of the second type of impurity in the region is activated by the thermal process of annealing, and the activation rate is high, and the damage caused by ion implantation can also be eliminated.
  • the method of forming the gate oxide layer is a low-temperature thermal oxidation method, and the grown thin gate oxide layer has Low interface state density, high breakdown voltage, low charge density, few pinholes, few defects, and uniform thickness. Therefore, it is possible to produce an insulated gate bipolar transistor having high breakdown voltage, low leakage, a positive temperature coefficient of conduction voltage drop, low switching loss, and high process reliability.
  • the above method uses a second type of heavily doped collector region on the back surface of the silicon wafer, and the second type impurity is easily concentrated on the silicon-silicon dioxide interface while being protected, so that the second The second type impurity distribution optimization in the type heavily doped collector region - the interface in contact with the back metal has a high doping concentration, and the interface in contact with the first type silicon has a low doping concentration.
  • it is easy to form good ohmic contact with the back metal on the other hand, it is beneficial to control PNP. The emission efficiency and improve the AC characteristics of the IGBT device.
  • FIG. 1 is a flow chart of a method of fabricating an FS-IGBT according to an embodiment
  • FIG. 2 is a schematic diagram of fabricating an FS region on the back side of a silicon wafer, in accordance with an embodiment
  • 3 to 4 are schematic views showing a process of forming a P well region according to an embodiment
  • 5-6 are schematic diagrams of processes for forming a gate oxide layer and a polysilicon layer according to an embodiment
  • FIG. 7 is a schematic diagram of forming a polysilicon gate and a first source region and a second source region, in accordance with an embodiment
  • FIG. 8 is a schematic view of forming a dielectric layer and a metal layer in accordance with an embodiment
  • FIG. 9 is a schematic view of forming a metal wiring layer according to an embodiment
  • Figure 10 is a schematic illustration of forming a collector region in accordance with an embodiment
  • Figure 11 is a schematic illustration of forming a back metal layer in accordance with an embodiment
  • Figure 12 is a schematic diagram of a prior art fabrication of an FS-IGBT.
  • the prior art FS-IGBT is based on a low-doped n-type single wafer, and a MOS structure is formed on the front side. Then, the silicon wafer is thinned from the back side to the thickness required for the withstand voltage, and then ion implantation is performed from the back side to obtain n.
  • a field stop layer (equivalent to an n-type buffer layer of a PT-IGBT) and a p-type collector region. Due to the thin and light doping of the collector region, the injection efficiency of the collector junction is very low.
  • the collector area is “transparent” to electronics. This allows the FS-IGBT to achieve faster switching times while maintaining a lower on-state voltage and maintain the positive temperature coefficient of the on-state voltage as determined by the mobility.
  • the manufacturing process of the FS-IGBT is complicated and lagging, the production cost is high, and the problem of low reliability of the product due to the backside thinning process is not solved.
  • the first embodiment of the present invention uses a silicon wafer as a semiconductor substrate, and relates to a method for fabricating an FS-IGBT device. The specific process is shown in FIG.
  • the semiconductor substrate in this embodiment may include a semiconductor element such as single crystal, polycrystalline or amorphous silicon or silicon germanium (SiGe), and may also include a mixed semiconductor structure such as silicon carbide or germanium. Indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof; or silicon-on-insulator (SOI). Further, the semiconductor substrate may further include other materials such as an epitaxial layer or a buried layer multilayer structure. Although a few examples of materials that can form a semiconductor substrate are described herein, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.
  • first conductivity type a first conductivity type and a second conductivity type
  • first conductivity type P-type
  • second conductivity type N-type
  • first conductivity type N-type
  • second conductivity type P-type
  • the face where the emitter and gate of the IGBT are located is generally understood to be the first major face, while the face on which the collector of the IGBT is located is generally understood to be the second major face.
  • the FS area is actually fabricated on the back side of the silicon wafer.
  • N Type ion implantation and high temperature push wells form the FS region.
  • the N-type silicon wafer is first selected, and the N-doping concentration and thickness are selected according to the required IGBT characteristics. For example, the higher the breakdown voltage, the lower the N-doping concentration requirement and the thicker the thickness requirement.
  • An N-type ion such as phosphorus, arsenic, antimony, sulfur or selenium is implanted on the back side of the silicon wafer at a dose of 1E12/cm 2 to 1E14/cm 2 and the well is pushed at a high temperature. The temperature and time are adjusted to diffuse the N-type impurity to the desired thickness, i.e., the FS region 101 is formed, as shown in Fig. 2, and impurity activation is also completed.
  • the annealing temperature is selected from 1150 ° C to 1250 ° C for 10 hours to 20 hours, and the FS region 101 of 15 ⁇ m to 30 ⁇ m can be formed.
  • the annealing temperature is selected from 1150 ° C to 1250 ° C for 10 hours to 20 hours, and the FS region 101 of 15 ⁇ m to 30 ⁇ m can be formed.
  • a photoresist pattern of the first P well region 201 and the second P well region 202 is formed by a photolithography process, and then the photoresist pattern is used as a mask for ion implantation.
  • the ion implantation layer 203 of the first P well region and the ion implantation layer 204 of the second P well region are formed in a manner; then, referring to FIG. 4, the photoresist layer is removed, and the first P well region is ion implanted by a thermal annealing process.
  • Layer 203 and ion implantation layer 204 of the second P-well region are pushed to sink and activate the implanted P
  • the type of impurity forms the first P well region 201 and the second P well region 202, and the thermal annealing process of this step can also employ a rapid thermal annealing process.
  • a gate oxide layer 301 is formed over the silicon wafer by a thermal oxidation growth process.
  • a polysilicon layer 302 is deposited over the gate oxide layer 301 to fabricate the gate.
  • a gate oxide layer 301 is formed on the surface of the silicon wafer.
  • the gate oxide layer 301 in this embodiment includes at least silicon oxide.
  • the gate oxide layer 301 may be formed by one-time growth of the gate on the surface of the silicon wafer.
  • the gate oxide layer 301 is formed by a thermal oxidation method at a lower temperature than a conventional high-temperature process, specifically, first, dry oxygen is performed at 800 ° C to 850 ° C for 5 min, and then an oxide layer is required according to requirements.
  • the thickness is H 2 -O 2 synthetic oxidation, and then dried at 800 ° C ⁇ 850 ° C for 3 min ⁇ 5 min, and finally annealed in N 2 atmosphere for 20 min ⁇ 30 min at 860 ° C ⁇ 875 ° C; this is because the continuous high temperature process will be greatly Increasing the interface charge of the gate and buried SiO 2 layer and the lattice defect density of silicon, resulting in high device leakage current, which reduces the reliability and radiation resistance of the device, while low temperature thermal oxidation can suppress defects such as stacking faults.
  • the growth and segregation of impurities in the channel region is H 2 -O 2 synthetic oxidation, and then dried at 800 ° C ⁇ 850 ° C for 3 min ⁇ 5 min, and finally annealed in N 2 atmosphere for 20 min ⁇ 30 min at 860 ° C ⁇ 875 ° C; this is because the continuous high temperature process will be greatly Increasing the interface charge of the gate and buried SiO 2 layer and the la
  • a polysilicon layer 302 is deposited on the gate oxide layer 301, and a photoresist layer having a gate region pattern is formed on the surface of the gate polysilicon layer by a photolithography process, followed by a photoresist having a gate region pattern.
  • the layer is a mask, and the polysilicon gate 401 is formed by dry etching (see FIG. 7).
  • the polysilicon layer 302 may be formed by chemical vapor deposition, physical vapor deposition or other methods, which is not specifically limited in this embodiment. .
  • a polysilicon gate 401 is formed by photolithography and etching processes, and a first P well region 201 and a second P well are formed on both sides of the polysilicon gate 401 by ion implantation and annealing processes.
  • An N-type heavily doped first source region 402 and a second source region 403 are formed in the regions 202, respectively.
  • a dielectric is formed in the step 500 to form a dielectric layer 501 surrounding a side surface and a top surface of the polysilicon gate 401 (see FIG. 7), and a contact hole is etched in the dielectric layer 501.
  • a metal and planarization process (such as a tungsten plug process) is deposited, a surface metal layer 502 is deposited on the surface of the silicon wafer, and then the metal layer 502 is photolithographically and etched to form a metal wiring layer 503.
  • the silicon wafer profile after completion of these steps is shown in Figure 9. Shown.
  • Step 600 referring to FIG. 10, ion implantation of a P-type impurity on the back surface of the N-type heavily doped field FS region 101 to form a P-type heavily doped collector region 601.
  • the ion-implanted P-type impurity is, for example, an impurity containing a boron element such as boron (B) or boron difluoride (BF 2 ).
  • the energy of ion implantation is, for example, 20 KeV to 80 KeV, and the dose is, for example, 1E13/cm 2 to 1E15/cm 2 .
  • the annealing temperature is selected between 350 ° C and 550 ° C, and the annealing time is 20 min - 200 min to ensure that the back collector region 601 diffuses slowly under the premise of ensuring a large activation rate, and forms the collector region 601 and the FS region 101.
  • the PN junction depth is less affected.
  • step 700 the residual layer on the back side of the silicon wafer is removed to form a back metal layer 701.
  • the silicon wafer is dried on the front side of the silicon wafer, and the residual layer is removed by a conventional dry method or a wet method. Marked), conventional dry degumming forms a back metal layer 701.
  • the FS region on the back side and the P-well region on the front side are not completing the IGBT.
  • the MOSFET is fabricated and post-grinded, but advanced until the gate oxide layer is formed.
  • the field termination FS region is formed on the back side of the silicon wafer to form the FS of the desired thickness, and then the device such as the front MOSFET is fabricated. Since the thicker FS is formed first, the device characteristics such as the front surface MOSFET of the silicon wafer to be fabricated are not affected.
  • the high temperature process of the front device of the silicon wafer has little effect on the FS region of 20 ⁇ m to 30 ⁇ m thick.
  • the method uses a low-temperature thermal oxidation method to form a gate oxide layer, and the grown thin gate oxide layer has low interface state density, high breakdown voltage, low charge density, less pinholes, less defects, uniform thickness, etc. Features. Therefore, it is possible to produce an IGBT having high breakdown voltage, low leakage current, positive temperature coefficient of conduction voltage drop, low switching loss, and high process reliability.
  • a layer of a medium such as silicon dioxide, is deposited on the front and back sides of the silicon wafer to protect both sides of the silicon wafer.
  • the protective layer can effectively prevent the silicon surface from being scratched in subsequent processes.
  • the material of the protective layer is SiN or SiO 2 /SiN composite layer, and the thickness can be determined according to actual conditions, generally 500 ⁇ to 1200 ⁇ , and SiO 2 in the protective layer can be formed by conventional thermal oxidation method, and low pressure chemical vapor deposition method is adopted. (LPCVD) Formation of SiN in the protective layer. Then, the fabrication of the FS-IGBT device is carried out in accordance with the method of the first embodiment of the present invention.
  • This method makes FS on the back of the silicon wafer.
  • a protective layer is formed on the front side of the silicon wafer and the back side of the silicon wafer to ensure that the front and back sides of the silicon wafer are not scratched by the manufacturing process.
  • start MOSFET Before the fabrication, the protective layer on the front side of the silicon wafer is removed, and the back protective layer needs to be removed until the last back metal deposition to protect the back PN junction from being scratched.

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Abstract

一种绝缘栅双极型晶体管的制造方法，包括：提供第一导电类型的半导体衬底，该半导体衬底具有第一主面和第二主面；在所述半导体衬底的第二主面形成第一导电类型的场终止层；在所述半导体衬底的第一主面有选择的形成第二导电类型的基区；在形成有所述基区的所述半导体衬底的第一主面继续形成所述绝缘栅双极型晶体管的第一主面结构；和在形成有所述场终止层的所述半导体衬底的第二主面继续形成所述绝缘栅双极型晶体管的剩余第二主面结构。本方法可以制作出具有高击穿电压、低漏电、导通压降正温度系数、低开关损耗且工序简单产品可靠性高的IGBT。

Description

绝缘栅双极型晶体管的制造方法
【技术领域】
本发明属于功率半导体器件技术领域，涉及绝缘栅双极型晶体管（ IGBT ），尤其是场终止型绝缘栅双极型晶体管（ FS-IGBT ）的制备方法。
【背景技术】
IGBT（Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管）是在VDMOS（Vertical Double-diffused MOSFET，垂直双扩散场效应晶体管）的基础上改进成的新器件，IGBT 的纵向结构己从最初的PT 型（Punch Through，穿通型）单一结构发展到了现在成熟的NPT 型（Non-Punch Through，非穿通型）、FS 型（Field-Stop，场终止型），在沟道结构上主要有Planer（平面型）和Trench（沟槽型）。
FS-IGBT（场截止型绝缘栅双极型晶体管）同时具有PT-IGBT（穿通型绝缘栅双极型晶体管）和NPT-IGBT（非穿通型绝缘栅双极型晶体管）的优点。FS-IGBT 利用N 型场截止层使得电场分布由NPT 型的三角形分布转为了类梯形分布，缩短了器件的厚度，大幅降低了器件的导通压降和损耗。但这给工艺增加了难度，目前通常采用先做正面工艺，背部薄片后背注的方式来引入FS 层，由于要保护正面金属图形，退火温度不能过高，此时杂质激活率很低，影响器件性能。目前各大公司Planar FS-IGBT（平面场截止型绝缘栅双极型晶体管）的制作工艺大致分为二种：一是通过外延实现，但外延工艺时间较长，影响生产产能，外延成本较高且产品可靠性低；二是通过购买双面扩散晶圆，但是，此晶圆成本较高，增加了产品成本。
传统的FS-IGBT工艺流程如图12，N+缓冲层弥补了NPT-IGBT具有较厚耐压层N-区的不足之处。PT 结构中，N-基区与P+发射区之间有一个N+区缓冲层，该层的N型掺杂浓度较N-基区高得多，其间的电场呈直角梯形分布，基区厚度较薄，但其电阻温度系数不理想，不利于多芯片并联的自均流效应的实现。FS 型结构中的缓冲层掺杂浓度比PT 型结构缓冲层N+浓度低，但比基区N-浓度高，于是电场在其间的分布呈斜角梯形分布，基区可以明显减薄，却还能保留正电阻温度系数的特征。当然，这样的制作难度增大了。因为FS-IGBT 的缓冲层是靠离子注入，然后退火形成的，在这之前表面的金属-氧化物-半导体场效应晶体管（metal-oxide-semiconductor field effect transistor，简称“MOSFET”）结构都已做完，如果离子注入后退火时间过长，温度过高，势必会导致表面MOSFET 结构中各p-n结结深发生变化，且已做成的表面MOSFET 结构的铝层限制了退火温度必须控制在500°C以下。所以，考虑到这点，FS-IGBT的N+缓冲层一般只能作到1μm 左右。但用如此薄的缓冲层做强电场中止层是很不安全的，所以制作时候对工艺要求较高。
【发明内容】
基于此，有必要提出一种能够制作出具有高击穿电压、低漏电、导通压降正温度系数、低开关损耗且工序简单产品可靠性高的IGBT制造方法。
一种绝缘栅双极型晶体管的制造方法，包括，提供第一导电类型的半导体衬底，该半导体衬底具有第一主面和第二主面；在所述半导体衬底的第二主面形成第一导电类型的场终止层；在所述半导体衬底的第一主面有选择的形成第二导电类型的基区；在形成有所述基区的所述半导体衬底的第一主面继续形成所述绝缘栅双极型晶体管的第一主面结构；和在形成有所述场终止层的所述半导体衬底的第二主面继续形成所述绝缘栅双极型晶体管的剩余第二主面结构。
在其中的一个实施例中，所述在形成有所述基区的所述半导体衬底的第一主面继续形成所述绝缘栅双极型晶体管的第一主面结构包括：在形成有所述基区的所述半导体衬底的第一主面上形成栅氧化层；在所述栅氧化层上积淀形成多晶硅层；有选择的在所述栅氧层和所述多晶硅层上经过光刻、刻蚀工艺制得有源区注入窗口，自所述有源区注入窗口向所述基区注入第一导电类型的杂质以形成有源区；在刻蚀有注入窗口的多晶硅层上形成介质层；在所述介质层上有选择的光刻、刻蚀出与所述有源区和所述基区相通的接触孔；在所述介质层上形成金属层以形成所述绝缘栅双极型晶体管的第一电极。
在其中的一个实施例中，所述在形成有所述场终止层的所述半导体衬底的第二主面继续形成所述绝缘栅双极型晶体管的剩余第二主面结构包括：自所述半导体衬底的第二主面向所述场终止层注入第二导电类型的杂质以形成注入区；在所述注入区上形成金属层以形成所述绝缘栅双极型晶体管的第二电极。
在其中的一个实施例中，第一导电类型为N型，第二导电类型为P型，所述有源区为N+有源区，所述注入区为P+集电极区，第一电极为发射极，第二电极为集电极。
在其中的一个实施例中，通过离子注入、高温推阱、激活工艺在所述半导体衬底的第二主面形成第一导电类型的场终止层。
在其中的一个实施例中，通过离子注入、高温推阱、激活工艺在所述半导体衬底的第一主面有选择的形成第二导电类型的基区。
在其中的一个实施例中，采用热氧化法形成所述栅氧化层。
在其中的一个实施例中，所述采用热氧化法形成所述栅氧化层的步骤包括：
在800℃~850℃时将硅片干氧5min；
根据需要的氧化层厚度进行H2-O2 合成氧化；
在800℃~850℃干氧氧化3min~5min；
在860℃~875℃时N2气氛中退火20min~30min。
在其中的一个实施例中，形成第一导电类型的场终止层时的离子注入的剂量为1E12/cm2～1E14/cm2。
在其中的一个实施例中，所述场终止层的厚度为15μm～30μm。
上述绝缘栅双极型晶体管的制造方法将背面的FS区和正面的第二类型阱区提前至栅氧化层形成之前。由于先形成较厚的FS，不影响之后制作的硅片正面MOSFET等器件特性。而硅片正面器件制作的高温过程对20μm～30μm厚的FS区影响很小。在栅氧化层形成之前，形成第二类型阱区，简化了后续工序且不易引起闩锁效应，提高了产品的可靠性；同时，背面离子注入集电区所需第二类型杂质，背面集电区第二类型杂质激活是靠退火的热过程激活，激活率高，也可消除离子注入产生的损伤；而且，该方法形成栅氧化层时采用低温热氧化方法，生长成的薄栅氧化层具有界面态密度低、击穿电压高、电荷密度低、针孔少、缺陷少、厚度均匀等特点。因此，可以制作出具有高击穿电压、低漏电、导通压降正温度系数、低开关损耗且工序简单产品可靠性高的绝缘栅双极型晶体管。
进一步地，上述方法采用二氧化硅覆盖硅片背面的第二类型重掺杂集电区，在保护的同时，利用第二类型杂质易于集中在硅-二氧化硅界面的特性，可以让第二类型重掺杂集电区中的第二类型杂质分布优化——与背面金属接触的界面具有高掺杂浓度，与第一类型硅接触的界面具有低掺杂浓度。一方面易于与背面金属形成好的欧姆接触，另一方面有利于控制PNP 的发射效率并改善IGBT器件的交流特性。
【附图说明】
图1是根据一实施方式制作FS-IGBT的方法流程图；
图2是根据一实施方式中的在硅片背面制作FS区的示意图；
图3~图4是根据一实施方式中的形成P阱区的过程示意图；
图5~图6是根据一实施方式中的形成栅氧化层和多晶硅层的过程示意图；
图7是根据一实施方式中的形成多晶硅栅极以及第一源区和第二源区的示意图；
图8是根据一实施方式中的形成介质层和金属层的示意图；
图9是根据一实施方式中的形成金属布线层的示意图；
图10是根据一实施方式中的形成集电区的示意图；
图11是根据一实施方式中的形成背面金属层的示意图；
图12是现有技术制造FS-IGBT的示意图。
【具体实施方式】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
正如背景技术部分所述，现有技术的FS-IGBT以低掺杂n 型单晶片为起始材料, 先在正面制MOS结构, 然后将硅片从背面减薄到耐压所需的厚度,再从背面进行离子注入得到n 型场终止层(相当于PT-IGBT的n型缓冲层)与p型集电区。由于集电区薄且轻掺杂,集电结的注入效率很低, 器件关断时,通过集电结的电流以电子流为主,电导调制区中积累的大量电子可以顺畅的通过集电区流到集电极。形象地说,集电区对电子是“透明”的。这使得FS-IGBT在具有较低通态电压的同时,能获得较快的开关时间,并且能保持由迁移率决定的通态电压正温度系数。但目前FS-IGBT的制作工艺流程复杂滞后，生产成本高，且没有解决由于背面减薄工艺所带来的产品可靠性低的问题。为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施方式作进一步地详细描述。
本发明第一实施方式以硅片为半导体衬底，涉及一种制作FS-IGBT器件的方法，具体流程如图1 所示。
需要说明的是，本实施例中的半导体衬底可以包括半导体元素，例如单晶、多晶或非晶结构的硅或硅锗(SiGe)，也可以包括混合的半导体结构，例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合；也可以是绝缘体上硅(SOI)。此外，半导体衬底还可以包括其它的材料，例如外延层或掩埋层的多层结构。虽然在此描述了可以形成半导体衬底的材料的几个示例，但是可以作为半导体衬底的任何材料均落入本发明的精神和范围。
在介绍本发明中的IGBT的制造方法之前，需要进行如下说明。本文中涉及到两种导电类型，分别为第一导电类型和第二导电类型。在第一导电类型为P型时，第二导电类型为N型；在第一导电类型为N型时，第二导电类型为P型。这不能被理解为一种限制。IGBT的发射极和栅极所在的面通常被理解为第一主面，而IGBT的集电极所在的面通常被理解第二主面。
在步骤100中，其实是在硅片背面制作FS区。在本实施方式中，通过硅片背面N 型离子注入和高温推阱形成FS区。
具体地说，首先选N- 型硅片，N- 掺杂浓度和厚度根据所需要的IGBT 特性选择，例如击穿电压越高，N- 的掺杂浓度要求越低，厚度要求越厚。在硅片背面注入N型离子，例如磷、砷、锑、硫或硒，剂量为1E12/cm2～1E14/cm2，并在高温下推阱。调节温度和时间，使N型杂质扩散到所需厚度，即形成FS区101，如图2所示，同时也完成杂质激活。例如，选择退火温度为1150℃～1250℃，时间10小时～20小时，可形成15μm～30μm的FS区101。FS区101中N型杂质离硅片背表面越远FS区101的杂质浓度越淡，这样的分布有利于降低关断损耗。
步骤200中，参见图3和图4，先采用光刻工艺形成第一P阱区201和第二P阱区202的光刻胶图案，之后以该光刻胶图案为掩膜采用离子注入的方式形成第一P阱区的离子注入层203，以及第二P阱区的离子注入层204；之后参见图4，去除光刻胶层，采用热退火工艺，对第一P阱区的离子注入层203以及第二P阱区的离子注入层204进行推阱并激活注入的P 型杂质，形成第一P阱区201和第二P阱区202，该步骤的热退火工艺也可采用快速热退火工艺。
步骤300中，在硅片之上通过热氧化生长工艺形成一层栅氧化层301，如图5所示，在栅氧化层301之上淀积一层多晶硅层302用以制造栅极。
参见图5，在硅片的表面上形成栅氧化层301，本实施例中的栅氧化层301至少包括氧化硅，形成栅氧化层301的方式可以为，在硅片的表面上一次性生长栅氧化层310，在本实施例中，采用相对于传统高温工艺较低温度的热氧化法形成栅氧化层301，具体为，首先在800℃~850℃时干氧5min,之后根据需要的氧化层厚度进行H2-O2 合成氧化,再在800℃~850℃干氧氧化3min~5min, 最后在860℃~875℃时N2气氛中退火20min~30min；这样是因为持续的高温过程会大大增加栅及埋SiO2层的界面电荷以及硅的晶格缺陷密度,导致高的器件泄漏电流,使器件的可靠性及抗辐照能力下降,而低温热氧化则能抑制堆垛层错等缺陷的生长和沟道区杂质的分凝。
如图6所示，在栅氧化层301上淀积多晶硅层302，采用光刻工艺在该栅多晶硅层表面上形成具有栅区图案的光刻胶层，之后以具有栅区图案的光刻胶层为掩膜，采用干法刻蚀的方式形成多晶硅栅极401（参见图7），其中多晶硅层302可采用化学气相淀积、物理气相淀积或其它方式形成，本实施例不做具体限定。
在步骤400中，如图7所示，采用光刻和刻蚀工艺形成多晶硅栅极401，采用离子注入和退火工艺在多晶硅栅极401两侧下方的第一P阱区201和第二P阱区202中分别形成N型重掺杂第一源区402和第二源区403。
参见图8，在本实施例中，介质在所述步骤500中淀积形成介质层501包围多晶硅栅极401（参见图7）的侧面和顶面，在介质层501中刻蚀接触孔，采用淀积金属和平坦化工艺(例如钨塞工艺)，在硅片表面淀积一层表面金属层502，然后对金属层502进行光刻与刻蚀，形成金属布线层503。这些步骤都完成后的硅片剖面如图9 所示。
步骤600，请参阅图10，对N型重掺杂场FS区101的背面进行P型杂质的离子注入，形成P型重掺杂集电区601。离子注入的P型杂质例如为硼(B)、二氟化硼(BF2)等含有硼元素的杂质。离子注入的能量例如为20KeV～80KeV，剂量例如为 1E13/cm2 ～1E15/cm2。 退火激活时，退火温度选在350℃～550℃之间，退火时间20min-200min，以保证较大激活率前提下背面集电区601扩散较慢，对集电区601和FS区101形成的PN 结深影响较小。
最后，步骤700，除去硅片背面的残留层，形成背面金属层701，参见图11，具体的说，在硅片正面甩胶烘干，用常规干法或湿法除去残留层（图中未标示出），常规干法去胶，形成背面金属层701。
不难发现，在本实施方式中，背面的FS区和正面的P阱区不是在完成IGBT 的MOSFET制作和背面研磨后进行，而是提前至栅氧化层形成之前。在制作MOSFET之前，先在硅片背面制作场终止FS区，形成所需厚度的FS后再做正面MOSFET等器件。由于先形成较厚的FS，不影响之后制作的硅片正面MOSFET等器件特性。而硅片正面器件制作的高温过程对20μm～30μm厚的FS区影响很小。在栅氧化层形成之前，形成P阱区，简化了后续工序且不易引起闩锁效应，提高了产品的可靠性；同时，背面离子注入集电区所需P 型杂质；而且，该方法形成栅氧化层时采用低温热氧化方法，生长成的薄栅氧化层具有界面态密度低、击穿电压高、电荷密度低、针孔少、缺陷少、厚度均匀等特点。因此，可以制作出具有高击穿电压、低漏电、导通压降正温度系数、低开关损耗且工序简单产品可靠性高的IGBT。
本发明第二实施方式，是先在硅片的正面和背面淀积一层介质，例如二氧化硅，用于保护硅片的两个面，保护层可以有效避免后续工序造成硅表面划伤。其中，保护层的材料为SiN或 SiO2/SiN 复合层，厚度可根据实际状况确定，一般为500Å～1200Å，可采用常规热氧化法形成保护层中的SiO2，采用低压化学气相淀积法(LPCVD) 形成保护层中的SiN。 而后，再按照本发明第一实施例的方法进行FS-IGBT器件的制作。
该方法在硅片背面制作FS 区之前，先在硅片正面和硅片背面形成保护层，以保证硅片正面和背面不会被制作过程划伤。开始进行MOSFET 的制作之前，除去硅片正面的保护层，而背面保护层需一直保留到最后背面金属淀积前去除，以保护背面PN 结不会被划伤。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种绝缘栅双极型晶体管的制造方法，其特征在于，包括：
    提供第一导电类型的半导体衬底，该半导体衬底具有第一主面和第二主面；
    在所述半导体衬底的第二主面形成第一导电类型的场终止层；
    在所述半导体衬底的第一主面有选择的形成第二导电类型的基区；
    在形成有所述基区的所述半导体衬底的第一主面继续形成所述绝缘栅双极型晶体管的第一主面结构；及
    在形成有所述场终止层的所述半导体衬底的第二主面继续形成所述绝缘栅双极型晶体管的剩余第二主面结构。
  2. 根据权利要求1所述的绝缘栅双极型晶体管的制造方法，其特征在于，所述在形成有所述基区的所述半导体衬底的第一主面继续形成所述绝缘栅双极型晶体管的第一主面结构的步骤包括：
    在形成有所述基区的所述半导体衬底的第一主面上形成栅氧化层；
    在所述栅氧化层上积淀形成多晶硅层；
    有选择的在所述栅氧化层和所述多晶硅层上经过光刻、刻蚀工艺制得有源区注入窗口，自所述有源区注入窗口向所述基区注入第一导电类型的杂质以形成有源区；
    在刻蚀有注入窗口的多晶硅层上形成介质层；
    在所述介质层上有选择的光刻、刻蚀出与所述有源区和所述基区相通的接触孔；
    在所述介质层上形成金属层以形成所述绝缘栅双极型晶体管的第一电极。
  3. 根据权利要求1所述的绝缘栅双极型晶体管的制造方法，其特征在于，
    所述在形成有所述场终止层的所述半导体衬底的第二主面继续形成所述绝缘栅双极型晶体管的剩余第二主面结构的步骤包括：
    自所述半导体衬底的第二主面向所述场终止层注入第二导电类型的杂质以形成注入区；
    在所述注入区上形成金属层以形成所述绝缘栅双极型晶体管的第二电极。
  4. 根据权利要求1所述的绝缘栅双极型晶体管的制造方法，其特征在于，
    第一导电类型为N型，第二导电类型为P型，
    所述有源区为N+有源区，所述注入区为P+集电极区，第一电极为发射极，第二电极为集电极。
  5. 根据权利要求1所述的绝缘栅双极型晶体管的制造方法，其特征在于，通过离子注入、高温推阱、激活工艺在所述半导体衬底的第二主面形成第一导电类型的场终止层。
  6. 根据权利要求1所述的绝缘栅双极型晶体管的制造方法，其特征在于，通过离子注入、高温推阱、激活工艺在所述半导体衬底的第一主面有选择的形成第二导电类型的基区。
  7. 根据权利要求2所述的绝缘栅双极型晶体管的制造方法，其特征在于，采用热氧化法形成所述栅氧化层。
  8. 根据权利要求7所述的绝缘栅双极型晶体管的制造方法，其特征在于，所述采用热氧化法形成所述栅氧化层的步骤包括：
    在800℃~850℃时将硅片干氧5min；
    根据需要的氧化层厚度进行H2-O2 合成氧化；
    在800℃~850℃干氧氧化3min~5min；
    在860℃~875℃时N2气氛中退火20min~30min。
  9. 根据权利要求5所述的绝缘栅双极型晶体管的制造方法，其特征在于，所述离子注入的剂量为1E12/cm2～1E14/cm2。
  10. 根据权利要求5所述的绝缘栅双极型晶体管的制造方法，其特征在于，所述场终止层的厚度为15μm～30μm。
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