WO2014192210A1 - 薄膜トランジスタ装置とその製造方法、および表示装置 - Google Patents
薄膜トランジスタ装置とその製造方法、および表示装置 Download PDFInfo
- Publication number
- WO2014192210A1 WO2014192210A1 PCT/JP2014/001929 JP2014001929W WO2014192210A1 WO 2014192210 A1 WO2014192210 A1 WO 2014192210A1 JP 2014001929 W JP2014001929 W JP 2014001929W WO 2014192210 A1 WO2014192210 A1 WO 2014192210A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- channel
- forming
- thin film
- film transistor
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 68
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 239000010409 thin film Substances 0.000 title claims description 29
- 238000002161 passivation Methods 0.000 claims abstract description 116
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 83
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 83
- 239000000470 constituent Substances 0.000 claims abstract description 60
- 239000000463 material Substances 0.000 claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 739
- 239000011241 protective layer Substances 0.000 claims description 86
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 81
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 80
- -1 aluminum compound Chemical class 0.000 claims description 67
- 239000010408 film Substances 0.000 claims description 58
- 229910052739 hydrogen Inorganic materials 0.000 claims description 51
- 239000001257 hydrogen Substances 0.000 claims description 51
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 50
- 230000015572 biosynthetic process Effects 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 34
- 238000003795 desorption Methods 0.000 claims description 33
- 229910052782 aluminium Inorganic materials 0.000 claims description 28
- 238000004458 analytical method Methods 0.000 claims description 23
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 23
- 239000007789 gas Substances 0.000 claims description 21
- 238000000137 annealing Methods 0.000 claims description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 239000012298 atmosphere Substances 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 description 49
- 239000011229 interlayer Substances 0.000 description 22
- 238000005401 electroluminescence Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 16
- 238000002347 injection Methods 0.000 description 15
- 239000007924 injection Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 239000010949 copper Substances 0.000 description 14
- 230000006866 deterioration Effects 0.000 description 14
- 238000005530 etching Methods 0.000 description 13
- 238000004544 sputter deposition Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 11
- 150000001875 compounds Chemical class 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- 239000011347 resin Substances 0.000 description 10
- 238000007789 sealing Methods 0.000 description 10
- 230000005525 hole transport Effects 0.000 description 9
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000005259 measurement Methods 0.000 description 8
- 239000011368 organic material Substances 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- 229920001940 conductive polymer Polymers 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 7
- 230000036961 partial effect Effects 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- 230000002829 reductive effect Effects 0.000 description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 229920000178 Acrylic resin Polymers 0.000 description 5
- 239000004925 Acrylic resin Substances 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 230000001629 suppression Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 229920001577 copolymer Polymers 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229920000098 polyolefin Polymers 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 229910010272 inorganic material Inorganic materials 0.000 description 3
- 239000011147 inorganic material Substances 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000005011 phenolic resin Substances 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 2
- 239000004721 Polyphenylene oxide Substances 0.000 description 2
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 2
- 150000004696 coordination complex Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 2
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000005038 ethylene vinyl acetate Substances 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- GVEPBJHOBDJJJI-UHFFFAOYSA-N fluoranthrene Natural products C1=CC(C2=CC=CC=C22)=C3C2=CC=CC3=C1 GVEPBJHOBDJJJI-UHFFFAOYSA-N 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910001195 gallium oxide Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000002905 metal composite material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 2
- 229920003986 novolac Polymers 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920001200 poly(ethylene-vinyl acetate) Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920000728 polyester Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 229920006380 polyphenylene oxide Polymers 0.000 description 2
- 229920000123 polythiophene Polymers 0.000 description 2
- 229920002635 polyurethane Polymers 0.000 description 2
- 239000004814 polyurethane Substances 0.000 description 2
- 229920000915 polyvinyl chloride Polymers 0.000 description 2
- 239000004800 polyvinyl chloride Substances 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910001930 tungsten oxide Inorganic materials 0.000 description 2
- QGKMIGUHVLGJBR-UHFFFAOYSA-M (4z)-1-(3-methylbutyl)-4-[[1-(3-methylbutyl)quinolin-1-ium-4-yl]methylidene]quinoline;iodide Chemical class [I-].C12=CC=CC=C2N(CCC(C)C)C=CC1=CC1=CC=[N+](CCC(C)C)C2=CC=CC=C12 QGKMIGUHVLGJBR-UHFFFAOYSA-M 0.000 description 1
- NSMJMUQZRGZMQC-UHFFFAOYSA-N 2-naphthalen-1-yl-1H-imidazo[4,5-f][1,10]phenanthroline Chemical compound C12=CC=CN=C2C2=NC=CC=C2C2=C1NC(C=1C3=CC=CC=C3C=CC=1)=N2 NSMJMUQZRGZMQC-UHFFFAOYSA-N 0.000 description 1
- 150000004325 8-hydroxyquinolines Chemical class 0.000 description 1
- 101100016388 Arabidopsis thaliana PAS2 gene Proteins 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- LSNNMFCWUKXFEE-UHFFFAOYSA-M Bisulfite Chemical compound OS([O-])=O LSNNMFCWUKXFEE-UHFFFAOYSA-M 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004709 Chlorinated polyethylene Substances 0.000 description 1
- WDECIBYCCFPHNR-UHFFFAOYSA-N Chrysene Natural products C1=CC=CC2=CC=C3C4=CC=CC=C4C=CC3=C21 WDECIBYCCFPHNR-UHFFFAOYSA-N 0.000 description 1
- 101100060179 Drosophila melanogaster Clk gene Proteins 0.000 description 1
- 229920000219 Ethylene vinyl alcohol Polymers 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 101100297150 Komagataella pastoris PEX3 gene Proteins 0.000 description 1
- 239000002841 Lewis acid Substances 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 239000004640 Melamine resin Substances 0.000 description 1
- 229920000877 Melamine resin Polymers 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 101150038023 PEX1 gene Proteins 0.000 description 1
- 239000002033 PVDF binder Substances 0.000 description 1
- YNPNZTXNASCQKK-UHFFFAOYSA-N Phenanthrene Natural products C1=CC=C2C3=CC=CC=C3C=CC2=C1 YNPNZTXNASCQKK-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 208000000474 Poliomyelitis Diseases 0.000 description 1
- 229920012266 Poly(ether sulfone) PES Polymers 0.000 description 1
- 229930182556 Polyacetal Natural products 0.000 description 1
- 239000004962 Polyamide-imide Substances 0.000 description 1
- 239000004697 Polyetherimide Substances 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- 229920001328 Polyvinylidene chloride Polymers 0.000 description 1
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 1
- 101100315760 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) PEX4 gene Proteins 0.000 description 1
- PJANXHGTPQOBST-VAWYXSNFSA-N Stilbene Natural products C=1C=CC=CC=1/C=C/C1=CC=CC=C1 PJANXHGTPQOBST-VAWYXSNFSA-N 0.000 description 1
- XBDYBAVJXHJMNQ-UHFFFAOYSA-N Tetrahydroanthracene Natural products C1=CC=C2C=C(CCCC3)C3=CC2=C1 XBDYBAVJXHJMNQ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229920001807 Urea-formaldehyde Polymers 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 125000000641 acridinyl group Chemical class C1(=CC=CC2=NC3=CC=CC=C3C=C12)* 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- MWPLVEDNUUSJAV-UHFFFAOYSA-N anthracene Natural products C1=CC=CC2=CC3=CC=CC=C3C=C21 MWPLVEDNUUSJAV-UHFFFAOYSA-N 0.000 description 1
- 150000001454 anthracenes Chemical class 0.000 description 1
- BBEAQIROQSPTKN-UHFFFAOYSA-N antipyrene Natural products C1=CC=C2C=CC3=CC=CC4=CC=C1C2=C43 BBEAQIROQSPTKN-UHFFFAOYSA-N 0.000 description 1
- YBGKQGSCGDNZIB-UHFFFAOYSA-N arsenic pentafluoride Chemical compound F[As](F)(F)(F)F YBGKQGSCGDNZIB-UHFFFAOYSA-N 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- BCZWPKDRLPGFFZ-UHFFFAOYSA-N azanylidynecerium Chemical compound [Ce]#N BCZWPKDRLPGFFZ-UHFFFAOYSA-N 0.000 description 1
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- ZYGHJZDHTFUPRJ-UHFFFAOYSA-N benzo-alpha-pyrone Natural products C1=CC=C2OC(=O)C=CC2=C1 ZYGHJZDHTFUPRJ-UHFFFAOYSA-N 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000006229 carbon black Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910000428 cobalt oxide Inorganic materials 0.000 description 1
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(ii) oxide Chemical compound [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- HPDFFVBPXCTEDN-UHFFFAOYSA-N copper manganese Chemical compound [Mn].[Cu] HPDFFVBPXCTEDN-UHFFFAOYSA-N 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 229960000956 coumarin Drugs 0.000 description 1
- 235000001671 coumarin Nutrition 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000000295 emission spectrum Methods 0.000 description 1
- ZSWFCLXCOIISFI-UHFFFAOYSA-N endo-cyclopentadiene Natural products C1C=CC=C1 ZSWFCLXCOIISFI-UHFFFAOYSA-N 0.000 description 1
- UFRKOOWSQGXVKV-UHFFFAOYSA-N ethene;ethenol Chemical compound C=C.OC=C UFRKOOWSQGXVKV-UHFFFAOYSA-N 0.000 description 1
- 239000004715 ethylene vinyl alcohol Substances 0.000 description 1
- 230000005281 excited state Effects 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 229920001973 fluoroelastomer Polymers 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- VPUGDVKSAQVFFS-UHFFFAOYSA-N hexabenzobenzene Natural products C1=C(C2=C34)C=CC3=CC=C(C=C3)C4=C4C3=CC=C(C=C3)C4=C2C3=C1 VPUGDVKSAQVFFS-UHFFFAOYSA-N 0.000 description 1
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 1
- 229920000554 ionomer Polymers 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 150000007517 lewis acids Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 description 1
- UFWIBTONFRDIAS-UHFFFAOYSA-N naphthalene-acid Natural products C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- NIHNNTQXNPWCJQ-UHFFFAOYSA-N o-biphenylenemethane Natural products C1=CC=C2CC3=CC=CC=C3C2=C1 NIHNNTQXNPWCJQ-UHFFFAOYSA-N 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 150000004866 oxadiazoles Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 101150014555 pas-1 gene Proteins 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- CSHWQDPOILHKBI-UHFFFAOYSA-N peryrene Natural products C1=CC(C2=CC=CC=3C2=C2C=CC=3)=C3C2=CC=CC3=C1 CSHWQDPOILHKBI-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001643 poly(ether ketone) Polymers 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 229920000172 poly(styrenesulfonic acid) Polymers 0.000 description 1
- 229920001197 polyacetylene Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 229920002312 polyamide-imide Polymers 0.000 description 1
- 229920000767 polyaniline Polymers 0.000 description 1
- 229920001230 polyarylate Polymers 0.000 description 1
- 229920001707 polybutylene terephthalate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229920000570 polyether Polymers 0.000 description 1
- 229920001601 polyetherimide Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920002098 polyfluorene Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920002959 polymer blend Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 229920006324 polyoxymethylene Polymers 0.000 description 1
- 229920000128 polypyrrole Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 229940005642 polystyrene sulfonic acid Drugs 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 239000005033 polyvinylidene chloride Substances 0.000 description 1
- 229920002981 polyvinylidene fluoride Polymers 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- JEXVQSWXXUJEMA-UHFFFAOYSA-N pyrazol-3-one Chemical class O=C1C=CN=N1 JEXVQSWXXUJEMA-UHFFFAOYSA-N 0.000 description 1
- 150000003219 pyrazolines Chemical class 0.000 description 1
- RQGPLDBZHMVWCH-UHFFFAOYSA-N pyrrolo[3,2-b]pyrrole Chemical compound C1=NC2=CC=NC2=C1 RQGPLDBZHMVWCH-UHFFFAOYSA-N 0.000 description 1
- WVIICGIFSIBFOG-UHFFFAOYSA-N pyrylium Chemical class C1=CC=[O+]C=C1 WVIICGIFSIBFOG-UHFFFAOYSA-N 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 235000021286 stilbenes Nutrition 0.000 description 1
- 239000012756 surface treatment agent Substances 0.000 description 1
- 239000002352 surface water Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- KKEYFWRCBNTPAC-UHFFFAOYSA-L terephthalate(2-) Chemical compound [O-]C(=O)C1=CC=C(C([O-])=O)C=C1 KKEYFWRCBNTPAC-UHFFFAOYSA-L 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229920002725 thermoplastic elastomer Polymers 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 150000005075 thioxanthenes Chemical class 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 150000003852 triazoles Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229920006305 unsaturated polyester Polymers 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
- KAKZBPTYRLMSJV-UHFFFAOYSA-N vinyl-ethylene Natural products C=CC=C KAKZBPTYRLMSJV-UHFFFAOYSA-N 0.000 description 1
- AKJVMGQSGCSQBU-UHFFFAOYSA-N zinc azanidylidenezinc Chemical compound [Zn++].[N-]=[Zn].[N-]=[Zn] AKJVMGQSGCSQBU-UHFFFAOYSA-N 0.000 description 1
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Definitions
- the present invention relates to a thin film transistor device, a method for manufacturing the same, and a display device, and more particularly to film quality such as a channel protective layer and a passivation layer in the thin film transistor device.
- the active matrix display device includes a TFT device having a thin film transistor (TFT) for driving light emission in units of sub-pixels.
- TFT thin film transistor
- a TFT device including a channel layer made of an oxide semiconductor material has been developed for use in a display device or the like (Patent Document 1).
- Patent Document 1 A TFT device including a channel layer made of such an oxide semiconductor material will be described with reference to FIG.
- a TFT device includes a gate electrode 1901, a gate insulating film 1903, a channel layer 1904, a protective film 1912, a drain electrode 1907, and a source electrode 1908 on a substrate 1900. It is comprised.
- the channel layer 1904 is an oxide semiconductor layer containing at least one of In, Zn, and Sn.
- the protective film 1912 is made of an amorphous oxide semiconductor material (amorphous SiO) and is formed in contact with the channel layer 1904. In this TFT device, it is specified that the protective film 1912 contains 3.8E19 cm ⁇ 3 or more of the desorbed gas observed as oxygen by the temperature programmed desorption analysis.
- amorphous oxide semiconductor material amorphous SiO
- the present invention has been made to solve such a problem, and includes a channel layer made of an oxide semiconductor material, and can be further stabilized and improved in reliability, and a manufacturing method thereof.
- An object is to provide a display device.
- a TFT device includes: (i) a substrate; (ii) a gate electrode; (iii) a source electrode and a drain electrode; (iv) a channel layer; (v) a channel protective layer; vi) a passivation layer.
- the gate electrode is formed above the substrate.
- the source electrode and the drain electrode are provided above the substrate, spaced from the gate electrode, and spaced from each other.
- the channel layer is inserted between the gate electrode, the source electrode, and the drain electrode, and each part of the source electrode and the drain electrode is in contact.
- the channel protective layer is inserted between the channel layer and the source and drain electrodes, except for a portion where each part of the source electrode and the drain electrode is in contact with the channel layer.
- the passivation layer is provided so as to cover the gate electrode, the source electrode, the drain electrode, the channel layer, and the channel protective layer.
- the channel layer is made of an oxide semiconductor material
- at least one of the channel protective layer and the passivation layer is made of silicon nitride or silicon oxynitride, and has a Si—H concentration of 2.3E21 cm ⁇ 3 or less. Including layers.
- the TFT device according to the above aspect it is possible to suppress the influence of hydrogen active species generated during the process and after the layer formation. Therefore, the TFT device according to the above aspect is stable and has excellent reliability.
- FIG. 3 is a schematic circuit diagram illustrating a circuit configuration in each sub-pixel 10a of the display panel 10.
- FIG. 3 is a schematic cross-sectional view showing a configuration of each sub-pixel 10a of the display panel 10.
- FIGS. 4A to 4D are schematic cross-sectional views showing states in respective steps in manufacturing the display panel 10.
- FIGS. 4A to 4D are schematic cross-sectional views showing states in respective steps in manufacturing the display panel 10.
- (A), (b) is a schematic cross section which shows the state in each process in manufacture of the display panel 10.
- (A) is a schematic diagram showing the configuration of a resistance evaluation TEG
- (b) is a characteristic diagram showing the relationship between the Si—H concentration in SiN and the TAOS sheet resistance. It is a characteristic view which shows the relationship between TAOS sheet resistance and threshold voltage Vth.
- (A) is a table showing the relationship between SiN film formation conditions and hydrogen concentration
- (b) is a characteristic diagram showing Vg-Id characteristics in sample 1
- (c) is a Vg ⁇ in sample 2. It is a characteristic view which shows Id characteristic.
- (A) is a table
- (b) is a characteristic view which shows the hydrogen emission spectrum of SiO by a temperature-programmed desorption measurement.
- (A) is a characteristic diagram showing the Vg-Id characteristics of samples 11 and 12, and (b) is a characteristic chart showing the Vg-Id characteristics of sample 13.
- (A) is a schematic diagram which shows the structure of the sample for TAOS carrier time measurement
- (b) is a schematic diagram which shows the measuring method of TAOS carrier time.
- (A) is a table
- (b) is a characteristic view which shows the relationship between a film-forming rate and carrier lifetime
- (c) is a refractive index and carrier lifetime. It is a characteristic view which shows a relationship.
- FIG. (A) is a characteristic diagram showing a Vg-Id characteristic in sample 21, (b) is a characteristic chart showing a Vg-Id characteristic in sample 22, and (c) is a Vg-Id characteristic in sample 23.
- FIG. (A) is a characteristic diagram showing the Vg-Id characteristic in the TFT according to the embodiment, and (b) is a characteristic chart showing the Vg-Id characteristic in the TFT according to the comparative example.
- It is a schematic cross section which shows the partial structure of the display panel 30 which concerns on Embodiment 2 of this invention.
- It is a schematic cross section which shows a partial structure of the display panel 40 concerning Embodiment 3 of this invention.
- a TFT device includes: (i) a substrate; (ii) a gate electrode; (iii) a source electrode and a drain electrode; (iv) a channel layer; (v) a channel protective layer; vi) a passivation layer.
- the gate electrode is formed above the substrate.
- the source electrode and the drain electrode are provided above the substrate, spaced from the gate electrode, and spaced from each other.
- the channel layer is inserted between the gate electrode, the source electrode, and the drain electrode, and each part of the source electrode and the drain electrode is in contact.
- the channel protective layer is inserted between the channel layer and the source and drain electrodes, except for a portion where each part of the source electrode and the drain electrode is in contact with the channel layer.
- the passivation layer is provided so as to cover the gate electrode, the source electrode, the drain electrode, the channel layer, and the channel protective layer.
- the channel layer is made of an oxide semiconductor material
- at least one of the channel protective layer and the passivation layer is made of silicon nitride or silicon oxynitride, and has a Si—H concentration of 2.3E21 cm ⁇ 3 or less. Including layers.
- the TFT device in the TFT device according to this aspect, it is possible to suppress the influence of hydrogen active species generated during the process and after the layer formation. Therefore, the TFT device according to the above aspect is stable and has excellent reliability.
- the TFT device since the TFT device according to this aspect includes a channel layer made of an oxide semiconductor material, a large electron mobility can be secured, and good electrical characteristics can be obtained regardless of the temperature.
- the Si—H concentration of the first constituent layer included in at least one of the channel protective layer and the passivation layer is 1.3E21 cm ⁇ 3 or less.
- At least one of the channel protective layer and the passivation layer is made of silicon oxide or silicon oxynitride, and is desorbed at 300 ° C. to 350 ° C. observed as hydrogen by thermal desorption analysis.
- a second constituent layer in which the increase rate of the average increase coefficient of the outgas is not positive is included.
- the TFT device by including silicon oxide or silicon oxynitride satisfying the above-mentioned definition as the second constituent layer, it is stable and has excellent reliability from the viewpoint of carrier lifetime and carrier concentration. .
- the channel protective layer includes the second configuration layer.
- the channel protective layer has a thickness of 50 nm / sec. To 110 nm / sec. These layers are made of silicon oxide and are formed at a rate of 1.45 to 1.461.
- the passivation layer has a stacked configuration including the first layer, the second layer, and the third layer from the substrate side. At least one of the first layer and the third layer of the passivation layer is a first constituent layer made of silicon nitride that satisfies the above-mentioned definition, and the second layer is a layer made of an aluminum compound.
- the TFT device since a layer made of an aluminum compound is adopted as the second layer of the passivation layer, moisture and hydrogen active species can be more reliably invaded into the channel layer made of the oxide semiconductor material. Can be suppressed. For this reason, higher quality can be maintained.
- the second layer of the passivation layer is a layer made of aluminum oxide.
- the passivation layer further includes a fourth layer stacked on the third layer, and the third layer and the fourth layer of the passivation layer are both included. It is made of silicon nitride, and the density of the third layer of silicon nitride is lower than the density of the fourth layer of silicon nitride.
- the density of the silicon nitride of the third layer lower than the density of the silicon nitride of the fourth layer, it becomes easy to taper when opening the contact hole with respect to the passivation layer.
- the first layer of the passivation layer is made of silicon oxide and is in contact with the source electrode and the drain electrode.
- a layer made of silicon oxide as the first layer of the passivation layer, high adhesion to the source electrode and the drain electrode can be secured, and the hydrogen content in the layer is reduced. It is desirable from the viewpoint of being able to.
- a display device includes the TFT device according to each of the above embodiments. Thereby, the said effect can be acquired as it is.
- the manufacturing method of a TFT device includes the following steps (i) to (v).
- a channel layer is formed using an oxide semiconductor material
- the step is made of silicon nitride or silicon oxynitride.
- the manufacturing method of the TFT device according to this aspect is adopted, the influence of the hydrogen active species generated during the process and after the layer formation can be suppressed, and a TFT device having a stable and excellent reliability is manufactured. be able to.
- the channel layer is formed using the oxide semiconductor material in the step (ii)
- a large electron mobility can be ensured, and the temperature can be increased or decreased. Regardless, a TFT device having good electrical characteristics can be manufactured.
- the channel layer is made to have a high resistance state without causing generation of desorbed hydrogen from the first constituent layer by performing annealing treatment at the above temperature condition after the film formation. Can be maintained.
- desorbed hydrogen is generated from the first constituent layer, it causes deterioration of the oxide semiconductor layer which is a channel layer, which causes a reduction in resistance of the channel layer.
- the substrate on which the channel layer is formed is placed under vacuum. Therefore, oxygen in the oxide semiconductor in the channel layer is lost and the resistance is reduced.
- a high resistance state can be maintained by performing an annealing process under the above temperature condition after the first constituent layer is formed.
- At least one of the step (ii) and the step (v) is made of silicon oxide or silicon oxynitride, and hydrogenated by thermal desorption analysis. And a sub-process for forming a second constituent layer in which the increase rate of the average increase coefficient of the desorbed gas at 300 to 350 ° C. is not positive. This makes it possible to suppress active hydrogen species generated during the process or after film formation, and to reduce the threshold shift ( ⁇ Vth) of the TFT in the NBTS (Negative Bias Temperature Stress) test and to have a highly reliable TFT device. Can be manufactured.
- the sub-step of forming the second constituent layer is included in the step (iii) (step of forming a channel protective layer), and the second constituent layer is In the sub-process to be formed, 50 nm / sec. To 110 nm / sec. A layer made of silicon oxide having a refractive index of 1.454 to 1.461 is formed as the second constituent layer. As a result, a TFT device having more stable characteristics can be manufactured.
- the method for manufacturing a TFT device in the sub-process for forming the second constituent layer, after the second constituent layer is formed, in a dry air or oxygen atmosphere at a temperature equal to or higher than the film forming temperature. Annealing treatment is performed. Even in the case of adopting such a method, similarly to the above, when the second constituent layer is formed, it is possible to maintain the high resistance state of the channel layer by performing an annealing process after the film formation under the above conditions. .
- a layer made of silicon oxide is formed as the second constituent layer on the channel protective layer, the source electrode, and the drain electrode.
- a sub-process, a sub-process for forming a layer made of an aluminum compound on the layer made of silicon oxide, and a sub-process for forming a layer made of silicon nitride as a first constituent layer above the layer made of an aluminum compound And a process.
- a TFT device including a passivation layer formed by laminating a second constituent layer made of silicon oxide, a layer made of an aluminum compound, and a first constituent layer made of silicon nitride is manufactured. Can do. For this reason, since the passivation layer includes a layer made of an aluminum compound, entry of moisture and hydrogen can be suppressed (barrier), and the channel layer can be protected.
- the etching selection between the second constituent layer and the aluminum compound layer in the passivation layer and between the aluminum compound layer and the first constituent layer is performed.
- the etching of the underlying film can be started in a state where the ratio is large and the etching of each film is completely completed by applying over-etching. Therefore, by adopting the above method, it is possible to produce with high yield while suppressing deterioration of the channel layer made of an oxide semiconductor.
- dry etching is used for etching the second constituent layer and etching for the first constituent layer, and wet etching is used for etching the layer made of the aluminum compound. desirable.
- a layer made of aluminum oxide is formed as a layer made of the aluminum compound. Accordingly, a passivation layer including a layer made of aluminum oxide can be formed, and entry of moisture and hydrogen active species into the channel layer made of an oxide semiconductor material can be more reliably suppressed. For this reason, higher quality can be maintained.
- the display device 1 includes a display panel 10 and a drive control circuit unit 20 connected thereto.
- the display panel 10 is an organic EL (Electro Luminescence) panel using an electroluminescence phenomenon of an organic material, and a plurality of organic EL elements are arranged in a matrix, for example.
- the drive control circuit unit 20 includes four drive circuits 21 to 24 and a control circuit 25.
- each circuit of the drive control circuit unit 20 with respect to the display panel 10 is not limited to the form shown in FIG. 1.
- each subpixel 10a includes two transistor element portions Tr 1 and Tr 2 , one capacitor C, and an EL element portion EL as a light emitting portion. It is configured. Two transistors element Tr 1, one transistor element Tr 1 of the Tr 2 is a driving transistor element part, the other transistor element Tr 2, a switching transistor element part.
- the gate electrode G 2 of the switching transistor element portion Tr 2 is connected to the scanning line Vscn, and the source electrode S 2 is connected to the data line Vdat.
- the drain electrode D 2 of the switching transistor element Tr 2 is connected to the gate electrode G 1 of the driving transistor element Tr 1.
- the drain electrode D 1 of the driving transistor element portion Tr 1 is connected to the power supply line Va, and the source electrode S 1 is connected to the anode of the EL element portion EL.
- the cathode in the EL element portion EL is connected to the ground line Vcat.
- capacitance C, and the gate electrode G 1 of the drain electrode D 2 and the driving transistor element Tr 1 of the switching transistor element Tr 2 is provided so as to connect the power line Va.
- subpixels 10a having a circuit configuration as shown in FIG. 2 are provided in a matrix, for example, and a plurality of adjacent subpixels 10a (for example, red (R) and green (G) are provided. And three sub-pixels 10a) of blue (B) emission color constitute one pixel.
- the display panel 10 is a top emission type organic EL display panel, in which a TFT device is configured below the Z-axis direction, and an EL element unit is configured thereon.
- TFT device As shown in FIG. 3, gate electrodes 101 and 102 are formed on a substrate 100 at intervals, and gate insulation is performed so as to cover the surfaces of the gate electrodes 101 and 102 and the substrate 100. A layer 103 is formed. On the gate insulating layer 103, channel layers 104 and 105 are formed corresponding to the gate electrodes 101 and 102, respectively. A channel protective layer 106 is formed so as to cover the surfaces of the channel layers 104 and 105 and the gate insulating layer 103.
- a source electrode 107 and a drain electrode 108 are formed on the channel protective layer 106 so as to correspond to the gate electrode 101 and the channel layer 104, and are similarly formed corresponding to the gate electrode 102 and the channel layer 105.
- the source electrode 110 and the drain electrode 109 are formed at a distance from each other.
- the source electrodes 107 and 110 and the drain electrodes 108 and 109 are in contact with the channel layers 104 and 105 in the lower part in the Z-axis direction through the contact holes opened in the channel protective layer 106, respectively.
- the drain electrode 108 and the gate electrode 102 are connected by a contact plug 111 provided through the gate insulating layer 103 and the channel protective layer 106.
- the gate electrode 101 corresponds to the gate electrode G 2 in FIG. 2
- the source electrode 107 corresponds to the source electrode S 2 in FIG. 2
- the drain electrode 108 corresponds to the drain electrode D 2 in FIG.
- the gate electrode 102 corresponds to the gate electrode G 1 in FIG. 2
- the source electrode 110 corresponds to the source electrode S 1 in FIG. 2
- the drain electrode 109 corresponds to the drain electrode D 1 in FIG. Therefore, the switching transistor element portion Tr 2 is formed on the left side in the Y-axis direction in FIG. 3, and the drive transistor element portion Tr 1 is formed on the right side in the Y-axis direction.
- the arrangement of the transistor element portions Tr 1 and Tr 2 is not limited to this.
- a passivation layer 112 is formed so as to cover the source electrodes 107 and 110, the drain electrodes 108 and 109, and the channel protective layer 106.
- a contact hole is formed in a part above the source electrode 110, and an upper electrode 113 is provided along the side wall of the contact hole.
- the passivation layer 112 has a stacked structure in which a lower insulating layer 1121, a barrier layer 1122, and upper insulating layers 1123 and 1124 are stacked in this order from the lower side in the Z-axis direction.
- An interlayer insulating layer 114 is deposited on the passivation layer 112.
- the anode 115 is provided per subpixel.
- the anode 115 is connected to the upper electrode 113 through a contact hole formed above the upper electrode 113 in the interlayer insulating layer 114 and the upper insulating layer 1124.
- the upper electrode 113 is connected to the source electrode 110 at the lower part of the Z axis.
- a hole injection layer 116 is formed, and a bank 117 is formed so as to cover an edge of the hole injection layer 116.
- An opening corresponding to each sub-pixel 10a is formed by surrounding the bank 117.
- a hole transport layer 118 In the opening defined by the bank 117, a hole transport layer 118, a light emitting layer 119, and an electron transport layer 120 are formed in this order from the lower side in the Z-axis direction.
- the hole transport layer 118 is in contact with the hole injection layer 116 at the lower part in the Z-axis direction.
- the cathode 121 and the sealing layer 122 are sequentially stacked so as to cover the electron transport layer 120 and the bank 117.
- the cathode 121 is formed continuously in the entire display panel 10 and connected to the bus bar wiring in pixel units or in units of several pixels (not shown).
- a substrate 126 having a color filter layer 124 and a light shielding layer 125 formed on the main surface on the lower side in the Z-axis direction is disposed above the sealing layer 122 in the Z-axis direction, and is bonded by the bonding layer 123.
- Substrate 100, 130 examples of the constituent material of the substrates 100 and 130 include, for example, a glass substrate, a quartz substrate, a silicon substrate, molybdenum sulfide, copper, zinc, aluminum, stainless steel, magnesium, iron, nickel, gold, silver, and other metal substrates, gallium arsenide.
- a semiconductor substrate such as a base, a plastic substrate, or the like can be employed.
- thermoplastic resin such as polyethylene, polypropylene, ethylene-propylene copolymer, ethylene-vinyl acetate copolymer (EVA), cyclic polyolefin, modified polyolefin, polyvinyl chloride, polyvinylidene chloride, polystyrene, polyamide, polyimide (PI), Polyamideimide, polycarbonate, poly- (4-methylbenten-1), ionomer, acrylic resin, polymethyl methacrylate, acrylic-styrene copolymer (AS resin), butadiene-styrene copolymer, polio copolymer (EVOH) ), Polyesters such as polyethylene terephthalate (PET), polybutylene terephthalate, polyethylene naphthalate (PEN), precyclohexane terephthalate (PCT), polyethers, polyether ketones Polyethers
- Gate electrodes 101 and 102 As the gate electrodes 101 and 102, for example, a stacked body (Cu: 300 [nm] + Mo: 20 [nm]) of copper (Cu) and molybdenum (Mo) is employed. However, the configuration of the gate electrodes 101 and 102 is not limited to this. For example, Cu, Cu / W, or the like can be used, and the following materials can also be used.
- Acids such as hydrochloric acid, sulfuric acid, sulfonic acid, phosphorus hexafluoride, arsenic pentafluoride, iron chloride
- a dopant such as a metal atom such as a halogen atom, sodium, potassium and iodine, or the like
- a polymer mixture containing fine metal particles and conductive particles such as graphite may be used. These may be used alone or in combination of two or more.
- Gate insulating layer 103 As the gate insulating layer 103, for example, a stacked body (SiO: 85 [nm] + SiN: 65 [nm]) of silicon oxide (SiO) and silicon nitride (SiN) is employed. However, the configuration of the gate insulating layer 103 is not limited to this, and as a constituent material of the gate insulating layer, for example, any known organic material or inorganic material may be used as long as it has an electrical insulating property. Can be used.
- the total thickness of the gate insulating layer 103 is in the range of 150 [nm] to 400 [nm], and its constituent layers (here, a constituent layer made of silicon oxide (SiO) and silicon nitride (SiN)).
- the layer thickness ratio of the component layers can be changed. For example, if the total layer thickness is made constant and the layer thickness of the SiN layer is increased and the layer thickness of the SiO layer is decreased, the breakdown voltage characteristic of the gate insulating layer is improved. The capacitance decreases.
- the gate insulating layer has a laminated structure in which a plurality of layers made of different materials are laminated, so that the degree of freedom in device design can be increased, and the thickness of each layer can be designed according to the TFT characteristics. It is possible to optimize in consideration.
- an acrylic resin for example, an acrylic resin, a phenol resin, a fluorine resin, an epoxy resin, an imide resin, a novolac resin, or the like can be used.
- inorganic materials include silicon oxide, aluminum oxide, tantalum oxide, zirconium oxide, cerium oxide, zinc oxide, cobalt oxide and other metal oxides, silicon nitride, aluminum nitride, zirconium nitride, cerium nitride, zinc nitride, Examples thereof include metal nitrides such as cobalt nitride, titanium nitride, and tantalum nitride, and metal composite oxides such as barium strontium titanate and lead zirconium titanate. These can be used in combination of 1 species or 2 species or more.
- ODTS OTS ⁇ HMDS ⁇ PTS surface treatment agent
- Channel layers 104 and 105 As the channel layers 104 and 105, layers having a layer thickness of 60 [nm] made of amorphous indium gallium zinc oxide (IGZO) are employed.
- the constituent material of the channel layers 104 and 105 is not limited to this, and an oxide semiconductor containing at least one selected from indium (In), gallium (Ga), and zinc (Zn) can be used. .
- the layer thickness of the channel layers 104 and 105 can be in the range of 20 [nm] to 200 [nm], and the channel layer 104 and the channel layer 105 may be set to have different layer thicknesses. it can.
- Channel protective layer 106 As the channel protective layer 106, a layer made of silicon oxide (SiO) with a layer thickness of 240 [nm] is employed. The constituent material of the channel protective layer 106 is not limited to this, and for example, silicon oxynitride (SiON) can be used.
- SiO silicon oxide
- SiON silicon oxynitride
- the layer thickness of the channel protective layer 106 can be in the range of 50 [nm] to 500 [nm].
- the channel protective layer 106 made of silicon oxide (SiO) is observed as hydrogen by temperature programmed desorption analysis, and the average of desorbed gases at 300 [° C.] to 350 [° C.] It is formed in accordance with the provision that the rate of increase of the increase coefficient is not positive.
- Source electrodes 107 and 110 Drain electrodes 108 and 109 As the source electrodes 107 and 110 and the drain electrodes 108 and 109, a stacked body of copper manganese (CuMn), copper (Cu), and molybdenum (Mo) (CuMn: 60 [nm] + Cu: 300 [nm] + Mo: 20 [nm] ]).
- CuMn copper manganese
- Cu copper
- Mo molybdenum
- the layer thicknesses of the source electrodes 107 and 110 and the drain electrodes 108 and 109 can be in the range of 100 [nm] to 500 [nm].
- the passivation layer 112 is a laminate in which the lower insulating layer 1121, the barrier layer 1122, and the upper insulating layers 1123 and 1124 are sequentially laminated from the lower side in the Z-axis direction. It has a configuration.
- the lower insulating layer 1121 is a layer having a thickness of 200 [nm] made of silicon oxide (SiO).
- the barrier layer 1122 is a layer having a thickness of 30 [nm] made of aluminum oxide (AlOx).
- the upper insulating layer 1123 is a layer having a thickness of 260 [nm] made of silicon oxide (SiO).
- the upper insulating layer 1124 is a layer having a thickness of 100 [nm] made of silicon nitride (SiN).
- the barrier layer 1122 is interposed between the lower insulating layer 1121 and the upper insulating layer 1123, and the lower insulating layer 1121 made of silicon oxide (SiO) includes the source electrodes 111 and 115 and the drain electrode. 112 and 114 are in contact.
- SiO silicon oxide
- the barrier layer 1122 has a function of suppressing intrusion of moisture and hydrogen and suppressing deterioration of the channel layers 104 and 105 made of an oxide semiconductor (IGZO or the like).
- the layer density of the barrier layer 1122 is desirably 2.80 g / cm 3 or more. That is, when the layer density of the barrier layer 1122 is less than 2.80 g / cm 3 , the function of suppressing the intrusion of moisture and hydrogen is drastically reduced, and the channel layers 104 and 105 are significantly deteriorated (the sheet resistance value is lowered). become.
- the layer density of the barrier layer 1122 is desirably 3.25 g / cm 3 or less. This is because when the contact hole for forming the upper electrode 113 is formed, a wet etching method is used for the barrier layer 1122, but in the range where the layer density exceeds 3.25 g / cm 3 , the etching is performed. It is desirable that the rate is very small and 3.25 g / cm 3 or less from the viewpoint of production efficiency.
- the upper insulating layer 1124 made of silicon nitride (SiN) is formed in accordance with the definition that the Si—H concentration is 2.3E21 cm ⁇ 3 or less.
- silicon oxynitride SiON
- silicon nitride (SiN) or silicon oxynitride (SiON) can be used.
- silicon oxide (SiO) or silicon oxynitride (SiON) can be used in addition to the above materials.
- the total layer thickness of the passivation layer 112 can be in the range of 200 [nm] to 1000 [nm].
- Upper electrode 113 As the upper electrode 113, a laminate (Cu: 300 [nm] + ITO: 70 [nm]) of copper (Cu) and indium tin oxide (ITO) is employed. Note that the material used for the structure of the upper electrode 113 is not limited to this, and can be appropriately selected from conductive materials.
- Interlayer insulating layer 114 is formed using an organic compound such as polyimide, polyamide, or acrylic resin material.
- the anode 115 is made of a metal material containing silver (Ag) or aluminum (Al).
- the surface portion thereof preferably has high reflectivity.
- anode 115 not only a single layer structure made of a metal material as described above but also a laminate of a metal layer and a transparent conductive layer can be adopted.
- a constituent material of the transparent conductive layer for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like can be used.
- the hole injection layer 116 may be formed of, for example, an oxide such as silver (Ag), molybdenum (Mo), chromium (Cr), vanadium (V), tungsten (W), nickel (Ni), iridium (Ir), or PEDOT. It is a layer made of a conductive polymer material such as (mixture of polythiophene and polystyrene sulfonic acid). In the display panel 10 according to the present embodiment shown in FIG. 3, it is assumed that the hole injection layer 116 made of a metal oxide is formed. In this case, a conductive polymer material such as PEDOT is used. Compared with the case of using, it has a function of injecting holes into the organic light emitting layer 108 stably or assisting the generation of holes, and has a large work function.
- an oxide such as silver (Ag), molybdenum (Mo), chromium (Cr), vanadium (V), tungsten (W), nickel (Ni), iridium
- the hole injection layer 116 is composed of an oxide of a transition metal
- a plurality of levels can be obtained by taking a plurality of oxidation numbers.
- hole injection is facilitated and the drive voltage is increased.
- WO X tungsten oxide
- the bank 117 is formed using an organic material such as a resin and has an insulating property.
- the organic material used for forming the bank 117 include acrylic resin, polyimide resin, and novolac type phenol resin.
- the bank 117 preferably has organic solvent resistance.
- the bank 117 since the bank 117 may be subjected to an etching process, a baking process, or the like during the manufacturing process, the bank 117 should be formed of a highly resistant material that does not excessively deform or alter the process. Is preferred.
- the surface can be treated with fluorine.
- the bank 117 when the bank 117 is formed using a lyophilic material, the difference in lyophilicity / liquid repellency between the surface of the bank 117 and the surface of the light emitting layer 119 is reduced, and the light emitting layer 119 is formed. This is because it becomes difficult to selectively hold ink containing an organic substance in the opening defined by the bank 117.
- the structure of the bank 117 not only a single layer structure as shown in FIG. 3 but also a multilayer structure of two or more layers can be adopted.
- the above materials can be combined for each layer, and an inorganic material and an organic material can be used for each layer.
- the hole transport layer 118 is formed using a polymer compound having no hydrophilic group.
- a polymer compound having no hydrophilic group for example, polyfluorene or a derivative thereof, or a polymer compound such as polyarylamine or a derivative thereof that does not have a hydrophilic group can be used.
- the light emitting layer 119 has a function of emitting light by generating an excited state by injecting and recombining holes and electrons.
- a material used for forming the light-emitting layer 119 it is necessary to use a light-emitting organic material that can be formed by a wet printing method.
- the oxinoid compound, perylene compound, coumarin compound, azacoumarin compound, oxazole compound, oxadiazole compound, perinone compound, pyrrolopyrrole described in Japanese Patent Publication (JP-A-5-163488) Compound, naphthalene compound, anthracene compound, fluorene compound, fluoranthene compound, tetracene compound, pyrene compound, coronene compound, quinolone compound and azaquinolone compound, pyrazoline derivative and pyrazolone derivative, rhodamine compound, chrysene compound, phenanthrene compound, cyclopentadiene compound, stilbene compound , Diphenylquinone compound, styryl compound, butadiene compound, dicyanomethylenepyran compound, dicyanomethylenethiopyran compound, fluoro Cein compounds, pyrylium compounds, thiapyrylium compounds, seren
- Electron transport layer 120 has a function of transporting electrons injected from the cathode 121 to the light emitting layer 119, and includes, for example, an oxadiazole derivative (OXD), a triazole derivative (TAZ), and a phenanthroline derivative (BCP, Bphen). Etc. are formed.
- OXD oxadiazole derivative
- TEZ triazole derivative
- BCP phenanthroline derivative
- the cathode 121 is formed using, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).
- ITO indium tin oxide
- IZO indium zinc oxide
- permeability shall be 80 [%] or more.
- the sealing layer 122 has a function of suppressing exposure of an organic layer such as the light emitting layer 119 to moisture or exposure to air.
- an organic layer such as the light emitting layer 119
- a sealing resin layer made of a resin material such as an acrylic resin or a silicone resin may be provided over a layer formed using a material such as silicon nitride (SiN) or silicon oxynitride (SiON).
- the sealing layer 122 needs to be formed of a light transmissive material.
- gate electrodes 101 and 102 are formed on the surface 100a on the upper side in the Z-axis direction of the substrate 100.
- the gate electrodes 101 and 102 can be formed as follows.
- a metal thin film made of Cu and a metal thin film made of Mo are sequentially laminated using a metal sputtering method, and a resist pattern is formed thereon using a photolithography method.
- the resist pattern is removed. Thereby, the gate electrodes 101 and 102 are formed.
- Gate Insulating Layer 1030 and Channel Layers 104, 105 As shown in FIG. 4B, a gate insulating layer 1030 is formed so as to cover the gate electrodes 101, 102 and the surface 100a of the substrate 100, Channel layers 104 and 105 are formed on the surface 1030a of the gate insulating layer 1030 so as to be spaced apart from each other.
- the gate insulating layer 1030 is formed by sequentially stacking a layer made of SiO and a layer made of SiN using a plasma CVD (Chemical Vapor Deposition) method or a sputtering method.
- the film formation conditions of the gate insulating layer 1030 are, for example, a film formation temperature of 350 [° C.] to 400 [° C.].
- the channel layers 104 and 105 are formed by forming an oxide semiconductor film using a sputtering method and patterning using a photolithography method and a wet etching method.
- the channel protection layer 1060 is formed so as to cover the channel layers 104 and 105 and the surface 1030a of the gate insulating layer 1030.
- the channel protective layer 1060 is formed by using a plasma CVD method or a sputtering method, by laminating and forming a layer made of SiO, and performing an annealing process at a temperature equal to or higher than the film formation temperature in a dry air or oxygen atmosphere after the film formation. Made.
- the film forming conditions of the channel protective layer 1060 in this embodiment are as follows.
- Source Electrodes 107 and 110 and Drain Electrodes 108 and 109 are formed on the surface 1060a of the channel protective layer 1060.
- a contact hole is formed in a corresponding portion of the channel protective layer 1060 and a corresponding portion of the gate insulating layer 103 below the channel protective layer 1060.
- the contact hole is formed by patterning using a photolithography method and then performing etching using a dry etching method.
- plugs are filled into the contact holes formed in the gate insulating layer 103 and the channel protective layer 1060 on the gate electrode 102.
- the source electrodes 107 and 110 and the drain electrodes 108 and 109 are formed by patterning using a photolithography method and a wet etching method. As a result, the source electrode 107 and the drain electrode 108 are also filled in the contact holes and are in contact with the channel layer 104 at the lower part. Similarly, the source electrode 110 and the drain electrode 109 are also filled in the contact holes and are in contact with the channel layer 104 at the bottom.
- drain electrode 108 is connected to the gate electrode 102 via the contact plug 111.
- the lower insulating layer 11210 is formed by performing an annealing process in a dry air or oxygen atmosphere after forming the film using a plasma CVD method or a sputtering method.
- the channel layers 104 and 105 are reduced in resistance due to oxygen deficiency by being placed under vacuum at the time of film formation. Recovery is made.
- the barrier layer 11220 is formed by a CVD method, an ALD (Atomic Layer Deposition) method, or a sputtering method. Note that the thickness of the barrier layer 11220 is preferably 100 [nm] or less. This is because if the layer thickness is too thick, the processing time becomes long. In this embodiment, as an example, the thickness of the barrier layer 11220 is set to 30 [nm].
- the upper insulating layer 11230 is formed using a plasma CVD method or a sputtering method.
- the film formation conditions of the lower insulating layer 11210 and the upper insulating layer 11230 in this embodiment are as follows.
- a contact hole 1120a is opened at a location on the source electrode 110 in the stacked body of the lower insulating layer 11210, the barrier layer 11220, and the upper insulating layer 11230. .
- the contact hole 1120a is formed so that the surface 110a of the source electrode 110 is exposed at the bottom thereof.
- the opening of the contact hole 1120a is executed as follows.
- a hole is opened in the upper insulating layer 11230 by using a dry etching method.
- the surface of the barrier layer 11220 is exposed at the bottom of the hole.
- the dry etching conditions can be the following conditions, for example.
- a hole is opened in the lower insulating layer 11210 from the bottom of the hole formed in the barrier layer 1122, and the contact hole 1120a is completed.
- the surface 110a of the source electrode 110 is exposed at the bottom of the contact hole 1120a.
- the dry etching conditions can be the same as the etching conditions for opening the hole in the upper insulating layer 11230.
- the contact hole 1120a is opened.
- the upper electrode 113 is formed by sputtering, using a photolithography method and a wet etching method after forming a metal film.
- the upper insulating layer 11240 can be formed by depositing a layer made of silicon nitride (SiN) on the upper insulating layer 1123 using a plasma CVD method or a sputtering method.
- the conditions for forming the upper insulating layer 11240 are as follows.
- the film formation temperature is 50 deg. Annealing treatment is performed at a low temperature (300 [° C.]). Accordingly, oxygen defects in the channel layers 104 and 105 made of an oxide semiconductor are repaired, and semiconductor characteristics can be maintained.
- a contact hole 112a is opened at a location corresponding to a part of the upper insulating layer 11240 above the upper electrode 113.
- a dry etching method can be used for the opening of the contact hole 112a. For example, the following conditions can be adopted.
- the interlayer insulating layer 114 is coated with an organic material on the passivation layer 112, planarized, and then contacted with the contact hole 112a. It is formed by opening a hole that communicates.
- the anode 115 is formed by forming a metal film on the surface of the interlayer insulating layer 114 including the inner surface of the side wall surrounding the contact hole.
- the anode 115 is formed by forming a metal film using a sputtering method or a vacuum deposition method, and then patterning using a photolithography method and an etching method. Note that the anode 115 is electrically connected to the upper electrode 113.
- the hole injection layer 116 is formed on the anode 115, and the bank 117 is formed so as to cover the edge.
- the bank 117 surrounds the opening 117a that defines each subpixel, and is provided so that the surface 116a of the hole injection layer 116 is exposed at the bottom thereof.
- the hole injection layer 116 is formed by forming a film made of a metal oxide (for example, tungsten oxide) using a sputtering method and then patterning each subpixel unit using a photolithography method and an etching method.
- a metal oxide for example, tungsten oxide
- a film made of a constituent material of the bank 121 (for example, a photosensitive resin material) is formed on the hole injection layer 116 by using a spin coat method or the like. Then, the resin film is patterned to open the opening 117a.
- the opening 117a is formed by arranging a mask above the resin film, exposing it, and developing it thereafter.
- the hole transport layer 118 is formed by applying an ink containing a constituent material into the opening 117a defined by the bank 117 and then baking it using a printing method.
- the light emitting layer 119 is formed by applying an ink containing a constituent material onto the hole transport layer 118 and then baking it using a printing method.
- the cathode 121 and the sealing layer 122 can be formed using a sputtering method or the like.
- the substrate 126 on which the color filter layer 114 and the like are formed is interposed between the bonding layers 123 to complete the bonded display panel 10.
- the channel layers 104 and 105 are formed of an oxide semiconductor (IGZO), they have high electron mobility and excellent electrical characteristics. For this reason, high electron mobility can be expected without depending on the temperature.
- IGZO oxide semiconductor
- the passivation layer 112 has a lower insulating layer 1121 made of SiO as a first layer, a barrier layer 1122 made of AlOx as a second layer, and an upper insulating layer 1123 made of SiO as a third layer. , And an upper insulating layer 1124 made of SiN as the fourth layer.
- the barrier layer 1122 is made of aluminum oxide as described above, the penetration of moisture and hydrogen can be suppressed (barrier), and the channel layers 104 and 105 made of IGZO can be protected (deterioration of deterioration).
- the lower insulating layer 1121 and the upper insulating layer 1123 made of SiO are observed as hydrogen by thermal desorption analysis, and the rate of increase in the average increase coefficient of desorbed gas from 300 [° C.] to 350 [° C.] is positive It is formed in accordance with the provision that it is not.
- hydrogen can be prevented from entering the channel layers 104 and 105 from the insulating layers 1121 and 1123 during or after the film formation process. Therefore, deterioration of the channel layers 104 and 105 can be suppressed, and high reliability can be ensured.
- the increase rate of the average increase coefficient of the desorbed gas at 300 [° C.] to 350 [° C.] observed as hydrogen by the temperature programmed desorption analysis is not positive. It is formed in accordance with the regulations. In the future, the deterioration of the channel layers 104 and 105 can be suppressed, and high reliability can be ensured.
- the upper insulating layer 1124 made of SiN is formed in accordance with the definition that the Si—H concentration is 2.3E21 [cm ⁇ 3 ] or less. Accordingly, the influence of hydrogen caused by the upper insulating layer 1124 on the channel layers 104 and 105 is small, and deterioration of the channel layers 104 and 105 can be suppressed. Therefore, high reliability can be ensured.
- the passivation layer 112 has a stacked structure in which at least the upper and lower sides of the barrier layer 1122 are sandwiched between the lower insulating layer 1121 and the upper insulating layer 1123, the yield decreases when the contact hole 112a is opened to the passivation layer 112. hard. Therefore, by employing the above structure, it is possible to produce with high yield while suppressing deterioration of the channel layers 104 and 105 made of an oxide semiconductor (IGZO in this embodiment).
- IGZO oxide semiconductor
- the channel protective layer 106 and the lower insulating layer 1121 and the upper insulating layer 1123 of the passivation layer 112 are observed as hydrogen by thermal desorption analysis, and are desorbed at 300 [° C] to 350 [° C].
- the TEG for resistance evaluation is formed by stacking an oxide semiconductor layer made of TAOS (Transparent Amorphous Oxide Semiconductor) on a glass substrate, and a source electrode spaced apart from the oxide semiconductor layer. And two electrodes corresponding to the drain electrode were provided. Then, a channel protective layer made of SiO was laminated on the oxide semiconductor layer, and a PAS1 layer made of SiO and a PAS2 layer made of SiN were laminated in that order.
- TAOS Transparent Amorphous Oxide Semiconductor
- FIG. 7B shows a graph in which the horizontal axis represents the Si—H concentration after film formation and the vertical axis represents the sheet resistance. Note that the data indicated by rhombuses is before annealing, and the data indicated by squares is 1 [hr. ] After the annealing treatment.
- the sheet resistance after the annealing treatment is lower than 1.0E8 [ ⁇ / ⁇ ] when the Si—H concentration exceeds 3.2E21 [cm ⁇ 3 ].
- TAOS is high resistance (1.0E8 [ ⁇ / ⁇ ] or more, actually 1. It can be seen that there is a margin of about 0E10 [ ⁇ / ⁇ ].
- FIG. 8 shows the relationship between the sheet resistance of the sample and the threshold voltage before annealing.
- the threshold voltage Vth is proportional to the sheet resistance value.
- the minus shift of the threshold voltage Vth is large when the sheet resistance value is less than 1.0E8 [ ⁇ / ⁇ ].
- the sheet resistance value is larger than 1.0E8 [ ⁇ / ⁇ ] from the viewpoint of variation of the threshold voltage Vth, whereas the sheet resistance value is 1.0E8 [ ⁇ . / ⁇ ] or more is acceptable.
- two types of samples 1 and 2 were prepared in order to measure the relationship between the Si—H concentration of the SiN layer and the TFT initial characteristics.
- the two types of samples have the same configuration except that the quality of the SiN layer in the passivation layer is different.
- the Si—H concentration in the SiN layer is 3.5E21 [cm ⁇ 3 ]
- the Si—H concentration in the SiN layer is 1.3E21 [cm ⁇ 3 ]. cm -3 ].
- the TFT device of Sample 2 in which the Si—H concentration in the SiN layer is 1.3E21 [cm ⁇ 3 ] is referred to as the TFT initial characteristic. Excellent in terms of viewpoint.
- Sample 1 and sample 2 have different Si—H concentrations by changing the film formation conditions as shown in FIG.
- the film forming conditions for setting the Si—H concentration to 2.3E21 [cm ⁇ 3 ] or less are not limited to the conditions used for forming the sample 2 in FIG. 9A, and can be appropriately set. .
- the channel protective layer 106, and the lower insulating layer 1121 and the upper insulating layer 1123 of the passivation layer 112, which are observed as hydrogen by thermal desorption analysis, are 300 [° C.] to 350 [° C.].
- the effect obtained by adopting the SiO layer in which the rate of increase in the average increase coefficient of the desorbed gas is not positive will be described with reference to FIGS.
- Samples 1 and 2 are samples according to the example, and sample 3 is a sample according to the comparative example. Samples 1 to 3 have different film forming conditions.
- the average increase coefficient of the desorbed gas (hydrogen) is positive in the sample 13 in the range of 300 [° C.] to 350 [° C.]. That is, in Sample 13, the average increase coefficient is approximately 1.0E- 13 when the temperature is 300 [° C.], whereas the average increase coefficient increases toward 350 [° C.].
- the rate of increase in the average increase coefficient of the desorbed gas at 300 [° C.] to 350 [° C.], which is observed as hydrogen by the temperature programmed desorption analysis in the SiO layer, can be changed depending on the film forming conditions. .
- FIG. 11A is a graph showing the TFT initial characteristics of the TFT samples using the SiO layers of Samples 11 and 12, and FIG. 11B is the TFT initial characteristics of the TFT sample using the SiO layer of Sample 13. It is a graph which shows.
- the TFT samples employing the SiO layers of Samples 11 and 12 show excellent TFT initial characteristics, whereas as shown in FIG. It can be seen that the TFT sample using the SiO layer has no characteristics as a TFT.
- the channel protective layer 106 and the lower insulating layer 1121 and the upper insulating layer 1123 of the passivation layer 112 are observed as hydrogen by thermal desorption analysis, and are 300 [° C.] to 350
- a TFT device having excellent initial TFT characteristics can be realized by employing a SiO layer in which the increase rate of the average increase coefficient of desorbed gas at [° C.] is not positive.
- the sample used for measuring the TAOS carrier time has a configuration in which a channel layer made of IGZO and a channel protective layer made of SiO are sequentially laminated on a substrate made of glass.
- the channel layer thickness t 2 30 [nm]
- the channel protective layer thickness t 1 240 [nm].
- the sample shown in FIG. 12A is irradiated with microwaves having a frequency of 26 [GHz], and the reflection intensity I 1 (base intensity) is measured.
- the sample is irradiated with an ultraviolet pulse laser simultaneously with microwave irradiation.
- the irradiation conditions of the ultraviolet pulse laser are as follows.
- the attenuation constant time from the peak P 1 to the point P 2 that becomes 1 / e
- Sample 21 (indicated as “S21” in the figure) and Sample 23 (indicated as “S23” in the figure) have a film formation rate of 50 nm / nm. sec. ] To 110 [nm / sec. ], While the sample 22 (shown as “S22” in the figure) is 150 [nm / sec. Sample 24 (shown as “S24” in the figure) is 200 [nm / sec. ].
- the film formation rate is 50 [nm / sec. ] To 110 [nm / sec. ]
- In the range of the carrier lifetime T is 3.0E-2 [ ⁇ sec. It can be seen that this is superior.
- the carrier lifetime T of the samples 21 to 24 are viewed from the viewpoint of the refractive index, the sample 23 whose refractive index is in the range of 1.454 to 1.461.
- the carrier lifetime T is 3.0E-2 [ ⁇ sec. ] It is long as described above, and is superior to the other samples 21, 22, and 24.
- TFT initial characteristics TFT initial characteristics of TFT samples in which the SiO layer having the film quality as in the above samples 21 to 23 is used as the channel protective layer, the lower insulating layer of the passivation layer, and the upper insulating layer are shown in FIG. To FIG. 14 (c). Note that when the SiO layer having the film quality as in the sample 24 is employed, the threshold voltage Vth is greatly shifted, so that the Vg-Id graph is not shown.
- the film formation rate is 50 [nm / sec. ] To 110 [nm / sec. ],
- the TFT device using the SiO layer of the sample 23 having the refractive index in the range of 1.454 to 1.461 is the TFT device using the SiO layer of the other samples 21, 22, and 24.
- Carrier lifetime T (1 / eLT) is 3.0E-2 [ ⁇ sec.
- the TFT characteristics are excellent.
- FIG. 15A the TFT characteristics of the TFT device according to this embodiment are shown in FIG. 15A
- FIG. 15B the TFT characteristics of the TFT device according to the comparative example are shown in FIG. ).
- the channel protective layer 106, the lower insulating layer 1121 of the passivation layer 112, and the upper insulating layer 1123 are observed as hydrogen by temperature programmed desorption analysis, which is 300 [° C.] to 350 [350 [
- a SiN layer having a Si—H concentration of 2.3E21 cm ⁇ 3 or less is used.
- the threshold voltage shift ⁇ Vth ⁇ 5.68 in the TFT device according to the comparative example including the channel protective layer and the passivation layer formed with film quality other than those described above. It became a big thing with [V].
- NBTS characteristics can be obtained by providing the film-quality SiO layer and SiN layer as in the TFT device according to the present embodiment.
- Embodiment 2 The configuration of the display panel 30 according to Embodiment 2 of the present invention will be described with reference to FIG. In FIG. 16, only a part of the configuration of the display panel 30 (a configuration mainly including the TFT device portion) is extracted and illustrated, and the configuration of the portion not illustrated is related to the first embodiment. The same configuration as that of the display panel 10 is adopted. In FIG. 16 as well, parts having the same configuration as the display panel 10 according to the first embodiment are given the same reference numerals.
- an interlayer insulating layer 327 is formed so as to cover the source electrodes 107 and 110, the drain electrodes 108 and 109, and the channel protective layer 106.
- the passivation layer 312 is formed thereon.
- the upper electrode 313 connected to the source electrode 110 is formed along the inner wall of the contact hole formed in the interlayer insulating layer 327, and a part of the upper part is formed in the interlayer insulating layer 327 and the lower insulating layer 3121 in the passivation layer 312. It is inserted in the boundary part between.
- the passivation layer 312 includes, in order from the lower side in the Z-axis direction, a lower insulating layer 3121 made of SiO, a barrier layer 3122 made of an aluminum compound such as aluminum oxide, and an upper insulating layer 3123 made of SiN. It has a laminated structure in which it is laminated.
- An anode 315 is formed on the passivation layer 312 via an interlayer insulating layer 314.
- the anode 315 is electrically connected to the upper electrode 313 through a contact hole formed in the interlayer insulating layer 314 and the passivation layer 312.
- the channel protective layer 106 and the lower insulating layer 3121 of the passivation layer 312 are observed as hydrogen by thermal desorption analysis, which is 300 [° C.].
- An SiO layer having a non-positive increase rate of the desorption gas average at ⁇ 350 [° C.] is employed, and the Si—H concentration of the upper insulating layer 3123 of the passivation layer 312 is 2.3E21 cm ⁇ 3 or less. Adopt layer. For this reason, the TFT characteristics are excellent as in the first embodiment.
- the channel layers 104 and 105 are formed of an oxide semiconductor (IGZO), and thus have high electron mobility and excellent electrical characteristics. . For this reason, high electron mobility can be expected without depending on the temperature.
- IGZO oxide semiconductor
- the passivation layer 312 includes the barrier layer 3122 made of an aluminum compound such as aluminum oxide, so that intrusion (barrier) of moisture and hydrogen is suppressed, and the channel layer 104 made of IGZO. , 105 can be protected (deterioration suppression).
- the TFT device according to this embodiment and the display device including the TFT device are stable and have excellent reliability.
- Embodiment 3 The configuration of the display panel 40 according to Embodiment 3 of the present invention will be described with reference to FIG. Also in FIG. 17, only a part of the configuration of the display panel 40 (a configuration mainly including the TFT device portion) is extracted and illustrated, and the configuration of the portion not illustrated is described in the first embodiment. The same configuration as that of the display panel 10 is adopted. Also in FIG. 17, the same reference numerals are given to the same components as those of the display panel 10 according to the first embodiment.
- the passivation layer 412 formed so as to cover the source electrodes 107 and 110, the drain electrodes 108 and 109, and the channel protective layer 106 has a five-layer configuration.
- a lower insulating layer 4121 made of SiO a barrier layer 4122 made of an aluminum compound such as aluminum oxide, an upper insulating layer 4123 made of SiO, an upper insulating layer 4124 made of SiN, And an upper insulating layer 4125 made of SiN.
- channel protective layer 106 and lower insulating layer 4121 and upper insulating layer 4123 of passivation layer 412 are observed as hydrogen by thermal desorption analysis.
- An SiO layer having a non-positive increase rate of the average desorption gas at 300 [° C.] to 350 [° C.] is adopted, and the upper insulating layers 4124 and 4125 of the passivation layer 412 have an Si—H concentration of 2.
- a SiN layer of 3E21 cm ⁇ 3 or less is employed.
- the upper electrode 413 is formed along the inner wall of the contact hole formed in the lower insulating layer 4121, the barrier layer 4122, and the upper insulating layers 412 and 4124. A part of the upper electrode 413 is formed between the upper insulating layer 4124 and the upper insulating layer 4125. It is inserted in the interface part between.
- An anode 415 is formed on the passivation layer 412 with an interlayer insulating layer 414 interposed therebetween.
- the anode 415 is electrically connected to the upper electrode 413 through contact holes formed in the interlayer insulating layer 414 and the upper insulating layer 4125. It is connected.
- the channel protective layer 106 and the passivation layer 412 are provided with the SiO layer and the SiN layer having the same film quality as in the first embodiment, the TFT characteristics are similarly excellent. Further, since two SiO layers and two SiN layers in the passivation layer 412 are provided, the reliability is higher than those in the first and second embodiments.
- the channel layers 104 and 105 are formed of an oxide semiconductor (IGZO), and thus have a large electron mobility and an excellent electrical characteristic. . For this reason, high electron mobility can be expected without depending on the temperature.
- IGZO oxide semiconductor
- the passivation layer 412 includes the barrier layer 4122 made of an aluminum compound such as aluminum oxide, the channel layer made of IGZO is suppressed (barrier) from the entry of moisture and hydrogen. 104 (105) can be protected (deterioration suppression).
- the TFT device according to this embodiment and the display device including the TFT device are stable and have excellent reliability.
- Embodiment 4 The configuration of the display panel 50 according to Embodiment 4 of the present invention will be described with reference to FIG. Also in FIG. 18, only a part of the configuration of the display panel 50 (a configuration mainly including the TFT device portion) is extracted and illustrated, and the configuration of the portion not illustrated is described in the first embodiment. The same configuration as that of the display panel 10 is adopted. In FIG. 18 as well, parts having the same configuration as that of the display panel 10 according to Embodiment 1 are given the same reference numerals.
- the passivation layer 512 formed so as to cover the source electrodes 107 and 110, the drain electrodes 108 and 109, and the channel protective layer 106 has a four-layer configuration.
- the channel protective layer 106 and the lower insulating layer 5121 of the passivation layer 512 are observed as hydrogen by thermal desorption analysis, which is 300 [° C.].
- An SiO layer with a non-positive increase rate of the average desorption gas at 350 ° C. is used, and the upper insulating layers 5123 and 5124 of the passivation layer 512 have an Si—H concentration of 2.3E21 cm ⁇ 3 or less.
- a certain SiN layer is adopted.
- the density of the upper insulating layer 5123 is lower than the density of the upper insulating layer 5124, which facilitates taper when the contact hole is opened.
- the upper electrode 513 is formed along the inner wall of the contact hole formed in the lower insulating layer 5121, the barrier layer 5122, and the upper insulating layer 5123, and a part of the upper electrode is between the upper insulating layer 5123 and the upper insulating layer 5124. It is inserted in the interface part.
- An anode 515 is formed on the passivation layer 512 via an interlayer insulating layer 514, and the connection form between the anode 515 and the upper electrode 513 is the same as described above.
- the channel protective layer 106 and the passivation layer 512 are provided with the SiO layer and the SiN layer having the same film quality as in the first embodiment, the TFT characteristics are similarly excellent.
- the channel layers 104 and 105 are formed of an oxide semiconductor (IGZO), they have high electron mobility and excellent electrical characteristics. For this reason, high electron mobility can be expected without depending on the temperature.
- IGZO oxide semiconductor
- the passivation layer 512 includes the barrier layer 5122 made of an aluminum compound such as aluminum oxide, the channel layer made of IGZO suppresses the entry of moisture and hydrogen (barrier). 104 (105) can be protected (deterioration suppression).
- the TFT device according to this embodiment and the display device including the TFT device are stable and have excellent reliability.
- Embodiment 5 The configuration of the display panel 60 according to Embodiment 5 of the present invention will be described with reference to FIG. Also in FIG. 19, only a part of the configuration of the display panel 60 (a configuration mainly including the TFT device) is extracted and illustrated, and the configuration of the portion not illustrated is described in the first embodiment. The same configuration as that of the display panel 10 is adopted. Also in FIG. 19, the same reference numerals are given to the same components as those of the display panel 10 according to the first embodiment.
- the passivation layer 612 formed so as to cover the source electrodes 107 and 110, the drain electrodes 108 and 109, and the channel protective layer 106 has a two-layer structure.
- the lower insulating layer 6121 made of SiO and the barrier layer 6122 made of an aluminum compound such as aluminum oxide are sequentially laminated from the lower side in the Z-axis direction.
- the channel protective layer 106 and the lower insulating layer 6121 of the passivation layer 612 are observed as hydrogen by thermal desorption analysis, which is 300 [° C.].
- An SiO layer having a non-positive increase rate of the average increase coefficient of desorbed gas at ⁇ 350 [° C.] is employed.
- the upper electrode 613 is formed along the inner wall of the contact hole formed in the lower insulating layer 6121, and a part of the upper part is interposed between the lower insulating layer 6121 and the barrier layer 6122 at the interface portion.
- An anode 615 is formed on the passivation layer 612 via an interlayer insulating layer 614, and the anode 615 is electrically connected to the upper electrode 613 through a contact hole formed in the interlayer insulating layer 614 and the barrier layer 6122. Has been.
- the SiN layer is not provided as a constituent layer of the passivation layer 612 in this embodiment mode, an SiO layer having the same film quality as that in Embodiment Mode 1 is provided as the channel protective layer 106 and the lower insulating layer 6121 of the passivation layer 612. Similarly, it has excellent TFT characteristics. Also in the TFT device according to this embodiment, since the channel layers 104 and 105 are formed of an oxide semiconductor (IGZO), they have high electron mobility and excellent electrical characteristics. For this reason, high electron mobility can be expected without depending on the temperature.
- IGZO oxide semiconductor
- the passivation layer 612 includes the barrier layer 6122 made of an aluminum compound such as aluminum oxide, the channel layer made of IGZO suppresses the entry of moisture and hydrogen (barrier). 104 (105) can be protected (deterioration suppression).
- the TFT device according to this embodiment and the display device including the TFT device are stable and have excellent reliability.
- Embodiment 6 The configuration of the display panel 70 according to Embodiment 6 of the present invention will be described with reference to FIG. Also in FIG. 20, only a part of the structure of the display panel 70 (the structure mainly including the TFT device) is extracted and illustrated, and the structure of the part not shown is described in the first embodiment. The same configuration as that of the display panel 10 is adopted. Also in FIG. 20, the same reference numerals are assigned to the same components as those of the display panel 10 according to the first embodiment.
- the passivation layer 712 formed so as to cover the source electrodes 107 and 110, the drain electrodes 108 and 109, and the channel protective layer 106 includes the above-described embodiment.
- the four-layer structure is different from the passivation layer 512 according to the fourth aspect.
- the barrier layer 7122 is formed as the uppermost layer in the Z-axis direction.
- the channel protective layer 106 and the lower insulating layer 7121 of the passivation layer 712 are observed as hydrogen by thermal desorption analysis, which is 300 [° C.].
- a SiO layer having a non-positive increase rate of the average increase coefficient of desorbed gas at 350 ° C. is employed, and the lower insulating layers 7123 and 5124 of the passivation layer 712 have an Si—H concentration of 2.3E21 cm ⁇ 3 or less.
- a certain SiN layer is adopted.
- the upper electrode 713 is formed along the inner wall of the contact hole formed in the lower insulating layer 7121 and the lower insulating layer 7123, and a part of the upper electrode is interposed between the lower insulating layer 7123 and the lower insulating layer 7124 at the interface portion. It is inserted.
- an anode 715 is formed via an interlayer insulating layer 714, and the connection form between the anode 715 and the upper electrode 713 is the same as described above.
- the channel protective layer 106 and the passivation layer 712 are provided with the SiO layer and the SiN layer having the same film quality as in the first embodiment, the TFT characteristics are similarly excellent.
- the channel layers 104 and 105 are formed of an oxide semiconductor (IGZO), they have high electron mobility and excellent electrical characteristics. For this reason, high electron mobility can be expected without depending on the temperature.
- IGZO oxide semiconductor
- the passivation layer 712 includes the barrier layer 7122 made of an aluminum compound such as aluminum oxide, the channel layer made of IGZO is suppressed (barrier) from moisture and hydrogen. 104 (105) can be protected (deterioration suppression).
- the TFT device according to this embodiment and the display device including the TFT device are stable and have excellent reliability.
- Embodiment 7 The configuration of the display panel 80 according to Embodiment 7 of the present invention will be described with reference to FIG. Also in FIG. 21, only a part of the configuration of the display panel 80 (a configuration mainly including the TFT device) is extracted and illustrated, and the configuration of the portion not illustrated is described in the first embodiment. The same configuration as that of the display panel 10 is adopted. Also in FIG. 21, the same reference numerals are given to the same components as those of the display panel 10 according to the first embodiment.
- the passivation layer 812 formed so as to cover the source electrodes 107 and 110, the drain electrodes 108 and 109, and the channel protective layer 106 has a two-layer structure.
- it has a stacked structure of a lower insulating layer 8121 made of SiO and an upper insulating layer 8123 made of SiN in order from the lower side in the Z-axis direction.
- the channel protective layer 106 and the lower insulating layer 8121 of the passivation layer 812 are observed as hydrogen by thermal desorption analysis, which is 300 [° C.].
- An SiO layer having a non-positive increase rate of the desorption gas average at ⁇ 350 [° C.] is employed, and the Si—H concentration of the upper insulating layer 8123 of the passivation layer 812 is 2.3E21 cm ⁇ 3 or less.
- the upper electrode 813 is formed along the inner wall of the contact hole formed in the lower insulating layer 8121, and a part of the upper part is interposed between the lower insulating layer 8121 and the upper insulating layer 8123 at the interface portion.
- An anode 815 is formed on the passivation layer 812 with an interlayer insulating layer 814 interposed therebetween, and the connection form between the anode 815 and the upper electrode 813 is the same as described above.
- the channel protective layer 106 and the passivation layer 812 are provided with the SiO layer and the SiN layer having the same film quality as in the first embodiment, the TFT characteristics are similarly excellent.
- the channel layers 104 and 105 are formed of an oxide semiconductor (IGZO), they have high electron mobility and excellent electrical characteristics. For this reason, high electron mobility can be expected without depending on the temperature.
- IGZO oxide semiconductor
- the passivation layer 812 has a laminated structure of a lower insulating layer 8121 made of SiO and an upper insulating layer 8123 made of SiN, so the number of constituent layers is small, and therefore the number of man-hours in manufacturing Can be reduced.
- a barrier layer made of aluminum oxide, which is difficult to open a contact hole, is not provided, there is a manufacturing merit.
- the TFT device according to this embodiment and the display device including the TFT device are stable and have excellent reliability.
- Embodiment 8 The configuration of the display panel 90 according to Embodiment 8 of the present invention will be described with reference to FIG. Also in FIG. 22, only a part of the configuration of the display panel 90 (a configuration mainly including the TFT device portion) is extracted and illustrated, and the configuration of the portion not illustrated is described in the first embodiment. The same configuration as that of the display panel 10 is adopted. Also in FIG. 22, the same reference numerals are given to the same components as those of the display panel 10 according to the first embodiment.
- the passivation layer 912 formed to cover the source electrodes 107 and 110, the drain electrodes 108 and 109, and the channel protective layer 106 has a three-layer structure.
- the lower insulating layer 9121 made of SiO, the upper insulating layer 9123 made of SiN, and the upper insulating layer 9124 made of SiN are laminated in order from the lower side in the Z-axis direction.
- the channel protective layer 106 and the lower insulating layer 9121 of the passivation layer 912 are observed as hydrogen by thermal desorption analysis, which is 300 [° C.].
- An SiO layer with a non-positive increase rate of the average increase coefficient of the desorbed gas at 350 ° C. is employed, and the upper insulating layers 9123 and 9124 of the passivation layer 912 have an Si—H concentration of 2.3E21 cm ⁇ 3 or less.
- a certain SiN layer is adopted.
- the density of the upper insulating layer 9123 is lower than the density of the upper insulating layer 9124, as in the fourth embodiment, so that when the contact hole is opened, Tapering is easy.
- the upper electrode 913 is formed along the inner wall of the contact hole formed in the lower insulating layer 9121 and the upper insulating layer 9123, and a part of the upper electrode is interposed between the upper insulating layer 9123 and the upper insulating layer 9124 at the interface portion. It is inserted.
- an anode 915 is formed via an interlayer insulating layer 914.
- the connection form between the anode 915 and the upper electrode 913 is the same as described above.
- the channel protective layer 106 and the passivation layer 912 are provided with the SiO layer and the SiN layer having the same film quality as in the first embodiment, the TFT characteristics are similarly excellent.
- the two upper insulating layers 9123 and 9124 made of SiN are provided on the channel protective layer 106 through the lower insulating layer 9121 made of SiO, hydrogen and hydrogen are formed by a dense film. Intrusion of moisture into the channel layers 104 and 105 can be suppressed.
- the channel layers 104 and 105 are formed of an oxide semiconductor (IGZO), they have high electron mobility and excellent electrical characteristics. For this reason, high electron mobility can be expected without depending on the temperature.
- IGZO oxide semiconductor
- the passivation layer 912 is not provided with a barrier layer made of aluminum oxide, and has a manufacturing advantage related to the establishment of a contact hole.
- the TFT device according to this embodiment and the display device including the TFT device are stable and have excellent reliability.
- a laminated structure of 2 to 5 layers is adopted as the passivation layer.
- the present invention is not limited to this, and a passivation layer having a single layer structure can be adopted, or a passivation layer having a laminated structure of six or more layers can be adopted.
- the combination of the constituent layers in the case of the laminated configuration it is sufficient that at least the SiO layer or the SiN layer is included, and whether or not a barrier layer made of an aluminum compound is employed can be appropriately changed.
- a SiON layer can be adopted as an alternative to the SiO layer or the SiN layer. Even in this case, the above-mentioned effect regarding the Si-H concentration and the above-mentioned rule regarding the rate of increase in the average increase coefficient of the desorbed gas observed as hydrogen by temperature programmed desorption analysis can be satisfied. it can.
- the channel protective layer may have not only a single-layer structure made of SiO but also a two-layer structure of a layer made of SiO and a layer made of SiN, or a stacked structure of three or more layers. Even in this case, the above-mentioned effect regarding the Si-H concentration and the above-mentioned rule regarding the rate of increase in the average increase coefficient of the desorbed gas observed as hydrogen by temperature programmed desorption analysis can be satisfied. it can.
- the SiN layer is included in the configuration of the channel protective layer, it is desirable to interpose the SiN layer closer to the channel layer than the SiN layer. This is for the purpose of further suppressing hydrogen intrusion into the channel layer.
- a bottom gate type (reverse stagger type) TFT device is used as an example.
- the present invention may be applied to a top gate type (stagger type) TFT device. it can. In this case, the same effect as described above can be obtained.
- a top emission type EL display panel is taken as an example of the display panel, but the present invention is not limited to this.
- it can be applied to a bottom emission type display panel or the like, and can also be applied to a liquid crystal panel, a field emission display panel, electronic paper, or the like.
- the configuration in which two transistor element portions Tr 1 and Tr 2 are provided for one subpixel 10a is adopted.
- the present invention is not limited to this. Absent.
- one transistor element unit may be provided for one subpixel, or three or more transistor element units may be provided.
- the constituent materials of each part can be changed as appropriate.
- the barrier layer in the passivation layer is not limited to AlOx, and a nitride or oxynitride containing Al can also be employed.
- the constituent materials of the gate electrode, the source electrode, and the drain electrode also include, for example, a laminated structure of a layer made of Mo and a layer made of Al, a layer made of Mo, and an alloy layer made of Al—Nd. It can also be set as a laminated structure.
- an anode is disposed below the EL element portion, and anodes 115, 315, 415, 515, 615, 715, 815, and 915 are connected to the source electrode 110 of the TFT device.
- a cathode is arranged at the lower part of the EL element part and an anode is arranged at the upper part. In this case, a cathode disposed below is connected to the drain of the TFT device.
- the present invention is useful for realizing a thin film transistor device having high electrical characteristics.
- Display panel 10a Subpixel 20. Drive / control section 21-24. Drive circuit 25.
- Substrate 101,102. Gate electrode 103,1030.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Electroluminescent Light Sources (AREA)
- Manufacturing & Machinery (AREA)
Abstract
Description
本発明の一態様に係るTFT装置は、(i)基板と、(ii)ゲート電極と、(iii)ソース電極およびドレイン電極と、(iv)チャネル層と、(v)チャネル保護層と、(vi)パッシベーション層とを備える。
(ii) ゲート電極の上方にチャネル層を形成する工程
(iii) チャネル層上に、チャネル保護層を形成する工程
(iv) チャネル保護層上に、互いの間に間隔をあけ、且つ、それぞれがチャネル保護層に開けられた孔(コンタクト孔)を通してチャネル層に一部が接するソース電極およびドレイン電極を形成する工程
(v) チャネル保護層、およびソース電極、およびドレイン電極の上方を覆うパッシベーション層を形成する工程
そして、本態様に係るTFT装置の製造方法では、上記(ii)の工程において、酸化物半導体材料を用いてチャネル層を形成し、上記(ii)の工程、および上記(v)の工程の少なくとも一方の工程では、窒化シリコンまたは酸窒化シリコンからなり、Si-H濃度が2.3E21cm-3以下である第1構成層を形成するサブ工程を有する。
1.表示装置1の全体構成
以下では、本発明の実施の形態1に係る表示装置1の全体構成について、図1を用い説明する。
表示パネル10における各サブピクセル10aの回路構成について、図2を用い説明する。
表示パネル10の構成について、図3の模式断面図を用い説明する。
図3に示すように、基板100上には、ゲート電極101,102が互いに間隔をあけて形成され、ゲート電極101,102および基板100の表面を被覆するように、ゲート絶縁層103が形成されている。ゲート絶縁層103上には、ゲート電極101,102のそれぞれに対応してチャネル層104,105が形成されている。そして、チャネル層104,105およびゲート絶縁層103の表面を被覆するように、チャネル保護層106が形成されている。
層間絶縁層114上には、サブピクセル単位でアノード115が設けられている。アノード115は、層間絶縁層114および上部絶縁層1124における上部電極113の上方に開設されたコンタクト孔を通して、上部電極113に接続されている。なお、上部電極113は、Z軸下部において、ソース電極110に接続されている。
図3に示す各部の構成材料について、一例を示す。
基板100,130の構成材料としては、例えば、例えば、ガラス基板、石英基板、シリコン基板、硫化モリブデン、銅、亜鉛、アルミニウム、ステンレス、マグネシウム、鉄、ニッケル、金、銀などの金属基板、ガリウム砒素基などの半導体基板、プラスチック基板等を採用することができる。
ゲート電極101,102としては、例えば、銅(Cu)とモリブデン(Mo)との積層体(Cu:300[nm]+Mo:20[nm])を採用している。ただし、ゲート電極101,102の構成については、これに限定されず、例えば、Cu、Cu/Wなどを採用することもできるし、次のような材料を採用することも可能である。
ゲート絶縁層103としては、例えば、酸化シリコン(SiO)と窒化シリコン(SiN)との積層体(SiO:85[nm]+SiN:65[nm])を採用している。ただし、ゲート絶縁層103の構成は、これに限定されるものではなく、 ゲート絶縁層の構成材料としては、例えば、電気絶縁性を有する材料であれば、公知の有機材料や無機材料のいずれも用いることができる。
チャネル層104,105としては、アモルファス酸化インジウムガリウム亜鉛(IGZO)からなる層厚が60[nm]の層を採用している。チャネル層104,105の構成材料は、これに限定されるものではなく、インジウム(In)、ガリウム(Ga)、亜鉛(Zn)から選択される少なくとも一種を含む酸化物半導体を採用することができる。
チャネル保護層106としては、酸化シリコン(SiO)からなる層厚が240[nm]の層を採用している。チャネル保護層106の構成材料は、これに限定されるものではなく、例えば、酸窒化シリコン(SiON)を用いることができる。
ソース電極107,110、ドレイン電極108,109としては、銅マンガン(CuMn)と銅(Cu)とモリブデン(Mo)の積層体(CuMn:60[nm]+Cu:300[nm]+Mo:20[nm])を採用している。
本実施の形態に係る表示パネル10では、上記のように、パッシベーション層112が、下部絶縁層1121、バリア層1122、および上部絶縁層1123,1124がZ軸方向下側から順に積層されてなる積層構成を有する。
上部電極113としては、銅(Cu)と酸化インジウムスズ(ITO)との積層体(Cu:300[nm]+ITO:70[nm])を採用している。なお、上部電極113の構成に用いる材料としては、これに限定されるものではなく、導電性を有する材料から適宜選択することが可能である。
層間絶縁層114は、例えば、ポリイミド、ポリアミド、アクリル系樹脂材料などの有機化合物を用い形成されている。
アノード115は、銀(Ag)またはアルミニウム(Al)を含む金属材料から構成されている。トップエミッション型の本実施の形態に係る表示パネル10の場合には、その表面部が高い反射性を有することが好ましい。
ホール注入層116は、例えば、銀(Ag)、モリブデン(Mo)、クロム(Cr)、バナジウム(V)、タングステン(W)、ニッケル(Ni)、イリジウム(Ir)などの酸化物、あるいは、PEDOT(ポリチオフェンとポリスチレンスルホン酸との混合物)などの導電性ポリマー材料からなる層である。なお、図3に示す本実施の形態に係る表示パネル10では、金属酸化物からなるホール注入層116を構成することを想定しているが、この場合には、PEDOTなどの導電性ポリマー材料を用いる場合に比べて、ホールを安定的に、またはホールの生成を補助して、有機発光層108に対しホールを注入する機能を有し、大きな仕事関数を有する。
バンク117は、樹脂等の有機材料を用い形成されており絶縁性を有する。バンク117の形成に用いる有機材料の例としては、アクリル系樹脂、ポリイミド系樹脂、ノボラック型フェノール樹脂等があげられる。バンク117は、有機溶剤耐性を有することが好ましい。さらに、バンク117は、製造工程中において、エッチング処理、ベーク処理など施されることがあるので、それらの処理に対して過度に変形、変質などをしないような耐性の高い材料で形成されることが好ましい。また、表面に撥水性をもたせるために、表面をフッ素処理することもできる。
ホール輸送層118は、親水基を備えない高分子化合物を用い形成されている。例えば、ポリフルオレンやその誘導体、あるいはポリアリールアミンやその誘導体などの高分子化合物であって、親水基を備えないものなどを用いることができる。
発光層119は、上述のように、ホールと電子とが注入され再結合されることにより励起状態が生成され発光する機能を有する。発光層119の形成に用いる材料は、湿式印刷法を用い製膜できる発光性の有機材料を用いることが必要である。
電子輸送層120は、カソード121から注入された電子を発光層119へ輸送する機能を有し、例えば、オキサジアゾール誘導体(OXD)、トリアゾール誘導体(TAZ)、フェナンスロリン誘導体(BCP、Bphen)などを用い形成されている。
カソード121は、例えば、酸化インジウムスズ(ITO)若しくは酸化インジウム亜鉛(IZO)などを用い形成される。本実施の形態のように、トップエミッション型の本実施の形態に係る表示パネル10の場合においては、光透過性の材料で形成されることが必要となる。光透過性については、透過率が80[%]以上とすることが好ましい。
封止層122は、発光層119などの有機層が水分に晒されたり、空気に晒されたりすることを抑制する機能を有し、例えば、窒化シリコン(SiN)、酸窒化シリコン(SiON)などの材料を用い形成される。また、窒化シリコン(SiN)、酸窒化シリコン(SiON)などの材料を用い形成された層の上に、アクリル樹脂、シリコーン樹脂などの樹脂材料からなる封止樹脂層を設けてもよい。
表示パネル10の製造方法について、図4から図6を用い説明する。
図4(a)に示すように、基板100のZ軸方向上側の表面100aに、互いに間隔をあけたゲート電極101,102を形成する。ゲート電極101,102の形成は、具体的に次のように行うことができる。
図4(b)に示すように、ゲート電極101,102および基板100の表面100aを被覆するように、ゲート絶縁層1030を形成し、ゲート絶縁層1030の表面1030aに互いに間隔をあけたチャネル層104,105を形成する。
図4(c)に示すように、チャネル層104,105およびゲート絶縁層1030の表面1030aを被覆するように、チャネル保護層1060を積層形成する。
電力;100[W]
圧力;4[torr]
N2O;1200[sccm]
SiH4;16[sccm]
電極間距離;550[mils]
なお、成膜後におけるアニール処理については、成膜中に発生するチャネル層104,105中の酸素欠陥を修復し、半導体特性を維持するためになされる。
図4(d)に示すように、チャネル保護層1060の表面1060aに、ソース電極107,110およびドレイン電極108,109を形成する。
図5(a)に示すように、ソース電極107,108およびドレイン電極108,109およびチャネル保護層106を被覆するように、下部絶縁層11210と、バリア層11220と、上部絶縁層11230とを順に積層形成する。
電力;100[W]
圧力;4[torr]
N2O;1200[sccm]
SiH4;16[sccm]
電極間距離;550[mils]
(6)コンタクト孔1120aの開設
図5(b)に示すように、下部絶縁層11210、バリア層11220、および上部絶縁層11230の積層体におけるソース電極110上の箇所に、コンタクト孔1120aを開設する。コンタクト孔1120aは、その底部にソース電極110の表面110aが露出するように形成される。コンタクト孔1120aの開設は、次のように実行される。
CF4/O2=80/20[sccm]
Pressure=13[Pa]
ICP/Bias=0/300[W]
Time=40[sec.](OE.50%)
(ii)2nd.
O2=150[sccm]
Pressure=13[Pa]
ICP/Bias=500/30[W]
Time=60[sec.]
次に、ウェットエッチング法を用い、上部絶縁層1123に開設された孔底から、バリア層11220に孔を開設する。孔底には、下部絶縁層11210の表面が露出する。ウェットエッチングは、PAN(リン酸/酢酸/硝酸)系エッチャントを用い、40[℃]で320[sec.]とした。
図5(c)に示すように、下部絶縁層1121、バリア層1122、および上部絶縁層1123の積層体に開設されたコンタクト孔1120aの内壁に沿って上部電極113を形成する。上部電極113の上部は、その一部が上部絶縁層1123上に配される。そして、上部電極113および上部絶縁層1123を被覆するように、上部絶縁層11240を積層形成する。
電力;150[W]
圧力;1.5[torr]
NH3;50[sccm]
N2;1000[sccm]
SiH4;15[sccm]
電極間距離;350[mils]
なお、本実施の形態に係る製造方法では、上部絶縁層11240の成膜後に、成膜温度より50deg.低い温度(300[℃])でアニール処理を施す。これにより、酸化物半導体からなるチャネル層104,105中の酸素欠陥が修復され、半導体特性を維持することができる。
図5(d)に示すように、上部絶縁層11240における上部電極113の上方の一部に相当する箇所に、コンタクト孔112aを開設する。コンタクト孔112aの開設には、ドライエッチング法を用いることができ、例えば、次のような条件を採用することができる。
CF4/O2=80/20[sccm]
Pressure=13[Pa]
ICP/Bias=0/300[W]
Time=53[sec.](OE.50%)
(ii)2nd.
O2=150[sccm]
Pressure=13[Pa]
ICP/Bias=500/30[W]
Time=60[sec.]
以上のようにして、コンタクト孔112aが開設されたパッシベーション層112が完成し、コンタクト孔112aからは、上部電極113の側壁内面が露出する。
図6(a)に示すように、層間絶縁層114は、パッシベーション層112上に有機材料を塗布し、表面を平坦化した後、コンタクト孔112aに連通する孔を開設することで形成される。
図6(a)に示すように、アノード115上に対して、ホール注入層116を形成し、その縁部を覆うようにバンク117を形成する。バンク117は、各サブピクセルを規定する開口117aを囲繞し、その底部にホール注入層116の表面116aが露出するように設けられる。
図6(b)に示すように、バンク117で規定された各開口部117a内に、ホール注入層116側から順に、ホール輸送層118、発光層119、および電子輸送層120を積層形成する。
図6(b)に示すように、電子輸送層120およびバンク117の頂部を被覆するように、カソード121および封止層122を順に積層形成する。
本実施の形態に係る表示パネル10が備えるTFT装置では、チャネル層104,105が酸化物半導体(IGZO)から形成されているので、大きな電子移動度を有し、優れた電気特性を有する。このため、温度の高低に依存せず、高い電子移動度が期待できる。
以下では、チャネル保護層106、およびパッシベーション層112の下部絶縁層1121、上部絶縁層1123について、昇温脱離分析により水素として観測される、300[℃]~350[℃]における脱離ガスの平均増加係数の増加率が正ではないSiO層とすることで得られる効果と、パッシベーション層112の上部絶縁層1124について、Si-H濃度が2.3E21cm-3以下であるSiN層とすることで得られる効果についての確認結果について、説明する。
先ず、パッシベーション層112の上部絶縁層1124について、Si-H濃度が2.3E21[cm-3]以下であるSiN層とすることで得られる効果について、図7から図9を用い説明する。
成膜後におけるSi-H濃度とシート抵抗との関係を確認するため、図7(a)に示すサンプルを準備した。
以上の結果を考慮して、パッシベーション層におけるSiN層(上部絶縁層)のSi-H濃度とTFT初期特性との関係について、図9を用い説明する。
次に、チャネル保護層106、およびパッシベーション層112の下部絶縁層1121および上部絶縁層1123について、昇温脱離分析により水素として観測される、300[℃]~350[℃]における脱離ガスの平均増加係数の増加率が正ではないSiO層を採用することで得られる効果について、図10から図14を用い説明する。
図10(a)に示すように、昇温脱離測定によるSiOの水素放出スペクトルを得るためのサンプルを3種類準備した。サンプル1,2は、実施例に係るサンプルであり、サンプル3は、比較例に係るサンプルである。サンプル1~3は、互いに成膜条件を変えている。
上記サンプル11,12のような膜質を有するSiO層をチャネル保護層、およびパッシベーション層の下部絶縁層、上部絶縁層として採用したTFTサンプルのTFT初期特性について、図11(a)および図11(b)に示す。図11(a)は、サンプル11,12のSiO層を採用したTFTサンプルのTFT初期特性を示すグラフであり、図11(b)は、サンプル13のSiO層を採用したTFTサンプルのTFT初期特性を示すグラフである。
以上上の結果より、チャネル保護層106、およびパッシベーション層112の下部絶縁層1121および上部絶縁層1123について、昇温脱離分析により水素として観測される、300[℃]~350[℃]における脱離ガスの平均増加係数の増加率が正ではないSiO層を採用することにより、優れたTFT初期特性を有するTFT装置を実現できる。
《サンプル構成》
キャリアライフタイムを測定するために用いたサンプルの構成を図12(a)に示す。
本測定における「キャリアライフタイム」の定義について、図12(b)を用い説明する。
・λ=349[nm]
・パルス時間幅;15[nsec.]
マイクロ波の反射強度I2を測定する。そして、反射強度I2から反射強度I1を差し引いた差分(I2-I1)を求め、その時間変化カーブを図12(b)のように作成する。
図13(a)に示すように、成膜条件を変えた4種類のサンプル21~24を作製した。
上記サンプル21~23のような膜質を有するSiO層をチャネル保護層、およびパッシベーション層の下部絶縁層、上部絶縁層として採用したTFTサンプルのTFT初期特性について、図14(a)から図14(c)に示す。なお、サンプル24のような膜質を有するSiO層を採用する場合には、閾値電圧Vthが大きくシフトしてしまったため、Vg-Idグラフの掲載を省略している。
以上のような測定結果を総合して、本実施の形態に係るTFT装置でのTFT特性を図15(a)に示し、比較例に係るTFT装置のTFT特性を図15(b)に示す。なお、図15(a)および図15(b)の測定は、90[℃]で、W/L=50[μm]/10[μm]との条件下で行った。
本発明の実施の形態2に係る表示パネル30の構成について、図16を用い説明する。図16では、表示パネル30の一部構成(TFT装置の部分を主とする構成)だけを抜き出して図示しており、図示を省略している部分の構成については、上記実施の形態1に係る表示パネル10と同一構成を採用している。また、図16においても、上記実施の形態1に係る表示パネル10と同一構成の部位については、同一の符号を付している。
本発明の実施の形態3に係る表示パネル40の構成について、図17を用い説明する。図17においても、表示パネル40の一部構成(TFT装置の部分を主とする構成)だけを抜き出して図示しており、図示を省略している部分の構成については、上記実施の形態1に係る表示パネル10と同一構成を採用している。また、図17においても、上記実施の形態1に係る表示パネル10と同一構成の部位については、同一の符号を付している。
本発明の実施の形態4に係る表示パネル50の構成について、図18を用い説明する。図18においても、表示パネル50の一部構成(TFT装置の部分を主とする構成)だけを抜き出して図示しており、図示を省略している部分の構成については、上記実施の形態1に係る表示パネル10と同一構成を採用している。また、図18においても、上記実施の形態1に係る表示パネル10と同一構成の部位については、同一の符号を付している。
本発明の実施の形態5に係る表示パネル60の構成について、図19を用い説明する。図19においても、表示パネル60の一部構成(TFT装置の部分を主とする構成)だけを抜き出して図示しており、図示を省略している部分の構成については、上記実施の形態1に係る表示パネル10と同一構成を採用している。また、図19においても、上記実施の形態1に係る表示パネル10と同一構成の部位については、同一の符号を付している。
本発明の実施の形態6に係る表示パネル70の構成について、図20を用い説明する。図20においても、表示パネル70の一部構成(TFT装置の部分を主とする構成)だけを抜き出して図示しており、図示を省略している部分の構成については、上記実施の形態1に係る表示パネル10と同一構成を採用している。また、図20においても、上記実施の形態1に係る表示パネル10と同一構成の部位については、同一の符号を付している。
本発明の実施の形態7に係る表示パネル80の構成について、図21を用い説明する。図21においても、表示パネル80の一部構成(TFT装置の部分を主とする構成)だけを抜き出して図示しており、図示を省略している部分の構成については、上記実施の形態1に係る表示パネル10と同一構成を採用している。また、図21においても、上記実施の形態1に係る表示パネル10と同一構成の部位については、同一の符号を付している。
本発明の実施の形態8に係る表示パネル90の構成について、図22を用い説明する。図22においても、表示パネル90の一部構成(TFT装置の部分を主とする構成)だけを抜き出して図示しており、図示を省略している部分の構成については、上記実施の形態1に係る表示パネル10と同一構成を採用している。また、図22においても、上記実施の形態1に係る表示パネル10と同一構成の部位については、同一の符号を付している。
上記実施の形態1~8では、パッシベーション層として、2層から5層の積層構成を採用した。本発明では、これに限らず、1層構成のパッシベーション層を採用することもできるし、6層以上の積層構成のパッシベーション層を採用することもできる。
10,30,40,50,60,70,80,90.表示パネル
10a.サブピクセル
20.駆動・制御部
21~24.駆動回路
25.制御回路
100,126.基板
101,102.ゲート電極
103,1030.ゲート絶縁層
104,105.チャネル層
106,1060.チャネル保護層
107,110.ソース電極
108,109.ドレイン電極
111.コンタクトプラグ
112,312,412,512,612,712,812,912.パッシベーション層
113,313,413,513,613,713,813,913.上部電極
114,314,327,414,514,614,714,814,914.層間絶縁層
115,315,415,515,615,715,815,915.アノード
116.ホール注入層
117.バンク
118.ホール輸送層
119.発光層
120.電子輸送層
121.カソード
122.封止層
123.接合層
124.カラーフィルタ層
125.遮光層
1121,3121,4121,5121,6121,7121,7123,7124,8121,9121,11210.下部絶縁層
1122,3122,4122,5122,6122,7122,11220.バリア層
1123,1124,3123,4123,4124,4125,5123,5124,8123,9123,9124,11230,11240.上部絶縁層
Claims (17)
- 基板と、
前記基板の上方に形成されたゲート電極と、
前記基板の上方であって、前記ゲート電極に対して間隔をあけ、且つ、互いの間に間隔をあけて設けられたソース電極およびドレイン電極と、
前記ゲート電極と前記ソース電極および前記ドレイン電極との間に挿設され、前記ソース電極および前記ドレイン電極の各一部が接するチャネル層と、
前記ソース電極および前記ドレイン電極の各一部が前記チャネル層に接する部分を除き、前記チャネル層と、前記ソース電極および前記ドレイン電極との間に挿設されたチャネル保護層と、
前記ゲート電極、および前記ソース電極、および前記ドレイン電極および前記チャネル層、および前記チャネル保護層の上方を覆うように設けられたパッシベーション層と、
を備え、
前記チャネル層は、酸化物半導体材料からなり、
前記チャネル保護層および前記パッシベーション層の少なくとも一方は、窒化シリコンまたは酸窒化シリコンからなり、Si-H濃度が2.3E21cm-3以下である第1構成層を含む
ことを特徴とする薄膜トランジスタ装置。 - 前記チャネル保護層および前記パッシベーション層の少なくとも一方に含まれる前記第1構成層のSi-H濃度は、1.3E21cm-3以下である
請求項1記載の薄膜トランジスタ装置。 - 前記チャネル保護層および前記パッシベーション層の少なくとも一方は、酸化シリコンまたは酸窒化シリコンからなり、昇温脱離分析により水素として観測される300℃から350℃における脱離ガスの平均増加係数の増加率が正ではない第2構成層を含む
請求項1または請求項2記載の薄膜トランジスタ装置。 - 前記チャネル保護層は、前記第2構成層を含む
請求項3記載の薄膜トランジスタ装置。 - 前記チャネル保護層は、50nm/sec.から110nm/sec.のレートを以って成膜された酸化シリコンからなる層であって、屈折率が1.454から1.461である
請求項4記載の薄膜トランジスタ装置。 - 前記パッシベーション層は、前記基板の側から第1層、第2層、および第3層を含む積層構成を有し、
前記パッシベーション層の前記第1層および前記第3層の少なくとも一方の層は、前記第1構成層であり、
前記パッシベーション層の前記第2層は、アルミニウムの化合物からなる層である
請求項1から請求項5の何れか記載の薄膜トランジスタ装置。 - 前記パッシベーション層の前記第2層は、酸化アルミニウムからなる
請求項6記載の薄膜トランジスタ装置。 - 前記パッシベーション層には、前記第3層上に積層された第4が前記積層構成中に更に含まれ、
前記パッシベーション層の前記第3層および前記第4層は、ともに窒化シリコンからなり、
前記第3層の窒化シリコンの密度は、前記第4層の窒化シリコンの密度よりも低い
請求項6または請求項7記載の薄膜トランジスタ装置。 - 前記パッシベーション層の前記第1層は、酸化シリコンからなり、
前記ソース電極および前記ドレイン電極に接している
請求項6から請求項8の何れか記載の薄膜トランジスタ装置。 - 請求項1から請求項9の何れか記載の薄膜トランジスタ装置を備える
ことを特徴とする表示装置。 - 基板の上方にゲート電極を形成する工程と、
前記ゲート電極の上方にチャネル層を形成する工程と、
前記チャネル層上に、チャネル保護層を形成する工程と、
前記チャネル保護層上に、互いの間に間隔をあけ、且つ、それぞれが前記チャネル保護層に開けられた孔を通して前記チャネル層に一部が接するソース電極およびドレイン電極を形成する工程と、
前記チャネル保護層、および前記ソース電極、および前記ドレイン電極の上方を覆うパッシベーション層を形成する工程と、
を備え、
前記チャネル層を形成する工程では、酸化物半導体材料を用いて前記チャネル層を形成し、
前記チャネル保護層を形成する工程、および前記パッシベーション層を形成する工程の少なくとも一方の工程では、窒化シリコンまたは酸窒化シリコンからなり、Si-H濃度が2.3E21cm-3以下である第1構成層を形成するサブ工程を有する
ことを特徴とする薄膜トランジスタ装置の製造方法。 - 前記第1構成層を形成するサブ工程では、当該第1構成層の成膜後において、成膜温度より50deg.低い温度でアニール処理を施す
請求項11記載の薄膜トランジスタ装置の製造方法。 - 前記チャネル保護層を形成する工程、および前記パッシベーション層を形成する工程の少なくとも一方の工程では、酸化シリコンまたは酸窒化シリコンからなり、昇温脱離分析により水素として観測される300℃から350℃における脱離ガスの平均増加係数の増加率が正ではない第2構成層を形成するサブ工程を有する
請求項11または請求項12記載の薄膜トランジスタ装置の製造方法。 - 前記第2構成層を形成するサブ工程は、前記チャネル保護層を形成する工程に含まれ、
前記第2構成層を形成するサブ工程では、50nm/sec.から110nm/sec.のレートを以って成膜し、屈折率が1.454から1.461である酸化シリコンからなる層を、前記第2構成層として形成する
請求項13記載の薄膜トランジスタ装置の製造方法。 - 前記第2構成層を形成するサブ工程では、当該第2構成層の成膜後において、ドライエア、あるいは酸素雰囲気中で、成膜温度以上の温度でアニール処理を施す
請求項13または請求項14記載の薄膜トランジスタ装置の製造方法。 - 前記パッシベーション層を形成する工程は、
前記チャネル保護層、および前記ソース電極、および前記ドレイン電極の上に、酸化シリコンからなる層を、前記第2構成層として形成するサブ工程と、
前記酸化シリコンからなる層上に、アルミニウムの化合物からなる層を形成するサブ工程と、
前記アルミニウムの化合物からなる層の上方に、窒化シリコンからなる層を、前記第1構成層として形成するサブ工程と、
を有する
請求項11から請求項15の何れか記載の薄膜トランジスタ装置の製造方法。 - 前記酸化シリコンからなる層上には、酸化アルミニウムからなる層を、前記アルミニウムの化合物からなる層として形成する
請求項16記載の薄膜トランジスタ装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015519618A JP6083053B2 (ja) | 2013-05-29 | 2014-04-03 | 薄膜トランジスタ装置とその製造方法、および表示装置 |
US14/894,027 US9799772B2 (en) | 2013-05-29 | 2014-04-03 | Thin film transistor device, method for manufacturing same and display device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013-112741 | 2013-05-29 | ||
JP2013112741 | 2013-05-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014192210A1 true WO2014192210A1 (ja) | 2014-12-04 |
Family
ID=51988265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2014/001929 WO2014192210A1 (ja) | 2013-05-29 | 2014-04-03 | 薄膜トランジスタ装置とその製造方法、および表示装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9799772B2 (ja) |
JP (1) | JP6083053B2 (ja) |
WO (1) | WO2014192210A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102279884B1 (ko) * | 2014-12-05 | 2021-07-22 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판 및 그 제조 방법 |
JP2017152252A (ja) * | 2016-02-25 | 2017-08-31 | 株式会社ジャパンディスプレイ | 表示装置 |
JP2018021993A (ja) * | 2016-08-02 | 2018-02-08 | 株式会社ジャパンディスプレイ | 半導体基板及びそれを用いた表示装置 |
CN106252362B (zh) * | 2016-08-31 | 2019-07-12 | 深圳市华星光电技术有限公司 | 一种阵列基板及其制备方法 |
KR102606738B1 (ko) | 2017-02-10 | 2023-11-24 | 글로벌웨이퍼스 씨오., 엘티디. | 반도체 구조들을 평가하기 위한 방법들 |
CN106876416B (zh) * | 2017-03-30 | 2020-02-11 | 合肥鑫晟光电科技有限公司 | 静电放电单元、阵列基板和显示面板 |
CN111048523A (zh) * | 2019-11-25 | 2020-04-21 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及其制备方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004056099A (ja) * | 2002-05-17 | 2004-02-19 | Semiconductor Energy Lab Co Ltd | 窒化珪素膜、並びに半導体装置及びその作製方法 |
JP2007123861A (ja) * | 2005-09-29 | 2007-05-17 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP2011091381A (ja) * | 2009-09-24 | 2011-05-06 | Semiconductor Energy Lab Co Ltd | 半導体素子、半導体素子の作製方法 |
JP2012104639A (ja) * | 2010-11-10 | 2012-05-31 | Toshiba Mobile Display Co Ltd | 薄膜トランジスタ回路基板及びその製造方法 |
JP2012119667A (ja) * | 2010-11-11 | 2012-06-21 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5443922A (en) | 1991-11-07 | 1995-08-22 | Konica Corporation | Organic thin film electroluminescence element |
JPH05163488A (ja) | 1991-12-17 | 1993-06-29 | Konica Corp | 有機薄膜エレクトロルミネッセンス素子 |
TWI288443B (en) | 2002-05-17 | 2007-10-11 | Semiconductor Energy Lab | SiN film, semiconductor device, and the manufacturing method thereof |
EP1995787A3 (en) | 2005-09-29 | 2012-01-18 | Semiconductor Energy Laboratory Co, Ltd. | Semiconductor device having oxide semiconductor layer and manufacturing method therof |
JP5305630B2 (ja) | 2006-12-05 | 2013-10-02 | キヤノン株式会社 | ボトムゲート型薄膜トランジスタの製造方法及び表示装置の製造方法 |
WO2011027656A1 (en) * | 2009-09-04 | 2011-03-10 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and display device |
JP5679143B2 (ja) * | 2009-12-01 | 2015-03-04 | ソニー株式会社 | 薄膜トランジスタならびに表示装置および電子機器 |
TWI471946B (zh) * | 2010-11-17 | 2015-02-01 | Innolux Corp | 薄膜電晶體 |
KR101832361B1 (ko) * | 2011-01-19 | 2018-04-16 | 삼성디스플레이 주식회사 | 박막 트랜지스터 표시판 및 그 제조 방법 |
JP5740270B2 (ja) * | 2011-09-27 | 2015-06-24 | 株式会社東芝 | 薄膜トランジスタ、その製造方法、および表示装置 |
US9116408B2 (en) * | 2011-11-11 | 2015-08-25 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal element and method for manufacturing the same |
CN104335332B (zh) * | 2012-05-28 | 2017-09-05 | 夏普株式会社 | 半导体装置及其制造方法 |
WO2014046068A1 (ja) * | 2012-09-24 | 2014-03-27 | シャープ株式会社 | アクティブマトリックス基板、表示装置、及び、その製造方法 |
TWI620323B (zh) * | 2012-11-16 | 2018-04-01 | 半導體能源研究所股份有限公司 | 半導體裝置 |
TWI515912B (zh) * | 2013-05-08 | 2016-01-01 | 友達光電股份有限公司 | 半導體元件 |
US9893088B2 (en) * | 2013-05-29 | 2018-02-13 | Joled Inc. | Thin film transistor device, method for manufacturing same and display device |
WO2014196107A1 (ja) * | 2013-06-04 | 2014-12-11 | パナソニック株式会社 | 薄膜トランジスタ素子とその製造方法及び表示装置 |
JP6326270B2 (ja) * | 2013-06-28 | 2018-05-16 | 株式会社神戸製鋼所 | 薄膜トランジスタおよびその製造方法 |
JP6104775B2 (ja) * | 2013-09-24 | 2017-03-29 | 株式会社東芝 | 薄膜トランジスタ及びその製造方法 |
JP2015149467A (ja) * | 2014-01-10 | 2015-08-20 | 株式会社Joled | 薄膜トランジスタ基板の製造方法 |
US9595546B2 (en) * | 2014-02-25 | 2017-03-14 | Lg Display Co., Ltd. | Display backplane and method of fabricating the same |
KR20160086016A (ko) * | 2015-01-08 | 2016-07-19 | 삼성디스플레이 주식회사 | 박막 트랜지스터 표시판 및 이의 제조 방법 |
US9887277B2 (en) * | 2015-01-23 | 2018-02-06 | Applied Materials, Inc. | Plasma treatment on metal-oxide TFT |
-
2014
- 2014-04-03 US US14/894,027 patent/US9799772B2/en active Active
- 2014-04-03 JP JP2015519618A patent/JP6083053B2/ja active Active
- 2014-04-03 WO PCT/JP2014/001929 patent/WO2014192210A1/ja active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004056099A (ja) * | 2002-05-17 | 2004-02-19 | Semiconductor Energy Lab Co Ltd | 窒化珪素膜、並びに半導体装置及びその作製方法 |
JP2007123861A (ja) * | 2005-09-29 | 2007-05-17 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP2011091381A (ja) * | 2009-09-24 | 2011-05-06 | Semiconductor Energy Lab Co Ltd | 半導体素子、半導体素子の作製方法 |
JP2012104639A (ja) * | 2010-11-10 | 2012-05-31 | Toshiba Mobile Display Co Ltd | 薄膜トランジスタ回路基板及びその製造方法 |
JP2012119667A (ja) * | 2010-11-11 | 2012-06-21 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2014192210A1 (ja) | 2017-02-23 |
US9799772B2 (en) | 2017-10-24 |
JP6083053B2 (ja) | 2017-02-22 |
US20160093744A1 (en) | 2016-03-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6057106B2 (ja) | 薄膜トランジスタ装置とその製造方法、および表示装置 | |
JP6083053B2 (ja) | 薄膜トランジスタ装置とその製造方法、および表示装置 | |
CN106158881B (zh) | 有机发光显示装置 | |
US10811631B2 (en) | Thin film transistor element substrate, method of producing the substrate, and organic EL display device including the thin film transistor element substrate | |
JPWO2013183289A1 (ja) | 薄膜トランジスタ、表示パネルおよび薄膜トランジスタの製造方法 | |
JP2016091841A (ja) | 有機発光デバイスと有機表示装置 | |
JP6439194B2 (ja) | 有機発光デバイス | |
JP6241859B2 (ja) | アクティブマトリクス型表示パネルの製造方法とアクティブマトリクス型表示パネル | |
JP6358510B2 (ja) | 薄膜トランジスタ装置、及びそれを用いた表示装置 | |
JP6232661B2 (ja) | 薄膜トランジスタ装置、及びそれを用いた表示装置 | |
JP6387562B2 (ja) | 有機発光デバイスおよび有機表示装置 | |
US9461270B2 (en) | Method for manufacturing organic light emitting diode display device | |
JP6779839B2 (ja) | 有機el表示パネル及び有機el表示パネルの製造方法 | |
JP6175676B2 (ja) | 電子デバイスおよびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14804394 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2015519618 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14894027 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 14804394 Country of ref document: EP Kind code of ref document: A1 |