WO2014187008A1 - 像素单元和阵列基板 - Google Patents

像素单元和阵列基板 Download PDF

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Publication number
WO2014187008A1
WO2014187008A1 PCT/CN2013/078169 CN2013078169W WO2014187008A1 WO 2014187008 A1 WO2014187008 A1 WO 2014187008A1 CN 2013078169 W CN2013078169 W CN 2013078169W WO 2014187008 A1 WO2014187008 A1 WO 2014187008A1
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Prior art keywords
extending direction
pad
pixel unit
data line
parallel
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PCT/CN2013/078169
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English (en)
French (fr)
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姚晓慧
薛景峰
许哲豪
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深圳市华星光电技术有限公司
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Priority to US13/985,693 priority Critical patent/US20140346534A1/en
Publication of WO2014187008A1 publication Critical patent/WO2014187008A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a pixel unit, and to an array substrate.
  • the liquid crystal display device includes a pair of substrates and a liquid crystal layer interposed between the pair of substrates, and the two substrates are respectively provided with electric field generating electrodes such as a pixel electrode and a common electrode.
  • electric field generating electrodes such as a pixel electrode and a common electrode.
  • the pixel electrode in the liquid crystal display device is generally designed as a plurality of strip electrodes which are parallel and spaced apart from each other, and the strip electrodes are further divided into a plurality of portions, and the strip electrodes of each portion extend in different directions.
  • the pixel electrode becomes a "meter" type or "" type structure.
  • FIG. 1 is a schematic structural diagram of a unit pixel in a liquid crystal display device of the prior art.
  • the liquid crystal display device has a scanning line G1, a data line D1, a pad 110, and a plurality of strip electrodes 120.
  • the scan line G1 and the data line D1 are perpendicular to each other, and pads 110 are formed at the intersections, and the pads 110 are generally rectangular.
  • the scan line G1 and the data line D1 are connected by a wire and a pad 110.
  • the plurality of strip electrodes 120 are parallel and spaced apart from each other.
  • the plurality of strip electrodes 120 and the scan line G1, the data line D1 and the pad 110 are respectively in different layers, and the layers are insulated.
  • a plurality of strip electrodes 120 are connected to the underlying pads 110 through vias 101.
  • FIG. 2 is a schematic diagram of the pointing of liquid crystal molecules corresponding to the pixel shown in FIG. 1 .
  • FIG. 3 is a schematic diagram of an optical analog image of the pixel shown in FIG. 1.
  • the area A1 and the area A2 are areas corresponding to the edges of the pads 110.
  • the liquid crystal molecules of the remaining areas have substantially uniform alignment directions except for the areas A1 and A2.
  • the area B1 corresponds to the area A1
  • the area B2 corresponds to the area A2.
  • the shadow C indicates the pad 110.
  • the light transmittance of the remaining areas is high, and the light transmittance of the area 110 and the area B2 is low due to the electric field of the pad 110, and this phenomenon is It is called the "dark grain" phenomenon.
  • a primary object of the present invention is to provide a pixel unit and an array substrate capable of reducing the influence of an electric field of a strip electrode.
  • a technical solution adopted by the present invention is to provide a pixel unit, the pixel unit includes: a scan line extending along a first extending direction; and a data line extending along a second extending direction. An extending direction intersects the second extending direction; the pad is formed at the intersection of the scan line and the data line, the pad is electrically connected to the scan line and the data line; the insulating layer, the insulating layer covers the scan line and the data line, and the insulating layer
  • the layer is provided with a via hole; a plurality of strip electrodes, the strip electrodes are parallel and spaced apart from each other, the strip electrodes are disposed on the insulating layer and extend along the third extending direction, and the third extending direction forms a predetermined angle with the first extending direction,
  • the plurality of strip electrodes are electrically connected to the pad through the via hole; wherein the pad and the strip electrode are both made of a transparent conductive material, and the shape of the pad is at least one set of
  • the pixel unit further includes a thin film transistor, where the thin film transistor is located at the intersection of the scan line and the data line, and the gate of the thin film transistor is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected to the pad.
  • the predetermined angle is 45 degrees.
  • the transparent conductive material is indium tin oxide.
  • the strip electrodes are spaced apart from each other by the same pitch.
  • the pixel unit includes: a scan line extending along a first extending direction; and a data line extending along a second extending direction.
  • the first extending direction intersects the second extending direction;
  • the pad is formed at the intersection of the scan line and the data line, the pad is electrically connected to the scan line and the data line;
  • the insulating layer covers the scan line and the data line,
  • the insulating layer is provided with a through hole; a plurality of strip electrodes, the plurality of strip electrodes are parallel and spaced apart from each other, the strip electrodes are disposed on the insulating layer and extend along the third extending direction, and the third extending direction forms a predetermined angle with the first extending direction a plurality of strip electrodes are electrically connected to the pads through the via holes; wherein the pads and the strip electrodes are made of a transparent conductive material, the shape of the pads is a polygon, and at least one side of the
  • the pixel unit further includes a thin film transistor, where the thin film transistor is located at the intersection of the scan line and the data line, and the gate of the thin film transistor is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected to the pad.
  • the shape of the pad is at least one set of parallelograms of opposite sides, and at least one pair of opposite sides of the pad is parallel to the third extending direction.
  • the shape of the via hole is a polygon, and at least one side of the via hole is parallel to the third extending direction.
  • the shape of the via hole is at least one set of quadrilateral parallel sides, and at least one pair of opposite sides of the via hole is parallel to the third extending direction.
  • the first extending direction is perpendicular to the second extending direction.
  • the predetermined angle is 45 degrees.
  • the transparent conductive material is indium tin oxide.
  • the strip electrodes are spaced apart from each other by the same pitch.
  • another technical solution adopted by the present invention is to provide an array substrate, wherein the array substrate includes a glass substrate and a pixel unit, and the pixel unit is disposed on the glass substrate, wherein the pixel unit includes: a scan line.
  • the scan line extends along the first extending direction; the data line extends along the second extending direction, the first extending direction intersects the second extending direction; the pad is formed at the intersection of the scan line and the data line, and the pad is The scan line and the data line are electrically connected; the insulating layer covers the scan line and the data line with an insulating layer, and the insulating layer is provided with a via hole; a plurality of strip electrodes, a plurality of strip electrodes are parallel and spaced apart from each other, and the strip electrodes are disposed on the insulating layer And extending along a third extending direction, the third extending direction forms a predetermined angle with the first extending direction, and the plurality of strip electrodes are electrically connected to the pad through the via hole; wherein the pad and the strip electrode are made of a transparent conductive material
  • the shape of the pad is a polygon, and at least one side of the pad is parallel to the third extending direction.
  • the pixel unit further includes a thin film transistor, where the thin film transistor is located at the intersection of the scan line and the data line, and the gate of the thin film transistor is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected to the pad.
  • the shape of the pad is at least one set of parallelograms of opposite sides, and at least one pair of opposite sides of the pad is parallel to the third extending direction.
  • the shape of the via hole is a polygon, and at least one side of the via hole is parallel to the third extending direction.
  • the shape of the via hole is at least one set of quadrilateral parallel sides, and at least one pair of opposite sides of the via hole is parallel to the third extending direction.
  • the first extending direction is perpendicular to the second extending direction.
  • At least one side of the pad in the pixel unit and the array substrate of the present invention is parallel to the extending direction of the strip electrode, so that the electric field of at least one side of the pad does not affect the electric field of the strip electrode, and the strip shape can be reduced.
  • the electric field of the electrode is affected, effectively suppressing the "dark lines" around the pad and improving the display quality.
  • FIG. 1 is a schematic structural view of a unit pixel in a liquid crystal display device of the prior art
  • FIG. 2 is a schematic view showing the orientation of liquid crystal molecules corresponding to the pixel shown in FIG. 1;
  • FIG. 3 is a schematic diagram of an optical analog image of the pixel shown in FIG. 1;
  • FIG. 4 is a schematic structural view of a first embodiment of a pixel unit of the present invention.
  • FIG. 5 is a schematic diagram showing the pointing of liquid crystal molecules corresponding to the pixel unit shown in FIG. 4;
  • FIG. 6 is a schematic diagram of an optical analog image of the pixel unit shown in FIG. 4;
  • Fig. 7 is a schematic structural view of a second embodiment of a pixel unit of the present invention.
  • FIG. 4 is a schematic structural diagram of a first embodiment of a pixel unit according to the present invention.
  • the pixel unit includes a scan line G4, a data line D4, a pad 410, an insulating layer (not shown), and a plurality of strip electrodes 420.
  • the scanning line G4 extends in the first extending direction S1, and the data line D4 extends in the second extending direction S2.
  • the first extending direction S1 intersects with the second extending direction S2.
  • the first extending direction S1 is perpendicular to the second extending direction S2.
  • the pad 410 is formed at the intersection of the scan line G4 and the data line D4, and the pad 410 is electrically connected to the scan line G4 and the data line D4, for example, by wire bonding.
  • the insulating layer covers the scan line G4 and the data line D4, and covers the pad 410, and the insulating layer is provided with a via 401.
  • the strip electrodes 420 are parallel to each other and spaced apart from each other. Preferably, the strip electrodes 420 are spaced apart from each other with the same pitch.
  • the strip electrodes 420 are disposed on the insulating layer and extend along the third extending direction S3.
  • the third extending direction S3 and the An extending direction S1 forms a predetermined angle.
  • the predetermined angle is 45 degrees, and the plurality of strip electrodes 420 are electrically connected to the pads 410 through the via holes 401, for example, by wire bonding.
  • the pad 410 and the strip electrode 420 are both made of a transparent conductive material.
  • the transparent conductive material is indium tin oxide.
  • the shape of the pad 410 is a polygon, and at least one side of the pad 410 is parallel to the third extending direction S3. Further, the pad 410 may be at least one set of parallelograms of opposite sides, and at least one pair of opposite sides of the pad 410 are parallel to the third extending direction S3. In the present embodiment, the shape of the pad 410 is a rectangle. In other embodiments, the shape of the pad 410 may also be trapezoidal or diamond shaped.
  • the electric field direction of the pad 410 on the strip side is the same as the electric field direction of the strip electrode 420, thereby reducing the influence of the pad 410 on the electric field of the strip electrode 420.
  • the "dark grain" phenomenon around the pad 410 is effectively suppressed, and the display quality is improved.
  • the strip electrode 420 is connected to the data line D4 through the pad 410. Therefore, the pixel unit adopts a passive driving mode, and an instant of inputting the driving voltage waveform on the scanning line G4 and the data line D4 will be instantaneous.
  • a driving waveform is synthesized on the strip electrode 420 to guide the alignment of the liquid crystal molecules.
  • FIG. 5 is a schematic diagram of the pointing of the liquid crystal molecules corresponding to the pixel unit shown in FIG. 4, and FIG. 6 is a schematic diagram of the optical analog image of the pixel unit shown in FIG.
  • the area A'1 and the area A'2 are respectively a region near the pair of opposite sides of the pad 410 in the third extending direction S3, in which the alignment direction of the liquid crystal molecules is changed little, It is basically consistent with the alignment direction of the liquid crystal molecules in the remaining regions.
  • region B'1 corresponds to region A'1
  • region B'2 corresponds to region A'2
  • shadow C' indicates pad 410. In these two areas, the light transmittance did not decrease significantly compared to the rest of the area, indicating that the "dark grain" phenomenon was effectively suppressed.
  • the shape of the via 401 is also a polygonal shape in the present embodiment. At least one side of 401 is parallel to the third extending direction S3.
  • the via 401 has the same shape as the pad 410, and the shape of the via 401 is at least one set of quadrilaterals having opposite sides, and at least one pair of opposite sides of the via 401 is parallel to the third extending direction S3.
  • FIG. 7 is a schematic structural diagram of a second embodiment of a pixel unit according to the present invention.
  • the pixel unit includes a scan line G7, a data line D7, a pad 710, an insulating layer (not shown), a plurality of strip electrodes 720, and a thin film transistor 730.
  • the scanning line G7 extends in the first extending direction S1, the data line D7 extends in the second extending direction S2, and the first extending direction S1 intersects the second extending direction S2.
  • the pad 710 is formed at the intersection of the scan line G7 and the data line D7, and the pad 710 is electrically connected to the scan line G7 and the data line D7, for example, by wire bonding.
  • the insulating layer covers the scan line G7 and the data line D7, and covers the pad 710, and the insulating layer is provided with a via 701.
  • the plurality of strip electrodes 720 are parallel and spaced apart from each other, and the strip electrodes 720 are disposed on the insulating layer and extend in the third extending direction S3, and the third extending direction S3 forms a predetermined angle with the first extending direction S1.
  • a plurality of strip electrodes 720 are electrically connected to the pads 710 through vias 701.
  • the thin film transistor 730 is located at the intersection of the scan line G7 and the data line D7, and the gate of the thin film transistor 730 is electrically connected to the scan line G7, the source is electrically connected to the data line D7, and the drain is electrically connected to the pad 710.
  • the pad 710 and the strip electrode 720 are each made of a transparent conductive material, the shape of the pad 710 is a polygon, and at least one side of the pad 710 is parallel to the third extending direction S3. Since at least one side of the pad 710 is parallel to the strip electrode 720, the electric field direction of the pad 710 in the vicinity of the side is the same as the electric field direction of the strip electrode 720. Therefore, the electric field of the strip electrode 720 is affected to be reduced, and the "on" can be effectively suppressed. Dark lines phenomenon.
  • the pixel unit adopts an active driving mode
  • the thin film transistor 730 functions as an active switching element, and can control whether the strip electrode 720 is connected to the data line D7, thereby controlling the alignment of the liquid crystal molecules.
  • the present invention also provides an array substrate which can be used in a liquid crystal display device.
  • the array substrate includes a glass substrate and the pixel unit of the above embodiment.
  • the pixel unit is disposed on the glass substrate.
  • At least one side of the pad in the pixel unit and the array substrate of the present invention is parallel to the extending direction of the strip electrode, so that the electric field of at least one side of the pad does not affect the electric field of the strip electrode, and the strip electrode can be reduced.
  • the electric field is affected, effectively suppressing the "dark lines" around the pad and improving the display quality.

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Abstract

提供了一种像素单元和阵列基板。像素单元包括：扫描线（G4），沿第一延伸方向（S1）延伸；数据线（D4），沿第二延伸方向（S2）延伸；焊盘（410），电性连接扫描线（G4）和数据线（D4）；绝缘层，覆盖扫描线（G4）和数据线（D4），设有过孔（401）；若干条状电极（420），配置于绝缘层上并沿与第一延伸方向（S1）形成预定角度的第三延伸方向（S3）延伸，通过过孔（401）与焊盘（410）电性连接；焊盘（410）和条状电极（420）透明且导电，焊盘（410）的形状至少一边与第三延伸方向（S3）平行的为多边形，从而能够有效抑制焊盘（410）周围的"暗紋"现象。

Description

像素单元和阵列基板
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种像素单元，还涉及一种阵列基板。
【背景技术】
LCD（Liquid Crystal Display，液晶显示）是目前主流的显示技术。液晶显示装置包括一对基板和夹设于一对基板中的液晶层，两块基板上分别设置有电场发生电极，例如像素电极和公共电极。在两块基板上施加电压，就会在液晶层产生电场，电场的方向决定了液晶分子的排列方向。通过调整电压，使液晶分子的排列方向发生改变，从而入射到液晶层中的光发生偏振，液晶显示装置显示图像。
为了提高液晶显示装置的视角，液晶显示装置中的像素电极通常设计为多个相互平行且间隔的条状电极，这些条状电极又分成若干部分，每个部分的条状电极的延伸方向不同，像素电极就变成“米”型或“《”型结构。例如，请参阅图1，图1是现有技术一种液晶显示装置中单位像素的结构示意图。液晶显示装置具有扫描线G1、数据线D1、焊盘110和若干条状电极120。扫描线G1和数据线D1相互垂直，在交叉处形成焊盘110，焊盘110一般为矩形。扫描线G1和数据线D1通过导线和焊盘110连接。若干条状电极120相互平行且间隔。若干条状电极120与扫描线G1、数据线D1及焊盘110分别处于不同层，不同层之间绝缘。若干条状电极120通过过孔101连接下方的焊盘110。
在现有技术中，只考虑到条状电极120所产生的电场会影响液晶分子的排列，然而，由于焊盘110与条状电极120均采用透明导电材质制成，例如ITO（Indium Tin Oxide，氧化铟锡），因此，在通电时焊盘110也会产生电场，由于焊盘110的边缘与条状电极120的方向交叉，从而焊盘110边缘所产生的电场会影响条状电极120的电场，造成液晶分子排列混乱。请结合参阅图1、图2和图3，图2是图1所示的像素对应的液晶分子的指向示意图。图3是图1所示的像素的光学模拟影像示意图。如图2所示，区域A1和区域A2是焊盘110的边缘对应的区域，从图2可知，除区域A1和区域A2处外，其余区域的液晶分子基本具有一致的排列方向。如图3所示，区域B1对应区域A1，区域B2对应区域A2。黑影C表示的是焊盘110。从图3可知，除区域B1和区域B2外，其余区域的光透过率较高，而受到焊盘110的电场影响，区域B1和区域B2处的光透过率较低，这种现象被称为“暗纹”现象。
【发明内容】
本发明的主要目的是提供一种像素单元和阵列基板，能够降低条状电极的电场受到的影响。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素单元，像素单元包括：扫描线，扫描线沿第一延伸方向延伸；数据线，数据线沿第二延伸方向延伸，第一延伸方向与第二延伸方向相交；焊盘，焊盘形成于扫描线和数据线相交处，焊盘与扫描线和数据线电性连接；绝缘层，绝缘层覆盖扫描线和数据线，绝缘层设有过孔；若干条状电极，若干条状电极相互平行且间隔设置，条状电极配置于绝缘层上并沿第三延伸方向延伸，第三延伸方向与第一延伸方向形成预定角度，若干条状电极通过过孔与焊盘电性连接；其中，焊盘和条状电极均由透明导电材质制成，焊盘的形状为至少一组对边平行的四边形，焊盘的至少一组对边与第三延伸方向平行，过孔的形状为至少一组对边平行的四边形，过孔的至少一组对边与第三延伸方向平行，第一延伸方向与第二延伸方向垂直。
其中，像素单元进一步包括薄膜晶体管，薄膜晶体管位于扫描线和数据线相交处，且薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接焊盘。
其中，预定角度为45度。
其中，透明导电材质为氧化铟锡。
其中，若干条状电极相互间隔的间距相同。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种像素单元，像素单元包括：扫描线，扫描线沿第一延伸方向延伸；数据线，数据线沿第二延伸方向延伸，第一延伸方向与第二延伸方向相交；焊盘，焊盘形成于扫描线和数据线相交处，焊盘与扫描线和数据线电性连接；绝缘层，绝缘层覆盖扫描线和数据线，绝缘层设有过孔；若干条状电极，若干条状电极相互平行且间隔设置，条状电极配置于绝缘层上并沿第三延伸方向延伸，第三延伸方向与第一延伸方向形成预定角度，若干条状电极通过过孔与焊盘电性连接；其中，焊盘和条状电极均由透明导电材质制成，焊盘的形状为多边形，且焊盘的至少一边与第三延伸方向平行。
其中，像素单元进一步包括薄膜晶体管，薄膜晶体管位于扫描线和数据线相交处，且薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接焊盘。
其中，焊盘的形状为至少一组对边平行的四边形，焊盘的至少一组对边与第三延伸方向平行。
其中，过孔的形状为多边形，过孔的至少一边与第三延伸方向平行。
其中，过孔的形状为至少一组对边平行的四边形，过孔的至少一组对边与第三延伸方向平行。
其中，第一延伸方向与第二延伸方向垂直。
其中，预定角度为45度。
其中，透明导电材质为氧化铟锡。
其中，若干条状电极相互间隔的间距相同。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，其中，阵列基板包括玻璃基板和像素单元，像素单元配置于玻璃基板上，其中，像素单元包括：扫描线，扫描线沿第一延伸方向延伸；数据线，数据线沿第二延伸方向延伸，第一延伸方向与第二延伸方向相交；焊盘，焊盘形成于扫描线和数据线相交处，焊盘与扫描线和数据线电性连接；绝缘层，绝缘层覆盖扫描线和数据线，绝缘层设有过孔；若干条状电极，若干条状电极相互平行且间隔设置，条状电极配置于绝缘层上并沿第三延伸方向延伸，第三延伸方向与第一延伸方向形成预定角度，若干条状电极通过过孔与焊盘电性连接；其中，焊盘和条状电极均由透明导电材质制成，焊盘的形状为多边形，且焊盘的至少一边与第三延伸方向平行。
其中，像素单元进一步包括薄膜晶体管，薄膜晶体管位于扫描线和数据线相交处，且薄膜晶体管的栅极电性连接扫描线，源极电性连接数据线，漏极电性连接焊盘。
其中，焊盘的形状为至少一组对边平行的四边形，焊盘的至少一组对边与第三延伸方向平行。
其中，过孔的形状为多边形，过孔的至少一边与第三延伸方向平行。
其中，过孔的形状为至少一组对边平行的四边形，过孔的至少一组对边与第三延伸方向平行。
其中，第一延伸方向与第二延伸方向垂直。
综上所述，本发明的像素单元和阵列基板中焊盘的至少一边与条状电极的延伸方向平行，从而使得焊盘的至少一边的电场不会影响条状电极的电场，能够降低条状电极的电场受到的影响，有效抑制焊盘周围的“暗纹”现象，提升显示质量。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
【附图说明】
图1是现有技术一种液晶显示装置中单位像素的结构示意图；
图2是图1所示的像素对应的液晶分子的指向示意图；
图3是图1所示的像素的光学模拟影像示意图；
图4是本发明像素单元第一实施例的结构示意图；
图5是图4所示的像素单元对应的液晶分子的指向示意图；
图6是图4所示的像素单元的光学模拟影像示意图；
图7是本发明像素单元第二实施例的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，均属于本发明保护的范围。
请参阅图4，图4是本发明像素单元第一实施例的结构示意图。像素单元包括扫描线G4、数据线D4、焊盘410、绝缘层（图未示）以及若干条状电极420。
扫描线G4沿第一延伸方向S1延伸，数据线D4沿第二延伸方向S2延伸。第一延伸方向S1与第二延伸方向S2相交，优选地，第一延伸方向S1与第二延伸方向S2垂直。
焊盘410形成于扫描线G4和数据线D4相交处，焊盘410与扫描线G4和数据线D4电性连接，例如通过导线连接。绝缘层覆盖扫描线G4和数据线D4，并且覆盖焊盘410，绝缘层设有过孔401。
若干条状电极420相互平行且间隔设置，优选地，若干条状电极420相互间隔的间距相同，条状电极420配置于绝缘层上并沿第三延伸方向S3延伸，第三延伸方向S3与第一延伸方向S1形成预定角度，优选地，预定角度为45度，若干条状电极420通过过孔401与焊盘410电性连接，例如通过导线连接。
焊盘410和条状电极420均由透明导电材质制成，优选地，透明导电材质为氧化铟锡。焊盘410的形状为多边形，且焊盘410的至少一边与第三延伸方向S3平行。进一步，焊盘410可以为至少一组对边平行的四边形，焊盘410的至少一组对边与第三延伸方向S3平行。在本实施例中，焊盘410的形状为矩形。在其它实施例中，焊盘410的形状还可以为梯形或菱形。
由于焊盘410的至少一边与第三延伸方向S3平行，则焊盘410在该条边的电场方向与条状电极420的电场方向相同，从而降低焊盘410对条状电极420电场的影响。焊盘410周围的“暗纹”现象就得到有效抑制，显示质量得到提升，
本实施例中条状电极420通过焊盘410与数据线D4连接，因此，该像素单元采用的是无源驱动方式，在扫描线G4和数据线D4上同步输入驱动电压波形的一瞬间，将会在像条状电极420上合成一个驱动波形，从而引导液晶分子排列。
请结合参阅图4、图5和图6，图5是图4所示的像素单元对应的液晶分子的指向示意图，图6是图4所示的像素单元的光学模拟影像示意图。在图5中，区域A'1和区域A'2分别是焊盘410平行第三延伸方向S3的一组对边附近的区域，在这两个区域中，液晶分子的排列方向改变很小，基本与其余区域的液晶分子的排列方向保持一致。在图6中，区域B'1对应区域A'1，区域B'2对应区域A'2，黑影C'表示焊盘410。在这两个区域中，比起其余区域，光透过率并无明显下降，说明“暗纹”现象得到了有效抑制。
请再参阅图4，由于过孔401具有导电性，并且过孔401的边缘和焊盘410的边缘之间需要保证一定距离，因此本实施方式中，过孔401的形状也为多边形，过孔401的至少一边与第三延伸方向S3平行。特别地，过孔401与焊盘410的形状相同，过孔401的形状为至少一组对边平行的四边形，过孔401的至少一组对边与第三延伸方向S3平行。
请参阅图7，图7是本发明像素单元第二实施例的结构示意图。像素单元包括扫描线G7、数据线D7、焊盘710、绝缘层（图未示）、若干条状电极720以及薄膜晶体管730。
扫描线G7沿第一延伸方向S1延伸、数据线D7沿第二延伸方向S2延伸，第一延伸方向S1与第二延伸方向S2相交。
焊盘710形成于扫描线G7和数据线D7相交处，焊盘710与扫描线G7和数据线D7电性连接，例如通过导线连接。绝缘层覆盖扫描线G7和数据线D7，并且覆盖焊盘710，绝缘层设有过孔701。
若干条状电极720相互平行且间隔设置，条状电极720配置于绝缘层上并沿第三延伸方向S3延伸，第三延伸方向S3与第一延伸方向S1形成预定角度。若干条状电极720通过过孔701与焊盘710电性连接。
薄膜晶体管730位于扫描线G7和数据线D7相交处，且薄膜晶体管730的栅极电性连接扫描线G7，源极电性连接数据线D7，漏极电性连接焊盘710。
焊盘710和条状电极720均由透明导电材质制成，焊盘710的形状为多边形，且焊盘710的至少一边与第三延伸方向S3平行。由于焊盘710的至少一边与条状电极720平行，焊盘710在该边附近的电场方向与条状电极720的电场方向相同，因此，条状电极720的电场受到影响降低，能够有效抑制“暗纹”现象。
本实施例与第一实施例的区别在于，像素单元采用的是有源驱动方式，薄膜晶体管730作为有源开关元件，可以控制条状电极720是否与数据线D7连接，从而控制液晶分子排列。
本发明还提供一种阵列基板，该阵列基板可用于液晶显示装置中。阵列基板包括玻璃基板和上述实施例的像素单元。像素单元配置于玻璃基板上。阵列基板的其他结构请参照现有技术，此处不再详述。
通过上述方式，本发明的像素单元和阵列基板中焊盘的至少一边与条状电极的延伸方向平行，从而使得焊盘的至少一边的电场不会影响条状电极的电场，能够降低条状电极的电场受到的影响，有效抑制焊盘周围的“暗纹”现象，提升显示质量。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素单元，其中，所述像素单元包括：
    扫描线，所述扫描线沿第一延伸方向延伸；
    数据线，所述数据线沿第二延伸方向延伸，所述第一延伸方向与所述第二延伸方向相交；
    焊盘，所述焊盘形成于所述扫描线和所述数据线相交处，所述焊盘与所述扫描线和所述数据线电性连接；
    绝缘层，所述绝缘层覆盖所述扫描线和所述数据线，所述绝缘层设有过孔；
    若干条状电极，所述若干条状电极相互平行且间隔设置，所述条状电极配置于所述绝缘层上并沿所述第三延伸方向延伸，所述第三延伸方向与所述第一延伸方向形成预定角度，所述若干条状电极通过所述过孔与所述焊盘电性连接；
    其中，所述焊盘和所述条状电极均由透明导电材质制成，所述焊盘的形状为至少一组对边平行的四边形，所述焊盘的所述至少一组对边与所述第三延伸方向平行，所述过孔的形状为至少一组对边平行的四边形，所述过孔的所述至少一组对边与所述第三延伸方向平行，所述第一延伸方向与所述第二延伸方向垂直。
  2. 根据权利要求1所述的像素单元，其中，所述像素单元进一步包括薄膜晶体管，所述薄膜晶体管位于所述扫描线和所述数据线相交处，且所述薄膜晶体管的栅极电性连接所述扫描线，源极电性连接所述数据线，漏极电性连接所述焊盘。
  3. 根据权利要求1所述的像素单元，其中，所述预定角度为45度。
  4. 根据权利要求1所述的像素单元，其中，所述透明导电材质为氧化铟锡。
  5. 根据权利要求1所述的像素单元，其中，所述若干条状电极相互间隔的间距相同。
  6. 一种像素单元，其中，所述像素单元包括：
    扫描线，所述扫描线沿第一延伸方向延伸；
    数据线，所述数据线沿第二延伸方向延伸，所述第一延伸方向与所述第二延伸方向相交；
    焊盘，所述焊盘形成于所述扫描线和所述数据线相交处，所述焊盘与所述扫描线和所述数据线电性连接；
    绝缘层，所述绝缘层覆盖所述扫描线和所述数据线，所述绝缘层设有过孔；
    若干条状电极，所述若干条状电极相互平行且间隔设置，所述条状电极配置于所述绝缘层上并沿所述第三延伸方向延伸，所述第三延伸方向与所述第一延伸方向形成预定角度，所述若干条状电极通过所述过孔与所述焊盘电性连接；
    其中，所述焊盘和所述条状电极均由透明导电材质制成，所述焊盘的形状为多边形，且所述焊盘的至少一边与所述第三延伸方向平行。
  7. 根据权利要求6所述的像素单元，其中，所述像素单元进一步包括薄膜晶体管，所述薄膜晶体管位于所述扫描线和所述数据线相交处，且所述薄膜晶体管的栅极电性连接所述扫描线，源极电性连接所述数据线，漏极电性连接所述焊盘。
  8. 根据权利要求6所述的像素单元，其中，所述焊盘的形状为至少一组对边平行的四边形，所述焊盘的所述至少一组对边与所述第三延伸方向平行。
  9. 根据权利要求8所述的像素单元，其中，所述过孔的形状为多边形，所述过孔的至少一边与所述第三延伸方向平行。
  10. 根据权利要求9所述的像素单元，其中，所述过孔的形状为至少一组对边平行的四边形，所述过孔的所述至少一组对边与所述第三延伸方向平行。
  11. 根据权利要求6所述的像素单元，其中，所述第一延伸方向与所述第二延伸方向垂直。
  12. 根据权利要求11所述的像素单元，其中，所述预定角度为45度。
  13. 根据权利要求6所述的像素单元，其中，所述透明导电材质为氧化铟锡。
  14. 根据权利要求6所述的像素单元，其中，所述若干条状电极相互间隔的间距相同。
  15. 一种阵列基板，其中，所述阵列基板包括玻璃基板和像素单元，所述像素单元配置于所述玻璃基板上，所述像素单元包括：
    扫描线，所述扫描线沿第一延伸方向延伸；
    数据线，所述数据线沿第二延伸方向延伸，所述第一延伸方向与所述第二延伸方向相交；
    焊盘，所述焊盘形成于所述扫描线和所述数据线相交处，所述焊盘与所述扫描线和所述数据线电性连接；
    绝缘层，所述绝缘层覆盖所述扫描线和所述数据线，所述绝缘层设有过孔；
    若干条状电极，所述若干条状电极相互平行且间隔设置，所述条状电极配置于所述绝缘层上并沿所述第三延伸方向延伸，所述第三延伸方向与所述第一延伸方向形成预定角度，所述若干条状电极通过所述过孔与所述焊盘电性连接；
    其中，所述焊盘和所述条状电极均由透明导电材质制成，所述焊盘的形状为多边形，且所述焊盘的至少一边与所述第三延伸方向平行。
  16. 根据权利要求15所述的阵列基板，其中，所述像素单元进一步包括薄膜晶体管，所述薄膜晶体管位于所述扫描线和所述数据线相交处，且所述薄膜晶体管的栅极电性连接所述扫描线，源极电性连接所述数据线，漏极电性连接所述焊盘。
  17. 根据权利要求15所述的阵列基板，其中，所述焊盘的形状为至少一组对边平行的四边形，所述焊盘的所述至少一组对边与所述第三延伸方向平行。
  18. 根据权利要求17所述的阵列基板，其中，所述过孔的形状为多边形，所述过孔的至少一边与所述第三延伸方向平行。
  19. 根据权利要求18所述的阵列基板，其中，所述过孔的形状为至少一组对边平行的四边形，所述过孔的所述至少一组对边与所述第三延伸方向平行。
  20. 根据权利要求15所述的阵列基板，其中，所述第一延伸方向与所述第二延伸方向垂直。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030117538A1 (en) * 2001-12-20 2003-06-26 Joo-Soo Lim Liquid crystal display device and driving method thereof
CN101086592A (zh) * 2006-06-06 2007-12-12 爱普生映像元器件有限公司 液晶装置及电子设备
CN101089715A (zh) * 1998-02-09 2007-12-19 精工爱普生株式会社 液晶板及电子设备
CN101398575A (zh) * 2007-09-27 2009-04-01 株式会社日立显示器 液晶显示装置
KR20090053610A (ko) * 2007-11-23 2009-05-27 엘지디스플레이 주식회사 횡전계방식 액정표시장치 및 그 제조방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100929675B1 (ko) * 2003-03-24 2009-12-03 삼성전자주식회사 다중 도메인 액정 표시 장치 및 그 박막 트랜지스터 기판
KR101337260B1 (ko) * 2003-08-13 2013-12-05 삼성디스플레이 주식회사 다중 도메인 액정 표시 장치 및 그 박막 트랜지스터 기판
KR20060030577A (ko) * 2004-10-06 2006-04-11 삼성전자주식회사 박막 트랜지스터 표시판
CN101154001B (zh) * 2006-09-27 2011-04-06 奇美电子股份有限公司 薄膜晶体管基板及其应用的液晶显示面板和液晶显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101089715A (zh) * 1998-02-09 2007-12-19 精工爱普生株式会社 液晶板及电子设备
US20030117538A1 (en) * 2001-12-20 2003-06-26 Joo-Soo Lim Liquid crystal display device and driving method thereof
CN101086592A (zh) * 2006-06-06 2007-12-12 爱普生映像元器件有限公司 液晶装置及电子设备
CN101398575A (zh) * 2007-09-27 2009-04-01 株式会社日立显示器 液晶显示装置
KR20090053610A (ko) * 2007-11-23 2009-05-27 엘지디스플레이 주식회사 횡전계방식 액정표시장치 및 그 제조방법

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