WO2014185462A1 - 基板と基板装置及び基板接続方法 - Google Patents
基板と基板装置及び基板接続方法 Download PDFInfo
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- WO2014185462A1 WO2014185462A1 PCT/JP2014/062870 JP2014062870W WO2014185462A1 WO 2014185462 A1 WO2014185462 A1 WO 2014185462A1 JP 2014062870 W JP2014062870 W JP 2014062870W WO 2014185462 A1 WO2014185462 A1 WO 2014185462A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3212—Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
- H04L63/0442—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload wherein the sending and receiving network entities apply asymmetric encryption, i.e. different keys for encryption and decryption
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
- H04L9/3093—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy involving Lattices or polynomial equations, e.g. NTRU scheme
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/24—Key scheduling, i.e. generating round keys or sub-keys for block encryption
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/029—Programmable, customizable or modifiable circuits having a programmable lay-out, i.e. adapted for choosing between a few possibilities
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10037—Printed or non-printed battery
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10212—Programmable component
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention is based on the priority claim of Japanese Patent Application No. 2013-105356 (filed on May 17, 2013), the entire contents of which are incorporated herein by reference. Shall.
- the present invention relates to a substrate, a substrate apparatus, and a substrate connection method, and more particularly to a substrate structure suitable for a substrate on which a stackable semiconductor device is mounted, a substrate apparatus including a plurality of the substrates, and a substrate connection method.
- IC Integrated Circuit
- a battery monitoring IC that can measure multiple battery cells (multi-cell) connected in series with a single IC and monitor each battery cell Have been commercialized.
- This type of IC has a function of stacking a plurality of ICs in series corresponding to the number of battery cells in series (see Non-Patent Document 1).
- the IC stack function corresponds to, for example, a daisy chain connection function for sequentially transferring commands / data to adjacent ICs.
- FIG. 10 schematically illustrates an example of a battery stack monitor IC corresponding to a multi-cell of related technology (see Non-Patent Document 1).
- the IC 10 is connected to a plurality of battery cells (in particular, 12 cells in the example of FIG. 10) that are connected in series.
- Another 12 cells can be connected to the upper side and / or the lower side of the 12 cells.
- a multiplexer (MUX) 11 selects a terminal pair (positive electrode, negative electrode) of one cell, and the voltage of the selected cell is converted into a digital signal by an analog-to-digital converter (ADC) 12. Convert. A digital signal output from the ADC 12 is transferred to a microprocessor (microcomputer) (not shown) or the like via a data bus (DATA) under the control of a register control circuit (REGISTERS AND CONTROL) 13. The command / data transferred from the previous stage IC via the data bus (DATA) is transferred to the subsequent stage IC via the register control circuit 13.
- DATA data bus
- REGISTERS AND CONTROL register control circuit
- a discharge switch (MOSFET (Metal Oxide Semiconductor Field Effect Transistor)) 14 is provided between the positive and negative terminals of the battery cell.
- MOSFET Metal Oxide Semiconductor Field Effect Transistor
- the chip selection input pin (CSBI) of the IC 10 is set to an active state (for example, a low potential) during the period of command data transfer under the control of a microcomputer (not shown). In this transfer period, the command or data is transferred from the previous stage to the next stage in synchronization with the clock signal.
- the IC 10 buffers the chip selection signal input from the chip selection input pin (CSBI) in the IC 10 and outputs the buffered signal from the chip selection output pin (CSBO). Further, the IC 10 buffers the clock signal input from the clock input pin (CKI) in the IC 10 and outputs it from the clock output pin (CKO) to drive the IC at the next stage.
- the positive power supply (V + ) of the IC 10 is connected to, for example, the highest positive potential of the stacked cells (the positive potential of the stacked 12-cell top cell), and the negative power supply (V ⁇ ) is stacked, for example. It is connected to the lowest negative potential of the cell (the negative potential of the bottom cell of 12 cells).
- IC10 of the positive power source (V +) the negative power of the next stage IC - is connected to the negative power of IC10 (V) (V -) is connected to a positive power source of the preceding IC (V +).
- TOS is a setting pin at the top of the stack (for example, the top device (IC) has a high potential and the other devices (IC) in the stack have a low potential).
- the IC 10 can be daisy chain-connected between ICs operating at different power supply potentials by, for example, a configuration in which data is differentially input / output with respect to the data bus (DATA).
- a stackable IC data such as the acquired cell voltage is transmitted to a microcomputer or the like, so the function setting of each stacked IC is required.
- IC function settings for example, there are many ICs that use hardware settings using, for example, IC peripheral circuits.
- the function setting pin of the IC is pulled up to the power supply voltage (VDD) or pulled down to the GND potential (Ground: ground).
- FIG. 7 is a diagram illustrating an example of related technology relating to IC function setting.
- FIG. 7 shows an example in which a plurality of stackable ICs 1 1 to IC 1 3 and a microcomputer 2 are mounted on a substrate (circuit substrate) 3.
- IC1 1 to IC1 3 have the same configuration and are electrically connected (stacked) in series.
- the microcomputer 2 and IC1 3 , IC1 3 and IC1 2 , IC1 2 and IC1 1 are connected by signal line groups 5 3 , 5 2 , and 5 1 , respectively.
- IC1 1 to IC1 3 may be, for example, a battery stack monitor IC similar to that shown in FIG.
- the signal line groups 5 1 , 5 2 , 5 3 receive signals such as the clock, chip selection signal, and data described with reference to FIG. Including.
- IC1 3 master IC to be connected to the microcomputer 2, and the other IC1 1, IC1 2 is a slave IC.
- IC1 3 functioning as the master, IC1 3 setting pins and the power supply voltage to set the functions and (VDD) is connected by a circuit (wiring) 4 3.
- GND and setting pins are connected by circuits (wirings) 4 1 and 4 2 , respectively.
- VDD is a positive power source V + (positive potential of 12 cells stacked)
- GND is a negative power source V ⁇ (stacked) The negative potential of the bottom cell of 12 cells).
- FIG. 7 instead of mounting a plurality of IC1 1 to IC1 3 that can be stacked on one substrate 3, there is a configuration in which stackable ICs are mounted and connected to a plurality of substrates one by one. .
- a plurality of substrates 3 1, 3 2, 3 3, by IC1 1, IC1 2, IC1 3 were respectively mounted, switch 6 1, 6 2, 6 3, IC1 1, IC1 2. Switch the connection of setting pins of IC1 3 .
- FIG. 9 the design of the substrates 3A, 3B, and 3C is changed for each function.
- Patent Document 1 as a cell voltage measurement device that enables accurate measurement of a cell voltage when a plurality of cells are stacked, the voltage of each cell is measured at a cell connection portion of the plurality of stacked cells.
- a cell-side terminal is provided, and the cell-side terminal is connected to a terminal of a ground connection changeover switch in the cell voltage measuring device provided corresponding to the connection portion of the cell. Has been.
- Patent Document 2 discloses a common bus line of each substrate unit with respect to a plurality of substrate units that are attached to a mother board having a common bus line and signal-wired by the common bus line.
- a configuration is disclosed in which a connector is provided at a terminal of the biasing board, a bias board connecting between connectors of two adjacent board units, and a terminal resistor attached to the connector of a single board unit are disclosed.
- the number of cells connected to the IC is limited. If there is a need to reduce the number of cells or add cells, the design of the substrate must be changed.
- the circuit design differs depending on the function of each board, such as the boards 3A to 3C. For this reason, design man-hours and costs increase.
- the present invention has been made in view of the above-described problems, and its purpose is to facilitate the functional setting of a semiconductor device mounted on the substrate, and to reduce setting mistakes and design man-hours. And a substrate connecting method and a substrate connecting method.
- a first terminal for inputting a signal for setting a function of the semiconductor device, a second terminal for supplying a first value, and a second terminal
- a substrate including at least a third terminal for supplying the value of A first connection portion connected to the first to third terminals of the semiconductor device;
- a second connection portion connected to the first connection portion provided on another substrate;
- at least two terminals of the second connection portion are connected to each other via a first connection circuit, and the first connection portion of the substrate is further provided on the second substrate.
- a substrate connected to the connection is provided.
- the semiconductor device of the first substrate includes at least first and second substrates made of the substrate of the viewpoint1.
- Two terminals including a terminal and the second or third terminal include the first connection portion of the first substrate, the second connection portion of the second substrate, and the second connection portion.
- the function of the semiconductor device of the first substrate corresponds to the first value or the second value supplied by the second terminal or the third terminal to which the first terminal is connected.
- a substrate device (electronic device) set to the first function or the second function is provided.
- a first terminal for inputting a signal for setting a function of the semiconductor device, a second terminal for supplying a first value, and a second terminal
- Each of the first to third substrates including at least a third terminal that supplies the value of A first connection portion connected to the first to third terminals of the semiconductor device;
- Embodiment 1 of the present invention It is a figure which shows the example of a connection of Embodiment 1 of this invention. It is a figure which illustrates Embodiment 2 of the present invention. It is a figure which shows the example of a connection of Embodiment 2 of this invention. It is a figure which illustrates Embodiment 3 of this invention. It is a figure which shows the example of a connection of Embodiment 3 of this invention. It is a figure explaining the related technique 1. FIG. It is a figure explaining the related technique 2. FIG. It is a figure explaining the related technique 2. FIG. It is a figure explaining a multicell battery stack monitor IC.
- a first terminal for example, the pin 104 of FIG. 1 or the figure for inputting a signal for setting the function of the semiconductor device (for example, the IC 101 of FIG. 1 or the IC 201 of FIG. 3).
- 3 pin 204 a second terminal for supplying a first value (for example, pin 103 in FIG. 1 or pin 203 in FIG. 3), and a third terminal for supplying a second value (for example, FIG. 1).
- Board 105 or pin 205 in FIG. 3
- a substrate for example, 100 in FIG. 1 or 200 in FIG. 3) having a semiconductor device (IC) that can be connected in series (stacked) is the semiconductor.
- a first connection portion for example, 106 in FIG.
- first connecting portion (106 in FIG. 1 or 207 in FIG. 3) of the substrate (100 in FIG.
- the second connecting portion (107 in FIG. 1 or 200 in FIG. 3) is connected to the second connecting portion (107 in FIG. 1). Or 107 4 in FIG. 2 or 206 in FIG. 3 and the other connection circuit having the same configuration as the first connection circuit (108 in FIG. 1 or 208 in FIG. 3). It is connected to the second connecting portion (107 in FIG. 1, 107 4 in FIG. 2, or 206 in FIG. 3) provided on the substrate.
- the second connecting portion (107 in FIG. 1 or 206 in FIG. 3) of the substrate is connected to another substrate provided with the first connecting portion having the same configuration as the substrate. It is connected to the first connecting portion (106 in FIG. 1 or 207 in FIG. 3).
- the semiconductor device for example, 301 in FIG. 5 is added to the first to third terminals (for example, the pins 306, 305, and 304 in FIG. 5), A fourth terminal (for example, pin 303 in FIG. 5) for inputting a signal for setting the function of the semiconductor device is further included.
- the first connecting portion (for example, 307 in FIG. 5) of the substrate (300 in FIG. 5) is connected to first to third terminals (for example, 306 and 305 in FIG. 5) of the semiconductor device (for example, 301 in FIG. 5). 304).
- the first connection portion for example, 307 in FIG. 5) further includes at least two terminals (for example, 307D and 307F in FIG. 5).
- the at least two terminals (for example, 307D and 307F in FIG. 5) of the first connection part (for example, 307 in FIG. 5) are respectively connected to at least two terminals in the second connection part of another substrate. .
- the substrate (300 in FIG. 5) has a second connection circuit (for example, FIG. 5) that connects the at least two terminals (for example, 307D and 307F in FIG. 5) of the first connection portion (307 in FIG. 5) to each other. 311) may be adopted.
- the second connection portion (for example, 308 in FIG. 5) of the substrate (300 in FIG. 5) is connected to two terminals (for example, FIG. 5) connected to each other by a first connection circuit (for example, 312 in FIG. 5).
- 308A and 308B (for example, 308D, 308E, and 308F in FIG. 5) and second to fourth terminals (301 in FIG. 5) of the semiconductor device (300 in FIG. 5).
- it may be configured to be connected to 305, 304, and 303) in FIG.
- the apparatus includes at least first and second substrates (for example, 100 1 and 100 2 in FIG. 2 or 200 2 and 200 1 in FIG. 4) made of the substrate,
- the first terminal (104 in FIG. 2 or 104 in FIG. 2 ) of the semiconductor device (101 1 in FIG. 2 or 201 2 in FIG. 4) on one substrate (for example, 100 1 in FIG. 2 or 200 2 in FIG. 4). 4) and the second or third terminal (103 or 105 in FIG. 2, 203 or 205 in FIG. 3) are connected to the first substrate (100 1 in FIG. 2). or 106 1 of FIG said first connecting portion 201 2) 4 (FIG. 2 or 207 2 of FIG. 4), the said second substrate (100 2 in FIG.
- the functions of the semiconductor device (101 1 in FIG. 2 or 201 2 in FIG. 4) of the first substrate (100 1 in FIG. 2 or 200 2 in FIG. 4) are connected to each other via the first substrate.
- the control device controls the semiconductor devices of the first and second substrates, wherein the semiconductor devices of the first and second substrates are connected in series.
- a control board (111 in FIG. 2) provided with (for example, the microcomputer 2 in FIG. 2) is provided.
- the control board (111 in FIG. 2) is the first connection portion (for example, 100 3 in FIG. 2) of the first and second boards adjacent to the control board (111 in FIG. 2).
- a second connecting portion (107 4 in FIG. 2) connected to 106 3 ) in FIG. 2 is provided.
- the second connecting portion (107 4 in FIG. 2) of the control board (111 in FIG. 2) is adjacent to the first connecting portion of the board adjacent to the control board (111 in FIG. 2).
- Two terminals comprising the first terminal (104 in FIG. 2) of the semiconductor device on the substrate (100 3 in FIG. 2) and the second or third terminal (103 or 105 in FIG. 2)
- the control board (111 in FIG. 2) is connected, and a connection circuit (third connection circuit) for connecting the two terminals to which the second connection portion (107 4 in FIG. 2) is connected (FIG. 2) 2 108 4 ) may be further provided.
- the semiconductor devices of the first and second substrates are connected in series, and the substrate (at the end of the first and second substrates)
- the configuration may include a third connection portion (212 in FIG. 4) connected to the first connection portion (207 2 in FIG. 4) of 200 1 ) in FIG.
- the third connection portion (212 in FIG. 4) is the first terminal (for example, FIG. 4) of the semiconductor device (for example, 201 1 in FIG. 4) on the substrate (for example, 200 1 in FIG. 4) located at the end portion. 4 of 204) and the second or third terminal (for example, 203 or 205 of FIG. 4), and the two terminals are connected to the third connecting portion (212 of FIG. 4).
- At least first to third substrates are provided (the second and third substrates are the first and second substrates). 1 on both sides of the substrate).
- the first terminal (306 in FIG. 6) of the semiconductor device (301 2 in FIG. 6) of the first substrate (for example, 300 2 in FIG. 6) and the second or third terminal (in FIG. 6) 305 or 304) are connected to the first connecting portion (307 2 in FIG. 6) of the first substrate (300 2 in FIG. 6) and the second substrate (300 3 in FIG. 6).
- the fourth terminal (303 in FIG. 6) of the semiconductor device (301 2 in FIG. 6) of the first substrate (300 2 in FIG. 6) and the second or third terminal (FIG. 6). 305 or 304) are connected to the second connection portion (308 2 in FIG. 6) of the first substrate (300 2 in FIG. 6) and the third substrate (in FIG. 6). 300 1 ) and the second connection circuit (311 1 in FIG. 6) of the third substrate (300 1 in FIG. 6), and the first connection portion (307 1 in FIG. 6). It is good also as a structure made.
- the function of the semiconductor device (301 2 in FIG. 6) of the first substrate (300 2 in FIG. 6) is the same as the function of the first terminal (306 in FIG.
- the first or second value supplied from the second or third terminal to be connected (305 or 304 in FIG. 6) to the first terminal (306 in FIG. 6) and the fourth terminal
- the semiconductor devices (301 2 and 301 3 in FIG. 6) of the first and second substrates are connected in series.
- Control provided with a control device (2 in FIG. 6) connected and controlling the semiconductor devices (301 2 and 301 3 in FIG. 6) of the first and second substrates (300 2 and 300 3 in FIG. 6) It is good also as a structure provided with the board
- Said control board (313 in FIG. 6) is 300 3 of the substrate (FIG. 6 adjacent to the control board (313 in FIG. 6) of the first and second substrate (300 2, 300 3 in FIG. 6) ) Of the second connection portion (308 4 in FIG.
- the second connecting portion (308 4 in FIG. 6) of the control board (313 in FIG. 6) is the first connection of the board (300 3 in FIG. 6) adjacent to the control board (313 in FIG. 6).
- the control board (313 in FIG. 6) connects the two terminals to which the second connection portion (308 4 in FIG. 6) of the control board (313 in FIG. 6) is connected to the control board (313 in FIG. 6).
- the semiconductor devices for example, 301 2 , 301 3, FIG. 6) of the first to third substrates (for example, 300 2 , 300 3, 300 1 of FIG. 6) are provided.
- 301 1 are connected in series, and the second of the substrates (for example, 300 1 in FIG. 6) located at the end of the first to third substrates (300 2 , 300 3 , 300 1 in FIG. 6).
- the third connection portion (315 in FIG. 6) is connected to the fourth terminal (303 in FIG. 6) of the semiconductor device (301 1 in FIG.
- connection circuit (6th connection circuit) (316 of FIG. 6) connected.
- the function of the IC on the board in relation to the board to be connected without changing the peripheral circuit depending on the function of each IC to be stacked. For this reason, the circuit can be shared. As a result, design man-hours and manufacturing costs can be reduced. Further, according to the present invention, the function of the IC can be automatically defined simply by connecting the substrate on which the IC is mounted. This eliminates the need for additional work after connecting the board, reducing the possibility of malfunction due to incorrect settings. Furthermore, according to the present invention, increase / decrease in the number of IC stacks is facilitated. Hereinafter, a description will be given according to some embodiments.
- FIG. 1 is a diagram illustrating the configuration of a substrate according to Embodiment 1 of the present invention.
- FIG. 1 illustrates a substrate (circuit board) in the first embodiment.
- a stackable IC 101 is mounted on a substrate 100.
- a connector 106 (first connection portion) and a connector 107 (second connection portion) are respectively disposed at opposing positions on two opposite sides of the substrate 100.
- the IC 101 includes a master / slave setting pin 104, a VDD (power supply voltage) pin 103, and a GND (Ground) pin 105.
- VDD power supply voltage
- GND Ground
- the GND pin 105, the master / slave setting pin 104, and the VDD pin 103 of the IC 101 are connected to terminals 106A, 106B, and 106C of the connector 106 by wirings 102A, 102B, and 102C on the substrate 100, respectively.
- the terminals 107A and 107B in the connector 107 correspond to the positions of the terminals 106A and 106B of the collector 106 facing each other.
- the terminals 107A and 107B in the connector 107 are connected to each other via a circuit (connection circuit) 108 (wiring) in the substrate 100.
- Reference numeral 107C of the connector 107 indicates a position corresponding to the position of the terminal 106C of the collector 106.
- a terminal such as a pin is provided at the position of 107C in the connector 107, it is not connected (open) to a circuit in the substrate 100, and therefore a terminal such as a pin is not required at the position of 107C (however, it is provided. Also good).
- a receptacle terminal that accommodates a pin connected to the connector 107 may be provided at the position of 107C.
- FIG. 2 is a diagram illustrating an example (substrate device) in which a plurality of the substrates 100 illustrated in FIG. 1 are provided and connected to the control substrate 111.
- substrates 100 1 to 101 3 have the same configuration as the substrate 100 shown in FIG. FIG. 2 discloses a configuration including three control boards 111 and 100, but it goes without saying that the number of boards 100 is not limited to three (see FIG. 4 described later). The same applies to FIG. 6).
- the connector 106 when the stack IC 101 1 and IC 101 2 Connect the substrate 100 1 and the substrate 100 2, the connector 106 first substrate 100 1, the corresponding terminals of the substrate 100 second connector 107 2, connected by a cable 109 1.
- three terminals of the substrate 100 1 of connector 106 1 (106A ⁇ 106C in FIG. 1), in three cables 109 1, three terminals (Fig substrate 100 second connector 107 2 1 107A to 107C).
- one terminal of the connector 107 2 (107C in FIG. 1), may be disconnected from the corresponding one of the terminals of the connector 106 1 (106C in FIG. 1).
- IC 101 1 of the functions of the substrate 100 1 is set to be a slave.
- IC 101 2 function of the substrate 100 2 is set to be a slave.
- Control board 111 is provided with IC 101 1 ⁇ IC 101 3 on the substrate 100 1-101 3 communicates via a line 110 1-110 3, transmission of the command, the microcomputer 2 to control the collection of data .
- the control board 111, the side facing the adjacent substrates 100 3, corresponding to the connector 106 3 of the substrate 100 3, connector 107 4 are provided. Two terminals of the connector 107 4 is connected through the circuit in the control board 111 (connected circuit) 108 4 (wiring).
- Connector 107 4 terminal connection of the control board 111 includes a IC 101 3 of the master slave setting pin 104 of the substrate 100 3, VDD pin 103, the substrate 100 3 of the connector 106 3, the cable 109 3, connector 107 4 of the control board 111 , via a circuit 108 4 in the control board 111, and is configured to connect to each other.
- the connector 107 4 provided on the control board 111, the terminal position 107C of the connector 107 in FIG. 1, 107B and terminal, and corresponds to the structure connected by the circuit 108 (108 4).
- the control board 111 on which the microcomputer 2 for controlling the ICs 101 1 to IC 101 3 is mounted has a different configuration from the boards 100 1 to 100 3 , but the connector 107 4 and the circuit 108 4 are connected to the connector 107 of the board 100 in FIG. This corresponds to the circuit 108.
- a connector 106 3 of the substrate 100 3 by connecting the connector 107 4 of the control board 111, the function of 3 IC 101 disposed on the substrate 100 3 is set to the master (ability to connect directly to the microcomputer 2).
- the connector of the mating terminals of the adjacent connectors 107 1 which is located opposite the side to the side opposite the substrate 100 2 is connected does not exist, both of which are open.
- the connection between the boards is not limited to the cable 109. You may use the card edge connector etc. which connect between board
- the connector 106 may be provided with a through pin, and the through pin may be fitted to the receptacle of the connector 107.
- the receptacles 107A to 107C of the connector 107 are provided corresponding to the pins of the connectors 106A to 106C of the connector 106 of the other board to be connected.
- the connection form between the boards is not limited to the connection using the connector, and is not limited to the presence or absence of the connector.
- the function setting of the IC 101 (setting of the master function and the slave function) is automatically performed according to the connection of the board. For this reason, according to the embodiment, it is not necessary to change the circuit according to the function of the IC, change the switch, or the like, and the design man-hours and costs can be reduced.
- the number of IC stacks can be changed by simply increasing or decreasing the number of substrates to be connected.
- the IC is a battery monitor IC
- the number of cells (batteries) connected in series to be monitored can be varied (can be made scalable).
- FIG. 3 is a diagram illustrating a substrate (circuit board) 200 according to the second embodiment.
- a stackable IC 201 is mounted on a substrate 200, and a connector 206 and a connector 207 are respectively connected to opposing positions on two opposite sides of the substrate 200.
- the IC 201 includes a top setting pin 204, a VDD pin 203, and a GND pin 205.
- the top setting pin 204 is connected to the VDD pin 203
- the function of the IC 201 is set to the top.
- the top setting pin 204 is connected to the GND pin 205
- the function of the IC 201 is set to non-top.
- the top is a function set to an IC farthest from the microcomputer side (for example, when a multi-cell battery monitor IC is connected in three stages, it corresponds to an IC that monitors the multi-cell with the highest potential). Since it is the last stage and there is no subsequent IC, there is no need to transfer the data transferred from the microcomputer side to the subsequent stage.
- the VDD pin 203, the top setting pin 204, and the GND pin 205 of the IC 201 are connected to the terminals 207A, 207B, and 207C of the connector 207 via the wirings 202A, 202B, and 202C of the substrate 200, respectively.
- the terminals 206B and 206C of the connector 206 at positions opposite to the terminals 207B and 207C of the connector 207 are connected via a circuit (connection circuit) 208 in the substrate 200. Even if a terminal is provided at the position of 206A of the connector 206, it is not connected to the circuit in the board 200, so that the connector terminal is unnecessary.
- a receptacle that accommodates a pin to be connected may be provided at the position of 206A.
- FIG. 4 is a diagram illustrating an example (a board device) of a connection configuration of a plurality of boards 200 1 to 200 3 (same as the board 200 of FIG. 3), the termination connector 212, and the control board 211.
- the substrates 200 1 to 200 3 are the same as the substrate 200 shown in FIG.
- the substrate 200 1 and the substrate 200 2 by connecting the substrate 200 1 and the substrate 200 2, to stack the IC 201 1 and IC 201 2, corresponding to terminals of the substrate 200 1 of connector 206 1 and the substrate 200 second connector 207 2, for example, connected by a cable 209 1.
- the top set pin 204 and the GND pin 205 of IC 201 2 is, the wiring 202 2, the connector 207 2, cable 209 1, the connector 206 first substrate 200 1, through the circuit 208 1 of the substrate 200 1 Is done.
- IC 201 2 function of the substrate 200 2 is set to non-top.
- three terminals of the substrate 200 1 of connector 206 1 (206A ⁇ 206C in FIG. 3) is, in three cables 209 1, the three substrates 200 second connector 207 two terminals (in FIG. 3 207A to 207C).
- one terminal of the connector 206 1 (206A in FIG. 3) and the connector 207 2 of a corresponding one of terminals (207A in FIG. 3) may be disconnected.
- top set pin 204 and the GND pin 205 of the substrate 200 3 of IC 201 3 is the wiring 202 3 and the connector 207 3, cable 209 2, the connector 206 and second substrate 200 2 are connected via a circuit 208 the second substrate 200 in 2. Therefore, IC 201 3 function of the substrate 200 3 is set to non-top.
- the connector 2071 of the substrate 200 1, when connecting end connector 212, top set pin 204 and the VDD pin 203 of IC 201 1 is, wiring 202 1, the connector 207 1, termination connector 212, circuit 213 (wiring) Connected through.
- IC 201 1 of the functions of the substrate 200 1 is set to the top.
- the connection between the boards is not limited to the cable 209. Further, the connection between the substrates is not limited to the connection using the connector.
- the top function of the IC mounted on the board is automatically set according to the board to be connected and the terminal connector.
- the number of IC stacks can be changed simply by increasing or decreasing the number of substrates to be connected.
- the IC is a battery monitor IC
- the number of cells (batteries) connected in series to be monitored can be varied (can be made scalable).
- FIG. 5 is a diagram illustrating a substrate (circuit board) 300 according to the third embodiment.
- the IC 301 is mounted on the substrate 300, and the connector 307 and the connector 308 are connected to the opposing positions on the two sides facing the substrate 300, respectively.
- the IC 301 includes a master / slave setting pin 306, a top setting pin 303, a VDD pin 304, and a GND pin 305.
- the master / slave setting pin 306 is connected to the VDD pin 304, the function of the IC 301 is set to the master, and when it is connected to the GND pin 305, it is set to the slave.
- the connectors 307 and 308 have five terminals. In the connectors 307 and 308, even if terminals such as pins are provided at the positions of 307E and 308C, they are not connected. Therefore, terminals such as connector pins are not required at these positions. However, when either of the connectors 307 and 308 is provided with a receptacle, a receptacle that accommodates a pin to be connected may be provided at a position of 307E or 308C.
- the master / slave setting pin 306, the GND pin 305, and the VDD pin 304 of the IC 301 are connected to terminals 307A, 307B, and 307C of the connector 307 through wirings 310A, 310B, and 310C, respectively.
- Terminals 307D and 307F of the connector 307 are connected via a circuit (connection circuit) 311 (wiring) in the substrate 300.
- the top setting pin 303, the VDD pin 304, and the GND pin 305 of the IC 301 are connected to the pins 308D, 308E, and 308F of the connector 308 through wirings 309D, 309E, and 309F, respectively.
- the pins 308A and 308B of the connector 308 are connected via a circuit 312 (wiring) in the substrate 300.
- FIG. 6 illustrates an example of a connection configuration (substrate device) of a plurality of substrates 300 1 to 300 3 (same as the substrate 300 of FIG. 5), the control substrate 313, and the termination connector 315.
- the stacking IC 301 1 and IC 301 2 Connect the substrate 300 1 and the substrate 300 2 connects the opposing connector 307 1 and the connector 308 2 cable. Connection in this case, the master slave setting pin 306 and the GND pin 305 of IC 301 1 on the substrate 3001, a wiring 310 1, the connector 307 1, the connector 308 2, circuit 312 2 (wiring) of the substrate 300 in 2 over the Is done.
- IC 301 1 of the functions of the substrate 300 1 is set to be a slave.
- six terminals of the substrate 300 1 of connector 307 1 (307A-306F of FIG. 5) is, at six cables, 308A of the substrate 300 second connector 308 2 six terminals (FIGS. 5 to 308F).
- one terminal of the connector 307 1 (307C in FIG. 5) and the connector 308 2 of a corresponding one of terminals (308C in FIG. 5) may be disconnected.
- IC 301 1 of the functions of the substrate 300 1 is set to the top.
- IC 301 2 function of the substrate 300 2 is set to non-top.
- IC 301 3 function of the substrate 300 3 is set to the master.
- IC 301 3 function of the substrate 300 3 is set to non-top.
- cables are connected between the connectors on the boards, but it is needless to say that the connections between the boards are not limited to cable connections. Further, the connection between the substrates is not limited to the connection using the connector.
- the master slave function and the top function of the IC mounted on the board are automatically set simultaneously according to the board to be connected and the termination connector.
- the number of IC stacks can be changed simply by increasing or decreasing the number of substrates to be connected. For example, when the IC is a battery monitor IC, the number of cells (batteries) connected in series to be monitored can be varied (can be made scalable).
- the IC described in each of the above embodiments is suitable for application to a multi-cell compatible battery stack monitor IC, and can also be applied to function setting of any IC that can be connected in a stack.
- (Appendix 1) At least a first terminal that inputs a signal for setting a function of the semiconductor device, a second terminal that supplies a first value, and a third terminal that supplies a second value, and supports serial connection
- a substrate provided with a semiconductor device A first connection portion connected to the first to third terminals of the semiconductor device;
- a second connection portion connected to the first connection portion provided on another substrate;
- At least two terminals of the second connection portion are connected to each other via a first connection circuit;
- the substrate, wherein the first connection portion of the substrate is connected to the second connection portion provided on another substrate.
- the semiconductor device further includes a fourth terminal for inputting a signal for setting a function of the semiconductor device;
- the first connection portion of the substrate is connected to the first to third terminals of the semiconductor device, and is further connected to at least two terminals of the second connection portion of another substrate, respectively.
- Has two terminals, The at least two terminals of the first connection portion are connected to each other via a second connection circuit;
- the second connection portion of the substrate is a terminal different from the at least two terminals connected to each other, and is connected to the second to fourth terminals of the semiconductor device of the substrate. Board.
- Appendix 3 Comprising at least first and second substrates made of the substrate according to appendix 1.
- Two terminals consisting of the first terminal of the semiconductor device on the first substrate and one of the second terminal or the third terminal are connected to the first connection of the first substrate.
- Part, and the second connection part and the first connection circuit of the second substrate are connected to each other,
- the function of the semiconductor device of the first substrate is supplied from the second terminal or the third terminal connected to the first terminal with respect to the first terminal of the semiconductor device.
- the semiconductor devices of the first and second substrates are connected in series;
- a control board comprising a control device for controlling the semiconductor devices of the first and second substrates;
- the control board is Of the first and second substrates, a second connection portion connected to the first connection portion of the substrate adjacent to the control substrate,
- the board device according to appendix 3 wherein at least two terminals of the second connection portion are connected to each other via a third connection circuit on the control board.
- the semiconductor devices of the first and second substrates are connected in series; A third connecting portion connected to the first connecting portion of the substrate located at an end of the first and second substrates; The third connection portion is configured to connect two terminals including the first terminal of the semiconductor device of the substrate located at the end portion and one of the second terminal and the third terminal to each other.
- Appendix 6 Comprising at least first to third substrates made of the substrate according to appendix 2, Two terminals comprising the first terminal of the semiconductor device on the first substrate and one of the second terminal or the third terminal are connected to the first connection of the second substrate. Connected to each other via the second connection portion of the second substrate and the first connection circuit of the second substrate, Two terminals of the fourth terminal of the semiconductor device of the first substrate and one of the second terminal or the third terminal are the second connection portion of the third substrate.
- the function of the semiconductor device of the first substrate is The first value or the second value supplied from the second terminal or the third terminal connected to the first terminal with respect to the first terminal of the semiconductor device; The first value or the second value supplied from the second terminal or the third terminal connected to the fourth terminal with respect to the fourth terminal of the semiconductor device; Substrate device set to a function corresponding to the combination of
- the semiconductor devices of the first and second substrates are connected in series;
- a control board comprising a control device for controlling the semiconductor devices of the first and second substrates;
- the control board is A second connection portion connected to the first connection portion of the substrate on the adjacent control substrate of the first and second substrates;
- the second connection part of the control board is connected to the first connection part of a board adjacent to the control board;
- the semiconductor devices of the first to third substrates are connected in series; A third connecting portion connected to the first connecting portion of the substrate located at an end of the first to third substrates; The third connecting portion is A sixth connection circuit configured to connect two terminals including the fourth terminal of the semiconductor device on the substrate located at the end portion and one of the second terminal and the third terminal to each other;
- the substrate apparatus according to appendix 6 or 7.
- a first connection portion connected to the first to third terminals of the semiconductor device Providing a second connecting portion connected to the first connecting portion of another substrate, connecting at least two terminals of the second connecting portion to each other on the substrate side; Connecting the first connection portion of the first substrate to the second connection portion of the second substrate; A substrate connection method, wherein the second connection portion of the first substrate is connected to the first connection portion of the third substrate.
- the semiconductor device further includes a fourth terminal for inputting a signal for setting a function of the semiconductor device;
- the first connection portion of the substrate is connected to the first to third terminals of the semiconductor device, and is further connected to at least two terminals of the second connection portion of another substrate, respectively.
- Has two terminals, The at least two terminals of the first connection portion are connected to each other via a second connection circuit; Item 11.
- the second connection portion of the substrate is a terminal different from the at least two terminals connected to each other, and is connected to the second to fourth terminals of the semiconductor device of the substrate. Board connection method.
- the semiconductor devices of the first and second substrates are connected in series;
- a control board comprising a control device for controlling the semiconductor devices of the first and second substrates;
- the control board is Of the first and second substrates, a second connection portion connected to the first connection portion of the substrate adjacent to the control substrate,
- the board connection method according to appendix 12 wherein at least two terminals of the second connection portion are connected to each other via a third connection circuit on the control board.
- the semiconductor devices of the first and second substrates are connected in series; A third connecting portion connected to the first connecting portion of the substrate located at an end of the first and second substrates; The third connection portion is configured to connect two terminals including the first terminal of the semiconductor device of the substrate located at the end portion and one of the second terminal and the third terminal to each other.
- Two terminals comprising the first terminal of the semiconductor device on the first substrate and one of the second terminal or the third terminal are connected to the first connection of the second substrate. Connected to each other via the second connection portion of the second substrate and the first connection circuit of the second substrate, Two terminals of the fourth terminal of the semiconductor device of the first substrate and one of the second terminal or the third terminal are the second connection portion of the third substrate.
- the function of the semiconductor device of the first substrate is The first value or the second value supplied from the second terminal or the third terminal connected to the first terminal with respect to the first terminal of the semiconductor device; The first value or the second value supplied from the second terminal or the third terminal connected to the fourth terminal with respect to the fourth terminal of the semiconductor device;
- the semiconductor devices of the first and second substrates are connected in series;
- a control board comprising a control device for controlling the semiconductor devices of the first and second substrates;
- the control board is A second connection portion connected to the first connection portion of the substrate on the adjacent control substrate of the first and second substrates;
- the second connection part of the control board is connected to the first connection part of a board adjacent to the control board;
- the semiconductor devices of the first to third substrates are connected in series; A third connecting portion connected to the first connecting portion of the substrate located at an end of the first to third substrates; The third connecting portion is A sixth connection circuit configured to connect two terminals including the fourth terminal of the semiconductor device on the substrate located at the end portion and one of the second terminal and the third terminal to each other; Furthermore, the board
Abstract
Description
本発明は、日本国特許出願:特願2013-105356号(2013年05月17日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、基板及び基板装置と基板接続方法に関し、特に、スタック可能な半導体デバイスを搭載した基板に好適な基板構造と、該基板を複数備えた基板装置と、基板の接続方法に関する。
前記半導体装置の前記第1乃至第3の端子に接続される第1の接続部と、
他の基板に設けられた前記第1の接続部に接続される第2の接続部と、
を備え、前記第2の接続部の少なくとも二つの端子は第1の接続回路を介して互いに接続され、前記基板の前記第1の接続部は、さらに別の基板に設けられた前記第2の接続部と接続される基板が提供される。
前記第1の基板の前記半導体装置の機能が、前記第1の端子が接続する前記第2の端子又は前記第3の端子が供給する前記第1の値又は前記第2の値に対応する第1の機能又は第2の機能に設定される、基板装置(電子装置)が提供される。
前記半導体装置の前記第1乃至第3の端子に接続される第1の接続部と、
他の基板の前記第1の接続部に接続される第2の接続部を設け、前記第2の接続部の少なくとも二つの端子を前記基板側で互いに接続し、
前記第1の基板の前記第1の接続部を、前記第2の基板の前記第2の接続部と接続し、
前記第1の基板の前記第2の接続部を、前記第3の基板の前記第1の接続部と接続する基板接続方法が提供される。
図1は、本発明の実施形態1の基板の構成を例示する図である。図1には、実施形態1における基板(回路基板)が例示されている。図1を参照すると、基板100上にスタック可能なIC101が実装されている。基板100の対向する2辺の相対する位置に、コネクタ106(第1の接続部)と、コネクタ107(第2の接続部)がそれぞれ配設されている。IC101は、マスタスレーブ設定ピン104、VDD(電源電圧)ピン103、GND(Ground)ピン105を有する。マスタスレーブ設定ピン104をVDDピン103に接続した場合、IC101の機能は、マスタに設定される。一方、マスタスレーブ設定ピン104をGNDピン105に接続した場合、IC101の機能はスレーブに設定される。
次に、本発明の実施形態2について説明する。図3は、実施形態2の基板(回路基板)200を例示する図である。図3を参照すると、基板200上に、スタック可能なIC201が実装され、基板200の対向する2辺の相対する位置に、コネクタ206、コネクタ207がそれぞれ接続されている。IC201は、トップ設定ピン204、VDDピン203、GNDピン205を備えている。トップ設定ピン204をVDDピン203に接続すると、IC201の機能はトップに設定される。トップ設定ピン204をGNDピン205に接続すると、IC201の機能は、非トップに設定される。なお、トップは、マイコン側から最も遠い位置のIC(例えばマルチセルバッテリモニタICを3段接続した場合、最も高電位のマルチセルをモニタするICに対応)に設定される機能であり、デイジーチェーン接続の最後段であり、後段のICがないため、マイコン側から転送されたデータの後段への転送は行わなくてよい。
次に、本発明の実施形態3について説明する。図5は、実施形態3の基板(回路基板)300を例示する図である。図5を参照すると、基板300上にIC301が実装され、基板300に対向する2辺の相対する位置に、それぞれコネクタ307、コネクタ308が接続されている。IC301は、マスタスレーブ設定ピン306、トップ設定ピン303、VDDピン304、GNDピン305を備えている。マスタスレーブ設定ピン306をVDDピン304に接続した場合、IC301の機能はマスタに設定され、GNDピン305に接続された場合、スレーブに設定される。IC301のトップ設定ピン303をVDDピン304に接続した場合、IC301の機能はトップに設定され、トップ設定ピン303をGNDピン305に接続した場合、非トップに設定される。コネクタ307、308は5つの端子を備えている。コネクタ307、308において、307E、308Cの位置にピン等の端子を設けても、非接続であるため、この位置にコネクタピン等の端子は不要である。ただし、コネクタ307、308のいずれかがレセプタクルを備えたものである場合、接続するピンを収容するレセプタクルを、307E又は308Cの位置に備えてもよい。
半導体装置の機能を設定する信号を入力する第1の端子と、第1の値を供給する第2の端子と、第2の値を供給する第3の端子とを少なくとも含み、直列接続に対応した半導体装置を備えた基板であって、
前記半導体装置の前記第1乃至第3の端子に接続される第1の接続部と、
他の基板に設けられた前記第1の接続部に接続される第2の接続部と、
を備え、
前記第2の接続部の少なくとも二つの端子は第1の接続回路を介して互いに接続され、
前記基板の前記第1の接続部は、さらに別の基板に設けられた前記第2の接続部と接続される、基板。
前記半導体装置が、前記半導体装置の機能を設定する信号を入力する第4の端子をさらに含み、
前記基板の前記第1の接続部は、前記半導体装置の前記第1乃至第3の端子に接続され、さらに、他の基板の前記第2の接続部の少なくとも二つの端子にそれぞれ接続される少なくとも二つの端子を有し、
前記第1の接続部の前記少なくとも二つの端子は第2の接続回路を介して互いに接続され、
前記基板の前記第2の接続部は、互いに接続される前記少なくとも二つの端子とは別の端子で、前記基板の前記半導体装置の前記第2乃至第4の端子に接続される、付記1記載の基板。
付記1記載の基板からなる第1及び第2の基板を少なくとも備え、
前記第1の基板の前記半導体装置の前記第1の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子が、前記第1の基板の前記第1の接続部と、前記第2の基板の前記第2の接続部及び前記第1の接続回路と、を介して、互いに接続され、
前記第1の基板の前記半導体装置の機能が、前記半導体装置の前記第1の端子に対して、前記第1の端子が接続する前記第2の端子又は前記第3の端子から供給される前記第1の値又は前記第2の値に対応する機能に設定される、基板装置。
前記第1及び第2の基板の前記半導体装置が直列に接続され、
前記第1及び第2の基板の前記半導体装置を制御する制御装置を備えた制御基板を備え、
前記制御基板は、
前記第1及び第2の基板のうち、前記制御基板に隣接する基板の前記第1の接続部に接続する第2の接続部を備え、
前記第2の接続部の少なくとも二つの端子は、前記制御基板上の第3の接続回路を介して互いに接続される、付記3記載の基板装置。
前記第1及び第2の基板の前記半導体装置が直列に接続され、
前記第1及び第2の基板のうち端部に位置する基板の前記第1の接続部に対して接続される第3の接続部を備え、
前記第3の接続部は、前記端部に位置する前記基板の前記半導体装置の前記第1の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子を互いに接続する第4の接続回路を備えた、付記3記載の基板装置。
付記2記載の基板からなる第1乃至第3の基板を少なくとも備え、
前記第1の基板の前記半導体装置の前記第1の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子が、前記第2の基板の前記第1の接続部、前記第2の基板の前記第2の接続部、さらに前記第2の基板の前記第1の接続回路を介して互いに接続され、
前記第1の基板の前記半導体装置の前記第4の端子と、前記第2の端子又は前記第3の端子の一方と、の二つの端子が、前記第3の基板の前記第2の接続部、前記第3の基板の前記第1の接続部、さらに前記第3の基板の前記第2の接続回路を介して互いに接続され、
前記第1の基板の前記半導体装置の機能が、
前記半導体装置の前記第1の端子に対して、前記第1の端子が接続する前記第2の端子又は前記第3の端子から、供給される前記第1の値又は前記第2の値と、
前記半導体装置の前記第4の端子に対して、前記第4の端子が接続する前記第2の端子又は前記第3の端子から、供給される前記第1の値又は前記第2の値と、
の組み合せに対応する機能に設定される、基板装置。
前記第1及び第2の基板の前記半導体装置が直列に接続され、
前記第1及び第2の基板の前記半導体装置を制御する制御装置を備えた制御基板を備え、
前記制御基板は、
前記第1及び第2の基板のうち隣接する前記制御基板に基板の前記第1の接続部に接続する第2の接続部を備え、
前記制御基板の前記第2の接続部は、前記制御基板に隣接する基板の前記第1の接続部に接続され、
前記制御基板の前記第2の接続部の少なくとも二つの端子は前記制御基板の第5の接続回路を介して互いに接続される、付記6記載の基板装置。
前記第1乃至第3の基板の前記半導体装置が直列に接続され、
前記第1乃至第3の基板のうち端部に位置する基板の前記第1の接続部に対して接続される第3の接続部を備え、
前記第3の接続部は、
前記端部に位置する基板の前記半導体装置の前記第4の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子を互いに接続する第6の接続回路を備えた、付記6又は7記載の基板装置。
前記各基板の前記第1及び第2の接続部が、前記基板の相対する二つの辺にそれぞれ設けられている、付記3乃至8のいずれか1に記載の基板装置。
半導体装置の機能を設定する信号を入力する第1の端子と、第1の値を供給する第2の端子と、第2の値を供給する第3の端子とを少なくとも含み、直列接続に対応した半導体装置を備えた第1乃至第3の基板の各々に、
前記半導体装置の前記第1乃至第3の端子に接続される第1の接続部と、
他の基板の前記第1の接続部に接続される第2の接続部を設け、前記第2の接続部の少なくとも二つの端子を前記基板側で互いに接続し、
前記第1の基板の前記第1の接続部を、前記第2の基板の前記第2の接続部と接続し、
前記第1の基板の前記第2の接続部を、前記第3の基板の前記第1の接続部と接続する、基板接続方法。
前記半導体装置が、前記半導体装置の機能を設定する信号を入力する第4の端子をさらに含み、
前記基板の前記第1の接続部は、前記半導体装置の前記第1乃至第3の端子に接続され、さらに、他の基板の前記第2の接続部の少なくとも二つの端子にそれぞれ接続される少なくとも二つの端子を有し、
前記第1の接続部の前記少なくとも二つの端子は第2の接続回路を介して互いに接続され、
前記基板の前記第2の接続部は、互いに接続される前記少なくとも二つの端子とは別の端子で、前記基板の前記半導体装置の前記第2乃至第4の端子に接続される、付記10記載の基板接続方法。
前記第1の基板の前記半導体装置の前記第1の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子が、前記第1の基板の前記第1の接続部と、前記第2の基板の前記第2の接続部及び前記第1の接続回路と、を介して、互いに接続され、
前記第1の基板の前記半導体装置の機能が、前記半導体装置の前記第1の端子に対して、前記第1の端子が接続する前記第2の端子又は前記第3の端子から供給される前記第1の値又は前記第2の値に対応する機能に設定される、付記10記載の基板接続方法。
前記第1及び第2の基板の前記半導体装置が直列に接続され、
前記第1及び第2の基板の前記半導体装置を制御する制御装置を備えた制御基板を備え、
前記制御基板は、
前記第1及び第2の基板のうち、前記制御基板に隣接する基板の前記第1の接続部に接続する第2の接続部を備え、
前記第2の接続部の少なくとも二つの端子は、前記制御基板上の第3の接続回路を介して互いに接続される、付記12記載の基板接続方法。
前記第1及び第2の基板の前記半導体装置が直列に接続され、
前記第1及び第2の基板のうち端部に位置する基板の前記第1の接続部に対して接続される第3の接続部を備え、
前記第3の接続部は、前記端部に位置する前記基板の前記半導体装置の前記第1の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子を互いに接続する第4の接続回路を備えた、付記12記載の基板接続方法。
前記第1の基板の前記半導体装置の前記第1の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子が、前記第2の基板の前記第1の接続部、前記第2の基板の前記第2の接続部、さらに前記第2の基板の前記第1の接続回路を介して互いに接続され、
前記第1の基板の前記半導体装置の前記第4の端子と、前記第2の端子又は前記第3の端子の一方と、の二つの端子が、前記第3の基板の前記第2の接続部、前記第3の基板の前記第1の接続部、さらに前記第3の基板の前記第2の接続回路を介して互いに接続され、
前記第1の基板の前記半導体装置の機能が、
前記半導体装置の前記第1の端子に対して、前記第1の端子が接続する前記第2の端子又は前記第3の端子から、供給される前記第1の値又は前記第2の値と、
前記半導体装置の前記第4の端子に対して、前記第4の端子が接続する前記第2の端子又は前記第3の端子から、供給される前記第1の値又は前記第2の値と、
の組み合せに対応する機能に設定される、付記11記載の基板接続方法。
前記第1及び第2の基板の前記半導体装置が直列に接続され、
前記第1及び第2の基板の前記半導体装置を制御する制御装置を備えた制御基板を備え、
前記制御基板は、
前記第1及び第2の基板のうち隣接する前記制御基板に基板の前記第1の接続部に接続する第2の接続部を備え、
前記制御基板の前記第2の接続部は、前記制御基板に隣接する基板の前記第1の接続部に接続され、
前記制御基板の前記第2の接続部の少なくとも二つの端子は前記制御基板の第5の接続回路を介して互いに接続される、付記15記載の基板接続方法。
前記第1乃至第3の基板の前記半導体装置が直列に接続され、
前記第1乃至第3の基板のうち端部に位置する基板の前記第1の接続部に対して接続される第3の接続部を備え、
前記第3の接続部は、
前記端部に位置する基板の前記半導体装置の前記第4の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子を互いに接続する第6の接続回路を備えた、付記15又は16記載の基板接続方法。
前記各基板の前記第1及び第2の接続部が、前記基板の相対する二つの辺にそれぞれ設けられている、付記12乃至17のいずれか1に記載の基板接続方法。
2 マイコン
3、31~34、3A~3C 基板
41~43 配線
51~53 信号線(バス)
61~63 スイッチ
11 マルチプレクサ(MUX)
12 アナログデジタル変換器(ADC)
13 レジスタ制御回路
14 放電スイッチ(MOSFET)
100、1001~1003、200、2001~2003、300、3001~3003 基板
1021~1023、102A、102B、102C、2021~2023、202A、202B、202C、3091~3093、309D、309E、309F、3101~3103、310A、310B、310C 配線
103、203、304 VDDピン
104、306 マスタスレーブ設定ピン
105、205、305 GNDピン
106、1061~1063、107、1071~1074、206、2061~2063 、207、2071~2073、307、3071~3073、308、3081~3084 コネクタ
106A~106C、107A~107C、206A~206C、207A~207C、307A~307F、308A~308F コネクタ端子
108、1081~1084、208、2081~2083、311、3111~3113、312、3121~3124 回路(配線)
1091~1093、2091~2092 ケーブル
1101~1103、2101~2103、3141~3143 信号線
111、211、313 制御基板
204、303 トップ設定ピン
212、315 終端用コネクタ
213、316 回路(接続回路)
Claims (10)
- 半導体装置の機能を設定する信号を入力する第1の端子と、第1の値を供給する第2の端子と、第2の値を供給する第3の端子とを少なくとも含み、直列接続に対応した半導体装置を備えた基板であって、
前記半導体装置の前記第1乃至第3の端子に接続される第1の接続部と、
他の基板に設けられた前記第1の接続部に接続される第2の接続部と、
を備え、
前記第2の接続部の少なくとも二つの端子は第1の接続回路を介して互いに接続され、
前記基板の前記第1の接続部は、さらに別の基板に設けられた前記第2の接続部と接続される、基板。 - 前記半導体装置が、前記半導体装置の機能を設定する信号を入力する第4の端子をさらに含み、
前記基板の前記第1の接続部は、前記半導体装置の前記第1乃至第3の端子に接続され、さらに、他の基板の前記第2の接続部の少なくとも二つの端子にそれぞれ接続される少なくとも二つの端子を有し、
前記第1の接続部の前記少なくとも二つの端子は第2の接続回路を介して互いに接続され、
前記基板の前記第2の接続部は、互いに接続される前記少なくとも二つの端子とは別の端子で、前記基板の前記半導体装置の前記第2乃至第4の端子に接続される、請求項1記載の基板。 - 請求項1記載の基板からなる第1及び第2の基板を少なくとも備え、
前記第1の基板の前記半導体装置の前記第1の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子が、前記第1の基板の前記第1の接続部と、前記第2の基板の前記第2の接続部及び前記第1の接続回路と、を介して、互いに接続され、
前記第1の基板の前記半導体装置の機能が、前記半導体装置の前記第1の端子に対して、前記第1の端子が接続する前記第2の端子又は前記第3の端子から供給される前記第1の値又は前記第2の値に対応する機能に設定される、基板装置。 - 前記第1及び第2の基板の前記半導体装置が直列に接続され、
前記第1及び第2の基板の前記半導体装置を制御する制御装置を備えた制御基板を備え、
前記制御基板は、
前記第1及び第2の基板のうち、前記制御基板に隣接する基板の前記第1の接続部に接続する第2の接続部を備え、
前記第2の接続部の少なくとも二つの端子は、前記制御基板上の第3の接続回路を介して互いに接続される、請求項3記載の基板装置。 - 前記第1及び第2の基板の前記半導体装置が直列に接続され、
前記第1及び第2の基板のうち端部に位置する基板の前記第1の接続部に対して接続される第3の接続部を備え、
前記第3の接続部は、前記端部に位置する前記基板の前記半導体装置の前記第1の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子を互いに接続する第4の接続回路を備えた、請求項3記載の基板装置。 - 請求項2記載の基板からなる第1乃至第3の基板を少なくとも備え、
前記第1の基板の前記半導体装置の前記第1の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子が、前記第2の基板の前記第1の接続部、前記第2の基板の前記第2の接続部、さらに前記第2の基板の前記第1の接続回路を介して互いに接続され、
前記第1の基板の前記半導体装置の前記第4の端子と、前記第2の端子又は前記第3の端子の一方と、の二つの端子が、前記第3の基板の前記第2の接続部、前記第3の基板の前記第1の接続部、さらに前記第3の基板の前記第2の接続回路を介して互いに接続され、
前記第1の基板の前記半導体装置の機能が、
前記半導体装置の前記第1の端子に対して、前記第1の端子が接続する前記第2の端子又は前記第3の端子から、供給される前記第1の値又は前記第2の値と、
前記半導体装置の前記第4の端子に対して、前記第4の端子が接続する前記第2の端子又は前記第3の端子から、供給される前記第1の値又は前記第2の値と、
の組み合せに対応する機能に設定される、基板装置。 - 前記第1及び第2の基板の前記半導体装置が直列に接続され、
前記第1及び第2の基板の前記半導体装置を制御する制御装置を備えた制御基板を備え、
前記制御基板は、
前記第1及び第2の基板のうち隣接する前記制御基板に基板の前記第1の接続部に接続する第2の接続部を備え、
前記制御基板の前記第2の接続部は、前記制御基板に隣接する基板の前記第1の接続部に接続され、
前記制御基板の前記第2の接続部の少なくとも二つの端子は前記制御基板の第5の接続回路を介して互いに接続される、請求項6記載の基板装置。 - 前記第1乃至第3の基板の前記半導体装置が直列に接続され、
前記第1乃至第3の基板のうち端部に位置する基板の前記第1の接続部に対して接続される第3の接続部を備え、
前記第3の接続部は、
前記端部に位置する基板の前記半導体装置の前記第4の端子と、前記第2の端子又は前記第3の端子の一方と、からなる二つの端子を互いに接続する第6の接続回路を備えた、請求項6又は7記載の基板装置。 - 前記各基板の前記第1及び第2の接続部が、前記基板の相対する二つの辺にそれぞれ設けられている、請求項3乃至8のいずれか1項に記載の基板装置。
- 半導体装置の機能を設定する信号を入力する第1の端子と、第1の値を供給する第2の端子と、第2の値を供給する第3の端子とを少なくとも含み、直列接続に対応した半導体装置を備えた第1乃至第3の基板の各々に、
前記半導体装置の前記第1乃至第3の端子に接続される第1の接続部と、
他の基板の前記第1の接続部に接続される第2の接続部を設け、前記第2の接続部の少なくとも二つの端子を前記基板側で互いに接続し、
前記第1の基板の前記第1の接続部を、前記第2の基板の前記第2の接続部と接続し、
前記第1の基板の前記第2の接続部を、前記第3の基板の前記第1の接続部と接続する、基板接続方法。
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Also Published As
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JP6299756B2 (ja) | 2018-03-28 |
US20160282923A1 (en) | 2016-09-29 |
US9910478B2 (en) | 2018-03-06 |
US9619000B2 (en) | 2017-04-11 |
US20160080333A1 (en) | 2016-03-17 |
JPWO2014185462A1 (ja) | 2017-02-23 |
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