WO2014176876A1 - 显示面板及其制作方法、液晶显示器 - Google Patents

显示面板及其制作方法、液晶显示器 Download PDF

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Publication number
WO2014176876A1
WO2014176876A1 PCT/CN2013/085497 CN2013085497W WO2014176876A1 WO 2014176876 A1 WO2014176876 A1 WO 2014176876A1 CN 2013085497 W CN2013085497 W CN 2013085497W WO 2014176876 A1 WO2014176876 A1 WO 2014176876A1
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Prior art keywords
gate
line
layer
opening
trace
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English (en)
French (fr)
Inventor
徐向阳
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13456—Cell terminals located on one side of the display only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • Embodiments of the present invention relate to a display panel, a method of fabricating the same, and a liquid crystal display. Background technique
  • a thin film transistor liquid crystal display is a liquid crystal display device driven by a semiconductor device.
  • TFT-LCD can be classified into a twisted nematic type, a vertical alignment type, an in-plane switching (IPS) type, and a fringe field conversion (FFS) type.
  • IPS in-plane switching
  • FFS fringe field conversion
  • the panel charges and discharges the pixel capacitance by progressive scanning, thereby deflecting the liquid crystal to control the light field of the backlight.
  • the scan signal and the drive voltage are generated by the gate integrated circuit and the driver integrated circuit, respectively.
  • the control signal of the gate integrated circuit is generated by a Timing Controller chip and transmitted to the gate integrated circuit via a panel Layout Gate.
  • a single layer of metal traces is used for the peripheral traces of the TFT-LCD array substrate.
  • the signal delay of the line has no effect on the display due to the lower frequency.
  • the frequency of the signal is also increasing.
  • the delay and attenuation of the signal in the line cannot be ignored.
  • There are two main reasons for the delay of the line on the one hand, the signal trace resistance of the line; on the other hand, the coupling capacitance of the line.
  • the coupling capacitance is generated between the different metal lines on the reverse side; and the resistance is determined by the characteristics of the metal trace itself, mainly depending on the resistivity, cross section and wiring length of the metal trace.
  • Common wiring metal materials include: aluminum, molybdenum, copper, indium tin oxide (ITO), and the like. In terms of electrical conductivity, copper is the best but the highest cost, and the process is the most difficult.
  • Embodiments of the present invention provide a display panel, a manufacturing method thereof, and a liquid crystal display, which are used for The resistance of the traces on the periphery of the low gate line reduces signal attenuation and delay, improving display performance.
  • An embodiment of the present invention provides a display panel including a gate line peripheral trace region provided with a gate line peripheral trace, wherein the gate line peripheral trace includes a first trace sequentially formed on the base substrate a gate insulating layer and a second trace; the gate insulating layer includes at least one first opening, and the first trace and the second trace are electrically connected through the first opening.
  • Another embodiment of the present invention provides a liquid crystal display including the display panel.
  • a further embodiment of the present invention provides a method for fabricating a display panel, the display panel including a display area and a gate line peripheral routing area, and the manufacturing method includes: on a base substrate in a peripheral line area of the gate line Forming a first trace for the gate line peripheral traces, a gate insulating layer and a second trace; the gate insulating layer includes at least one first opening, the first trace and the second trace The wires are electrically connected through the first opening.
  • FIG. 1 is a schematic diagram of an array of anti-peripheral circuits of a liquid crystal display panel
  • FIG. 2 is a schematic diagram of a peripheral trace of a gate line according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a peripheral trace of a gate line according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of processing and forming of a mask provided by a specific embodiment of the present invention.
  • 100 electrostatic ring short circuit; 101: gate line; 102: terminal area; 103: common electrode; 104: electrostatic ring; 105: pixel drive chip; 106: gate integrated circuit; 107: data line; 108: gate line Peripheral routing; 109: Display area.
  • Embodiments of the present invention provide a display panel and a method for fabricating the same, and a liquid crystal display for reducing resistance of a peripheral trace of a gate line, reducing signal attenuation and delay, and improving display performance.
  • the display panel includes a display area 109 at the center and a peripheral area outside the display area 109.
  • the display area 109 includes a plurality of gate lines 101, a plurality of data lines 107, and a plurality of pixel units defined by the intersection of the gate lines 101 and the data lines 107.
  • each pixel unit includes a thin film transistor (TFT) as a switching element, and a gate of the thin film transistor is electrically connected or integrally formed with a corresponding gate line, and a source of the thin film transistor is electrically connected or integrally formed with a corresponding data line, and the thin film
  • the drain of the transistor is electrically connected or integrally formed with the corresponding pixel electrode.
  • the peripheral area includes the peripheral line of the gate line where the gate line outer trace 108 is located, and other areas in the vicinity (e.g., the terminal area 102, etc.).
  • the gate integrated circuit 106 is for applying a gate scan signal to the gate lines in the display area 109.
  • the liquid crystal panel may further include other components or structures such as the electrostatic ring short circuit 100, the terminal region 102, the common electrode 103, the electrostatic ring 104, and the pixel driving chip 105.
  • An embodiment of the present invention provides a structure of a gate line peripheral trace of a display panel, wherein a gate line peripheral trace of the liquid crystal panel includes a first trace sequentially formed on a base substrate for a peripheral trace of the gate line, a gate insulating layer and a second trace; the gate insulating layer includes at least one first opening, and the first trace and the second trace are electrically connected through the first opening. At least one first opening in the gate insulating layer is exposed to a first trace under the gate insulating layer to enable the first and second traces to Electrically connected to each other, thereby reducing the overall resistance of the outer traces of the gate lines.
  • the intermediate layer of the active layer in the peripheral trace area of the gate line is etched and removed during the fabrication process, or, for example, there are The intermediate layers of the source layer are all removed, for example by etching.
  • the intermediate layer may be, for example, an interlayer insulating layer separating the pixel electrode layer and the source/drain metal layer.
  • the first trace may be formed simultaneously with the gate line, and the second trace may be formed simultaneously with the source drain electrode or the pixel electrode.
  • the first opening also passes through the intermediate layer to expose the first trace under the intermediate layer.
  • the total length of the first opening may be greater than one-half of the length of the outer trace of the gate line, that is, more than half of the outer traces of the gate line are exposed.
  • sufficient contact is required between the first trace and the second trace, and the larger the contact area of the two, the lower the overall resistance of the resulting trace of the peripheral trace of the gate line.
  • the first opening may be formed in the peripheral wiring area of the entire gate line, thereby exposing the entire peripheral line of the gate line; or the first opening may be formed continuously or at intervals only in the peripheral line area of the partial gate line, that is, The first opening may not be limited to one.
  • the peripheral trace of the gate line may be at least two points. One of the regions is formed such that the first trace and the second trace can be electrically connected directly.
  • the display panel gate line peripheral trace region may further include an insulating protective layer formed on the base substrate and a third trace above the insulating protective layer.
  • the third trace may be formed simultaneously with the pixel electrode formed on the insulating protective layer, and at this time, the second trace is formed, for example, simultaneously with the source and drain electrodes.
  • At least one second opening may be formed in the insulating protective layer, and the third trace and the second trace are electrically connected through the second opening.
  • the second opening is exposed to a second trace below the insulating protective layer. If the three conductive layers of the first trace, the second trace, and the third trace are electrically connected to each other, the obtained trace of the peripheral trace of the gate line is better, and the overall resistance is lower.
  • the total length of the second opening may be greater than one-half of the length of the outer trace of the gate line. Similar to the first opening, in order to maintain good electrical conductivity, sufficient contact is required between the second trace and the third trace.
  • the second opening may also be not limited to one.
  • a liquid crystal display provided by an embodiment of the present invention includes the display panel; a gate line peripheral trace of the display panel connects the timing control chip and the gate integrated circuit.
  • Another embodiment of the present invention provides a method of fabricating a display panel, which can be performed as follows:
  • the base substrate is, for example, a glass substrate, and the outer peripheral wiring region of the gate line is formed on the outer side of the display region, for example, on both sides or all four sides of the rectangular substrate.
  • the above embodiment has been described by taking a bottom gate type display panel as an example, but the present invention is not limited thereto.
  • the first trace needs to be directly electrically connected to the second trace. Therefore, in the peripheral wiring region of the gate line, the gate insulating layer and the active layer between the first trace and the second trace need to be etched away to form the first opening of the first trace exposed
  • the gate insulating layer and the active layer at other positions in the peripheral region of the gate line can be removed or etched as needed.
  • forming a gate insulating layer and an active layer in sequence in step S202 and forming at least one first opening in a peripheral line region of the gate line includes: forming a gate insulating layer and a gate in a peripheral region of the gate line Forming a first opening in the pole insulating layer; forming an active layer and removing the active layer or all active layers at the first opening in a peripheral wiring region of the gate line. That is, in the latter case, the gate insulating layer near the peripheral wiring region of the gate line is left, and the entire active layer of the gate wiring peripheral wiring region and its vicinity is etched away.
  • forming a gate insulating layer and an active layer in sequence in step S202 and forming at least one first opening in a peripheral wiring region of the gate line includes: forming a gate insulating layer; forming an active layer and surrounding the gate line The wiring region forms at least one first opening; the gate insulating layer and the active layer corresponding to the first opening are both removed by etching, for example.
  • Etching the gate insulating layer and the active layer may include simultaneously etching away all of the gate insulating layer and the active layer of the gate wiring peripheral region and the vicinity thereof, or simultaneously etching away the gate wiring in the peripheral routing region a gate insulating layer and an active layer.
  • step S203 may be: forming a pixel electrode layer on the active layer, and then forming a second trace at at least the first opening in the peripheral trace region of the gate line, where The second trace is electrically connected to the first trace through the first opening.
  • the source and drain electrodes may be formed before or after the pixel electrode, and the two may be in direct contact, or an insulating layer may be formed therebetween and electrically connected to each other through via holes in the insulating layer.
  • the method of the above embodiment using the source/drain metal layer to form the second trace can also continue as follows:
  • the pixel electrode is formed over the insulating protective layer, and is electrically connected to one of the source and drain electrodes through a via hole in the insulating protective layer.
  • step S204 after forming an insulating protective layer on the source/drain metal layer, at least one second opening is formed in the insulating protective layer in the peripheral wiring region of the gate line to expose the second trace below;
  • a third trace is formed at the second opening of the peripheral wiring region of the gate line.
  • the two wires of the first wire and the second wire may be used to transmit signals, or the first wire, the second wire, and the third wire may be used. Transmission signal.
  • the metal layers are in contact with each other, which can increase the cross-sectional area of the metal layer and reduce the trace resistance at the periphery of the gate line.
  • the total length of the second opening may be greater than one-half of the length of the outer trace of the gate line.
  • 2 is a schematic diagram of a gate line peripheral trace of one embodiment of the present invention, and only the gate line peripheral trace shown in the figure includes three traces (wires) parallel to each other, but the present invention is not limited thereto.
  • 3 is a cross-sectional view of a trace of FIG.
  • the structure of the trace comprising: a glass substrate 200 as a base substrate; a first walk formed on the glass substrate 200 a wire 201; a gate insulating layer 202 formed on the glass substrate 200, the gate insulating layer 202 having a first opening 310 to expose the first trace 201; and a second trace 203 passing through the first opening 310 and the first
  • the wiring 201 is electrically connected; an insulating protective layer 204 is formed on the second trace 203, the insulating protective layer 204 has a second opening 320 to expose the second trace 203; and a third formed on the insulating protective layer 204
  • the trace 205 is electrically connected to the second trace 203 through the second opening 320.
  • the gate line peripheral traces in this example include three layers of traces electrically connected to each other, and the active layer is completely removed in the gate line peripheral traces.
  • each layer pattern includes, but is not limited to, the form of FIG. 3.
  • Each layer may also be patterned (eg, etched) into other graphic patterns, and only needs to ensure that the three layers of metal can be sufficiently contacted to form an electrical connection. .
  • each layer of the peripheral line area of the gate line corresponds to the following steps in the production process of the display panel:
  • FIG. 4 a schematic diagram of the processing of the masks corresponding to steps 1-2 and 4-5 is performed.
  • Another embodiment of the present invention provides a method of fabricating a display panel, which can be performed as follows:
  • a gate insulating layer on the source/drain metal layer forming a gate insulating layer on the source/drain metal layer, forming a first opening in the gate insulating layer of the peripheral portion of the gate line, the first opening exposing at least a portion of the first trace;
  • a gate metal layer on the gate insulating layer thereby forming a gate and a gate line in the display region, and forming a second trace in the peripheral trace region of the gate line, the second trace passing through the first opening
  • the first trace is electrically connected.
  • the base substrate is, for example, a glass substrate, and the outer peripheral wiring region of the gate line is formed on the outer side of the display region, for example, on both sides or all four sides of the rectangular substrate.
  • the above embodiment has been described by taking a top gate type display panel as an example, but the present invention is not limited thereto.
  • the method of the embodiment of the present invention can etch all the active layer of the gate line and the active layer in the vicinity of the gate line when the active layer is patterned, and the same active process as that of the conventional display panel can be used.
  • Layer mask For example, the patterning of the active layer is performed between the patterning of the gate insulating layer and the source/drain metal layer. If the peripheral wiring region of the gate line only removes the active layer at the first opening, the active layer mask used is different from that used in the process of fabricating the conventional display panel, and remains in the periphery of the gate line in the corresponding patterning process. The active layer in the trace area.
  • the first opening is formed by changing the gate insulating layer to form the first opening therein and the second opening is formed therein by changing the insulating protective layer mask, and the first to the second opening are connected through the first and second openings
  • the three-layer metal traces are used to obtain the peripheral traces of the gate lines, thereby achieving the purpose of reducing the trace resistance of the gate lines.
  • the embodiments of the present invention provide a display panel, a method for fabricating the same, and a liquid crystal display device, which can reduce the resistance of the peripheral lines of the gate line, reduce signal attenuation and delay, and improve the display effect.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种显示面板包括设置有栅线外围走线的栅线外围走线区，栅线外围走线包括依次形成于基板上的第一走线（201）、栅线绝缘层（202）和第二走线（203）；栅线绝缘层（202）存在至少一个第一开口（310），第一走线（201）与第二走线（203）通过第一开口（310）电连接。显示面板可降低栅线外围走线的电阻，减小信号衰减与延迟，提高显示效果。

Description

显示面板及其制作方法、 液晶显示器 技术领域
本发明的实施例涉及一种显示面板及其制作方法、 液晶显示器。 背景技术
薄膜晶体管液晶显示器（TFT-LCD )是一种由半导体器件驱动的液晶显 示装置。 根据面板驱动电场的不同， TFT-LCD可分为扭曲向列型、 垂直排列 型、 面内转换（IPS )型和边缘场转换（FFS )型等。 虽然所形成的驱动液晶 的电场的形式不同， 但是面板都是通过逐行扫描的方式对像素电容进行充放 电， 进而使液晶偏转来控制背光源的光场。 扫描信号和驱动电压分别由栅极 集成电路和驱动集成电路产生。 栅极集成电路的控制信号由时序控制 (Timing Controller)芯片产生后，经面板栅线外围走线 （Peripheral Layout Gate) 传输至栅极集成电路。
目前 TFT-LCD阵列基板的外围走线多釆用单层金属走线。 对于低分辨 率与低帧刷新速率的面板来说， 由于频率较低， 所以线路的信号延迟对显示 的效果不会产生影响。 随着人们对显示器分辨率的要求不断提高， 信号的频 率也在不断提高， 对于高帧刷新速率的面板来说， 信号在线路中的延迟和衰 减不能不考虑。 线路的延迟主要有两方面原因产生： 一方面是线路的信号走 线电阻； 另一方面是线路的耦合电容。 耦合电容是在 反上的不同金属线之 间产生的； 而电阻则是由于金属走线本身的特性决定， 主要取决于金属走线 的电阻率、 横截面与布线长度。 目前常见的布线金属材料包括： 铝、 钼、铜、 铟锡金属氧化物 （Indium Tin Oxide, ITO)等。 就导电性而言， 铜最好但成本 也是最高， 工艺难度还最大。
因此， 对于高分辨率与高帧速率刷新的面板而言， 栅线外围走线的电阻 增加了信号的衰减与延迟， 降低了显示效果。 发明内容
本发明实施例提供了一种显示面板及其制作方法、 液晶显示器， 用于降 低栅线外围走线的电阻， 减小信号衰减与延迟， 提高显示效果。
本发明的一个实施例提供了一种显示面板， 包括设置有栅线外围走线的 栅线外围走线区， 其中， 所述栅线外围走线包括依次形成于基底基板上的第 一走线、 栅极绝缘层和第二走线； 所述栅极绝缘层包括至少一个第一开口， 所述第一走线与所述第二走线通过该第一开口电连接。
本发明的另一个实施例提供了一种液晶显示器包括所述显示面板。
本发明的再一个实施例提供了一种显示面板的制作方法， 该显示面板包 括显示区和栅线外围走线区， 该制作方法包括： 在基底基板上在所述栅线外 围走线区中依次形成用于栅线外围走线的第一走线、栅极绝缘层和第二走线； 所述栅极绝缘层包括至少一个第一开口， 所述第一走线与所述第二走线通过 该第一开口电连接。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍， 显而易见地， 这些附图仅仅涉及本发明的一些实施例， 而非对 本发明的限制。
图 1为液晶显示面板的阵列^反外围电路示意图；
图 2为本发明实施例提供的栅线外围走线示意图；
图 3为本发明具体实施例提供的栅线外围走线具体结构示意图； 图 4为本发明具体实施例提供的掩模板的处理成形示意图。
附图标记：
100: 静电环短接线路； 101 : 栅线； 102: 端子区； 103: 公共电极； 104: 静电环； 105: 像素驱动芯片； 106: 栅极集成电路； 107: 数据线; 108: 栅线外围走线； 109: 显示区。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。本公开中使用的 "第一"、 "第 二" 以及类似的词语并不表示任何顺序、 数量或者重要性， 而只是用来区分 不同的组成部分。 同样， "一个" 、 "一" 或者 "该" 等类似词语也不表示 数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类似的词语意 指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及 其等同， 而不排除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语 并非限定于物理的或者机械的连接， 而是可以包括电性的连接， 不管是直接 的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关 系， 当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明的实施例提供了一种显示面板及其制作方法、 液晶显示器， 用于 降低栅线外围走线的电阻， 减小信号衰减与延迟， 提高显示效果。
图 1是一种液晶显示面板（例如 TFT-LCD面板） 的阵列基板外围电路 示意图。 栅线外围走线 108 的主要作用是将控制信号传输到栅极集成电路 106。 该显示面板包括位于中部的显示区 109和在显示区 109外的周边区域。 显示区 109包括多条栅线 101、 多条数据线 107和由这些栅线 101和数据线 107相交叉而界定的多个像素单元。 例如， 每个像素单元包括作为开关元件 的薄膜晶体管（TFT ) , 薄膜晶体管的栅极与相应的栅线电连接或一体形成， 薄膜晶体管的源极与相应的数据线电连接或一体形成， 薄膜晶体管的漏极与 相应的像素电极电连接或一体形成。 周边区域包括栅线外围走线 108所在的 栅线外围走线区以及附近的其他区域（例如端子区 102等） 。 栅极集成电路 106用于对显示区 109中的栅线施加栅扫描信号。 此外， 该液晶面板还可以 包括静电环短接线路 100、 端子区 102、 公共电极 103、 静电环 104以及像素 驱动芯片 105等其他部件或结构。
本发明的一个实施例提供了一种显示面板的栅线外围走线的结构， 该液 晶面板的栅线外围走线包括依次形成于基底基板上用于栅线外围走线的第一 走线、 栅极绝缘层和第二走线； 所述栅极绝缘层包括至少一个第一开口， 所 述第一走线与所述第二走线通过该第一开口电连接。 栅极绝缘层中的至少一 个第一开口暴露在栅极绝缘层下方的第一走线从而使得第一和第二走线能够 彼此电连接， 从而降低栅线外围走线的整体电阻。
由于栅线外围走线仅作导线使用， 因此在制作过程中栅线外围走线区中 的例如有源层的中间层被刻蚀而去除， 或者， 在制作过程中将显示区域以外 的例如有源层的中间层全部例如通过刻蚀而去除。 除有源层外， 该中间层还 可以为例如将像素电极层和源漏金属层隔开的层间绝缘层。
例如， 第一走线可以与栅线同时形成， 第二走线可以与源漏电极或像素 电极同时形成。 当第二走线与像素电极同时形成且像素电极形成在中间层上 时， 则第一开口还穿过该中间层以暴露在该中间层下的第一走线。
例如， 所述第一开口总的长度可以大于栅线外围走线长度的二分之一， 即将超过一半的栅线外围走线暴露。 为保持良好的导电性能， 第一走线和第 二走线之间需要有充分的接触， 二者的接触面积越大则所得到的栅线外围走 线的整体电阻越低。 可以在整个栅线外围走线区中形成第一开口， 由此将整 条栅线外围走线都暴露； 也可以仅在部分栅线外围走线区中连续或间隔地形 成第一开口， 即第一开口可以不限于一个。 当仅在部分栅线外围走线区中形 成第一开口时， 或者制作过程中部分栅线外围走线区中的栅极绝缘层未刻蚀 完全时， 栅线外围走线可以在至少二分之一的区域内形成以使得第一走线和 第二走线能够直接电连接。
例如， 该显示面板栅线外围走线区还可以包括形成在基底基板上的绝缘 保护层和在绝缘保护层上方的第三走线。 第三走线可以与形成在该绝缘保护 层上的像素电极同时形成， 而此时第二走线例如与源漏电极同时形成。
例如， 该绝缘保护层中可以形成有至少一个第二开口， 所述第三走线与 所述第二走线通过该第二开口电连接。 该第二开口暴露在该绝缘保护层下方 的第二走线。如果第一走线、第二走线和第三走线这三个导电层彼此电连接， 可使得所得到的栅线外围走线的导电性更好， 其整体电阻更低。
例如， 所述第二开口的总长度可以大于栅线外围走线长度的二分之一。 与第一开口类似， 为保持良好的导电性能， 第二走线和第三走线之间需要有 充分的接触。 第二开口也可以不限于一个。
例如， 在垂直于显示面板的基底基板（例如玻璃基板） 的方向上， 第一 开口和第二开口可以处于同一位置； 即第二开口位于第一开口的上方。但是， 并不要求第一开口和第二开口一定具有相同的外形。 本发明的一个实施例提供的一种液晶显示器包括所述显示面板； 所述显 示面板的栅线外围走线将时序控制芯片和栅极集成电路连接。
本发明的另一个实施例提供的一种显示面板的制作方法， 该方法可如下 进行：
S201、 在基底 反上的显示区中形成栅线和栅极， 同时在栅线外围走线 区中形成第一走线；
5202、 依次形成栅极绝缘层和有源层， 并且在栅线外围走线区中形成至 少一个第一开口以暴露第一走线；
5203、 在有源层上形成源漏金属层， 同时在栅线外围走线区中至少第一 开口处形成第二走线， 其中所述第二走线通过所述第一开口与所述第一走线 电连接。
该基底基板例如为玻璃基板， 栅线外围走线区形成在显示区域的外侧， 例如矩形基板的彼此相对的两侧或全部四侧。 上述实施例以底栅型显示面板 为例进行了说明， 但本发明不限于此。
本实施例中， 第一走线需要与第二走线能够直接电连接。 因此， 在栅线 外围走线区中， 位于第一走线和第二走线之间的栅极绝缘层和有源层需要被 刻蚀掉以形成暴露在下的第一走线的第一开口； 在栅线外围走线区中其他位 置的栅极绝缘层和有源层，可根据需要既可以通过刻蚀以去除，也可以保留。
在一个示例中， 步骤 S202 中依次形成栅极绝缘层和有源层并且在栅线 外围走线区形成至少一个第一开口包括： 形成栅极绝缘层并且在栅线外围走 线区中的栅极绝缘层中形成第一开口； 形成有源层并且在栅线外围走线区中 去除该第一开口处的有源层或全部有源层。 也就是说， 在后一种情况， 保留 栅线外围走线区附近的栅极绝缘层 , 而刻蚀掉栅线外围走线区及其附近的全 部有源层。
在一个示例中， 步骤 S202 中依次形成栅极绝缘层和有源层并且在栅线 外围走线区形成至少一个第一开口， 包括： 形成栅极绝缘层； 形成有源层并 且在栅线外围走线区形成至少一个第一开口； 对应于第一开口的栅极绝缘层 和有源层均例如被刻蚀而去除。 刻蚀栅极绝缘层和有源层可包括同时刻蚀掉 栅线外围走线区及其附近的全部的栅极绝缘层和有源层， 或者同时刻蚀掉栅 线外围走线区中的栅极绝缘层和有源层。 此外， 也可以使用灰阶掩模板的方 式， 通过同一灰阶掩才莫板连续进行两次刻蚀， 可以在刻蚀掉显示区域以外的 有源层的同时， 保留栅线外围走线区中第一开口附近的栅极绝缘层。
例如， 所述第一开口的总长度可以大于栅线外围走线长度的二分之一。 当通过像素电极层形成第二走线时， 则步骤 S203 可以为： 在有源层上 形成像素电极层， 然后在栅线外围走线区中至少第一开口处形成第二走线， 其中所述第二走线通过所述第一开口与所述第一走线电连接。 在该示例中， 源漏电极可以在像素电极之前或之后形成， 二者可以直接接触， 或在二者之 间形成有绝缘层且通过绝缘层中的过孔彼此电连接。
上述使用源漏金属层形成第二走线的实施例的方法还可以继续如下进 行：
5204、 在源漏金属层上形成绝缘保护层；
5205、 在绝缘保护层上形成像素电极层。
此时， 像素电极形成在绝缘保护层之上， 且通过绝缘保护层中的过孔与 源漏电极之一电连接。 在一个示例中， 步骤 S204 中， 在源漏金属层上形成 绝缘保护层后， 在栅线外围走线区中在绝缘保护层中形成至少一个第二开口 以暴露在下方的第二走线； 在绝缘保护层上形成像素电极层时， 在栅线外围 走线区的第二开口处形成第三走线。
因此， 在本发明的实施例中， 既可以使用第一走线和第二走线这两层金 属传输信号， 也可以使用第一走线、 第二走线和第三走线这三层金属传输信 号。 金属层之间互相接触， 能够增大金属层横截面积， 降低栅线外围走线电 阻。
例如， 所述第二开口的总长度可以大于栅线外围走线长度的二分之一。 图 2是本发明一个实施例的栅线外围走线的示意图， 图中仅示出的栅线 外围走线包括三根彼此平行的走线（导线） ， 但是本发明不限于此。 图 3示 出了一个示例中图 2中一根走线沿图中 AA，方向的截面图， 该走线的结构包 括： 作为基底基板的玻璃基板 200; 形成在玻璃基板 200上的第一走线 201 ; 形成在玻璃基板 200上的栅极绝缘层 202, 该栅极绝缘层 202中具有第一开 口 310以暴露第一走线 201 ; 第二走线 203 , 通过第一开口 310与第一走线 201电连接； 形成在第二走线 203之上的绝缘保护层 204, 该绝缘保护层 204 中具有第二开口 320以暴露第二走线 203; 形成在绝缘保护层 204上的第三 走线 205 , 通过该第二开口 320与第二走线 203电连接。 该示例中的栅线外 围走线包括三层彼此电连接的走线， 而且在栅线外围走线中有源层完全被去 除。
本发明的实施例中， 各层图形包括但不限于图 3的形式， 各层也可以被 构图 （例如刻蚀）为其它的图形样式， 只需要保证三层金属能够充分接触形 成电连接即可。
对于以上图 3所示的示例， 栅线外围走线区各层在显示面板的制作流程 中分别对应如下步骤：
1、在基底基板上形成栅极金属膜，然后将栅极金属膜构图以在显示区中 形成栅线、 薄膜晶体管的栅电极， 在栅线外围走线区中形成第一走线 201 ;
2、 形成栅极绝缘膜， 然后构图以在栅线外围走线区中形成栅极绝缘层 202中的第一开口 310, 该第一开口 310暴露至少部分第一走线 201 ;
3、形成有源层薄膜，然后将该有源层薄膜构图以在显示区中形成薄膜晶 体管的有源层并且将栅线外围走线区中的有源层薄膜去除， 暴露第一开口 310和第一走线 201 ;
4、形成源漏金属膜，然后将该源漏金属膜构图以在显示区中形成薄膜晶 体管的源漏电极和数据线， 在栅线外围走线区中形成第二走线 203 , 该第二 走线 203通过第一开口 310与第一走线 201电连接；
5、形成绝缘保护膜，然后将该绝缘保护膜构图以在显示区中在源漏电极 之一的上方形成像素电极过孔， 在栅线外围走线区中形成绝缘保护层 204中 第二开口 320, 该第二开口 320暴露至少部分第二走线 203;
6、形成像素电极膜，然后将该像素电极膜构图以在显示区中形成像素电 极， 在栅线外围走线区中形成第三走线 205, 像素电极通过像素电极过孔与 源漏电极之一电连接， 第三走线 205通过第二开口 320与第二走线 203电连 接。
参见图 4, 为步骤 1-2和 4-5对应的掩模板 ( mask )处理成形示意图。 本发明的另一个实施例提供了一种显示面板的制作方法， 该方法可以如 下进行：
S301、 在基底基板上形成有源层；
S302、 在基底基板上形成源漏金属层， 由此在显示区域中形成位于有源 层上的源漏电极和数据线， 在栅线外围走线区中形成第一走线；
5303、 在源漏金属层上形成栅绝缘层， 在栅线外围走线区的栅绝缘层中 形成第一开口， 该第一开口暴露至少部分第一走线；
5304、在栅绝缘层上形成栅金属层，由此在显示区域中形成栅极和栅线， 在在栅线外围走线区中形成第二走线， 该第二走线通过第一开口与第一走线 电连接。
该基底基板例如为玻璃基板， 栅线外围走线区形成在显示区域的外侧， 例如矩形基板的彼此相对的两侧或全部四侧。 上述实施例以顶栅型显示面板 为例进行了说明， 但本发明不限于此。
上述示例中， 本发明实施例的方法在构图有源层时， 可将栅线外围走线 区及其附近的有源层全部刻蚀， 则可以使用与制备传统显示面板的工艺相同 的有源层掩模板。 例如， 有源层的构图是在栅极绝缘层和源漏金属层的构图 之间进行的。 如果栅线外围走线区仅将第一开口处的有源层去除， 则使用的 有源层掩模板与制备传统显示面板的工艺中所使用的不同， 在相应的构图工 艺保留在栅线外围走线区中的有源层。
在上述实施例通过改变栅极绝缘层掩才莫板以在其中形成第一开口以及通 过改变绝缘保护层掩模板以在其中形成第二开口， 以及通过第一和第二开口 连接第一至第三层金属走线以得到栅线外围走线， 实现降低栅线外围走线电 阻的目的。
综上所述， 本发明实施例提供了一种显示面板及其制作方法、 液晶显示 器， 可降低栅线外围走线的电阻， 减小信号衰减与延迟， 提高显示效果。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
11、、 一一种种显显示示面面板板，， 包包括括布布置置有有栅栅线线外外围围走走线线的的栅栅线线外外围围走走线线区区，， 其其中中，， 所所述述栅栅线线外外围围走走线线包包括括依依次次形形成成于于基基底底基基板板上上的的第第一一走走线线、、 栅栅极极绝绝缘缘层层和和第第
55 二二走走线线；； 所所述述栅栅极极绝绝缘缘层层包包括括至至少少一一个个第第一一开开口口，， 所所述述第第一一走走线线与与所所述述第第二二 走走线线通通过过该该第第一一开开口口电电连连接接。。
11、、如如权权利利要要求求 11所所述述的的显显示示面面板板，， 其其中中，， 该该栅栅线线外外围围走走线线还还包包括括绝绝缘缘保保 护护层层和和在在所所述述绝绝缘缘保保护护层层上上方方的的第第三三走走线线。。
33、、如如权权利利要要求求 22所所述述的的显显示示面面板板，， 其其中中，， 所所述述绝绝缘缘保保护护层层包包括括至至少少一一个个 1100 第第二二开开口口，， 所所述述第第三三走走线线与与所所述述第第二二走走线线通通过过该该第第二二开开口口电电连连接接。。
44、、如如权权利利要要求求 33所所述述的的显显示示面面板板，， 其其中中，， 所所述述第第二二开开口口的的总总长长度度大大于于栅栅 线线外外围围走走线线长长度度的的二二分分之之一一。。
55、、 如如权权利利要要求求 11--44任任一一所所述述的的显显示示面面板板，， 其其中中，， 所所述述第第一一开开口口的的总总长长度度 大大于于栅栅线线外外围围走走线线长长度度的的二二分分之之一一。。
1155 66、、如如权权利利要要求求 11所所述述的的显显示示面面板板，，其其中中，，该该栅栅线线外外围围走走线线还还包包括括中中间间层层，， 所所述述第第一一开开口口还还穿穿过过该该中中间间层层。。
77、、 一一种种液液晶晶显显示示器器，， 包包括括权权利利要要求求 11--66任任一一权权项项所所述述的的显显示示面面板板。。
88、、一一种种显显示示面面板板的的制制作作方方法法，，该该显显示示面面板板包包括括显显示示区区和和栅栅线线外外围围走走线线区区，， 该该制制作作方方法法包包括括：：
2200 在在基基底底基基板板上上在在所所述述栅栅线线外外围围走走线线区区中中依依次次形形成成用用于于栅栅线线外外围围走走线线的的第第 一一走走线线、、 栅栅极极绝绝缘缘层层和和第第二二走走线线；； 所所述述栅栅极极绝绝缘缘层层包包括括至至少少一一个个第第一一开开口口，， 所所述述第第一一走走线线与与所所述述第第二二走走线线通通过过该该第第一一开开口口电电连连接接。。
99、、 根根据据权权利利要要求求 88的的制制作作方方法法，， 包包括括：：
在在所所述述基基底底基基板板上上在在所所述述显显示示区区中中形形成成栅栅线线和和栅栅极极，， 同同时时在在所所述述栅栅线线外外 2255 围围走走线线区区中中形形成成第第一一走走线线；；
依依次次形形成成栅栅极极绝绝缘缘层层和和有有源源层层，， 并并且且在在所所述述栅栅线线外外围围走走线线区区中中形形成成至至少少 一一个个所所述述第第一一开开口口；；
在在所所述述有有源源层层上上形形成成源源漏漏金金属属层层，， 同同时时在在所所述述栅栅线线外外围围走走线线区区中中第第一一开开 口口处处形形成成第第二二走走线线；；
3300 * 在所述绝缘保护层上形成像素电极层。
10、 如权利要求 9所述的方法， 其中， 在所述源漏金属层上形成所述绝 缘保护层后， 在所述栅线外围走线区中在所述绝缘保护层中形成至少一个第 二开口，
在所述绝缘保护层上形成所述像素电极层时， 在所述栅线外围走线区中 的第二开口处形成第三走线。
11、如权利要求 10所述的方法， 其中， 所述第二开口的总长度大于栅线 外围走线长度的二分之一。
12、 如权利要求 9-11任一所述的方法， 其中， 所述第一开口的总长度大 于栅线外围走线长度的二分之一。
13、 如权利要求 9-12任一所述的方法， 其中， 依次形成所述栅极绝缘层 和所述有源层并且在所述栅线外围走线区中形成至少一个所述第一开口， 包 括：
形成所述栅极绝缘层并且在所述栅线外围走线区中的所述栅极绝缘层中 形成至少一个所述第一开口；
形成所述有源层并且去除所述栅线外围走线区中第一开口处的有源层。
14、 如权利要求 9-12任一所述的方法， 其中， 依次形成所述栅极绝缘层 和所述有源层并且在所述栅线外围走线区形成至少一个所述第一开口，包括： 形成所述栅极绝缘层；
形成所述有源层， 并且在所述栅线外围走线区中形成至少一个所述第一 开口， 而且所述第一开口处的栅极绝缘层和所述有源层均被去除。
15、 如权利要求 8所述的方法， 包括：
在所述基底基板上形成有源层；
在所述基底基板上形成源漏金属层， 在所述栅线外围走线区中形成所述 第一走线；
在所述源漏金属层上形成所述栅绝缘层， 在所述栅线外围走线区中在所 述栅绝缘层中形成至少一个所述第一开口；
在所述栅绝缘层上形成栅金属层， 在所述栅线外围走线区中形成所述第 二走线， 所述第二走线通过所述第一开口与所述第一走线电连接。
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CN106094373A (zh) * 2016-06-02 2016-11-09 武汉华星光电技术有限公司 Tft基板及其制作方法
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CN114597223A (zh) * 2022-03-25 2022-06-07 北京京东方显示技术有限公司 显示基板及制备方法、显示面板和显示装置
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