WO2014155974A1 - 半導体デバイス - Google Patents
半導体デバイス Download PDFInfo
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- WO2014155974A1 WO2014155974A1 PCT/JP2014/001105 JP2014001105W WO2014155974A1 WO 2014155974 A1 WO2014155974 A1 WO 2014155974A1 JP 2014001105 W JP2014001105 W JP 2014001105W WO 2014155974 A1 WO2014155974 A1 WO 2014155974A1
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- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K1/02—Details
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- H01L2223/66—High-frequency adaptations
- H01L2223/6644—Packaging aspects of high-frequency amplifiers
- H01L2223/6655—Matching arrangements, e.g. arrangement of inductive and capacitive components
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
Definitions
- the present disclosure relates to a semiconductor device including a semiconductor device, and more particularly to a semiconductor device including a semiconductor device that processes high frequency signals and a matching circuit.
- the input / output impedance of a semiconductor element that processes high frequency signals is different from the input / output impedance of an external circuit connected to the semiconductor element.
- impedance mismatch occurs between the semiconductor element and the external circuit. It occurs. Therefore, in the semiconductor device, matching circuits (hereinafter simply referred to as "matching circuits") are provided on the input side and the output side of the semiconductor device for high frequency in order to eliminate the impedance mismatch with the external circuit.
- the semiconductor element is a transistor chip and the input power and the output power are high, the gate width of the transistor chip becomes large and the impedance of the transistor chip becomes very low.
- the match is greater.
- the matching circuit loss is increased due to the circuit configuration, and in order to reduce the matching circuit loss, the matching circuit is configured with components having a high Q value, and the matching circuit
- the mainstream is the method of placing the inside of the package.
- the internal matching circuit provided inside the packaged semiconductor device includes a high dielectric constant substrate which can be expected to have a wavelength shortening effect, a conductive layer having a conductive pattern formed on the surface of the high dielectric constant substrate, and A conductive layer for grounding is formed on the entire surface of the back surface of the dielectric constant substrate, and a capacitance pattern or a microstrip line pattern is formed in the internal matching circuit.
- the transistor chip and the internal matching circuit, and the lead terminal for connecting to the external circuit outside the package and the internal matching circuit are connected by a wire such as a gold wire.
- a wire such as a gold wire.
- the inductance of the wire can not be ignored, and the inductance of the wire functions as part of the internal matching circuit. Therefore, if the length of the wire changes due to the positional deviation of the transistor chip and the internal matching circuit or the dimensional tolerance of the transistor chip and the internal matching circuit, high frequency characteristics of the semiconductor device, for example, the external circuit and the semiconductor device Variations occur in high frequency characteristics such as loss due to impedance mismatch at the connection point of the above and / or transmission loss in the signal transmission line from the lead terminal to the transistor chip.
- Patent Document 1 forms a groove in advance on the mounting surface on which the transistor chip and the matching circuit substrate are mounted, and positions the transistor chip and the matching circuit substrate by the groove. Methods are disclosed.
- Patent Document 2 discloses a method in which a recess is formed in advance on a mounting surface on which a circuit substrate is mounted, and the circuit substrate is embedded in the recess.
- the semiconductor device is disposed on a convex pedestal formed on the surface of the carrier plate, and the pedestal is a semiconductor device in which the matching circuit substrate is mounted on the surface of the carrier plate in the vicinity of the pedestal.
- An arrangement (with overhanging sides) with a cross section of inverted trapezoidal shape is disclosed.
- Patent Documents 1 to 3 require special additional processing to form a reference portion for positioning a groove or a recess with respect to the mounting surface on which the transistor chip and the matching circuit substrate are mounted.
- the transistor chip and the matching circuit board are positioned based on the reference portion formed by such additional processing, high processing accuracy is required in the additional processing for forming the reference portion.
- the portion of the mounting surface around the processed portion is distorted and the transistor chip and the matching circuit substrate are mounted
- the flatness of the mounting surface portion may be reduced. As a result, the positioning accuracy of the transistor chip and the matching circuit board with respect to the mounting surface may be reduced.
- a semiconductor device having a package which comprises: As parts placed inside the package, Input and output terminals for exchanging signals with external circuits outside the package; A semiconductor element disposed on a signal transmission path between the input terminal and the output terminal to perform signal processing; The signal transmission path is disposed on at least one of a signal transmission path on the input side between the input terminal and the semiconductor element and a signal transmission path on the output side between the semiconductor element and the output terminal, An internal matching circuit substrate for matching at least one of the output impedance of an external circuit connected to the input impedance of the semiconductor device or the input impedance of the external circuit connected to the output terminal and the output impedance of the semiconductor device , And a plurality of wires for electrically connecting parts to transmit a signal; In the plurality of wires, the inside of the package is brought into direct or indirect contact with parts electrically connected by at least one wire whose high frequency characteristics of the semiconductor device change over tolerance when the wire length changes. It
- the parts in the semiconductor device are brought into contact with each other. Variations in wire length can be suppressed.
- semiconductor devices can be manufactured at low cost, and semiconductor devices having excellent characteristics in which variations in high frequency characteristics are suppressed can be provided.
- the semiconductor device is A semiconductor device having a package, As parts placed inside the package, Input and output terminals for exchanging signals with external circuits outside the package; A semiconductor element disposed on a signal transmission path between the input terminal and the output terminal to perform signal processing; The signal transmission path is disposed on at least one of a signal transmission path on the input side between the input terminal and the semiconductor element and a signal transmission path on the output side between the semiconductor element and the output terminal, An internal matching circuit substrate for matching at least one of the output impedance of an external circuit connected to the input impedance of the semiconductor device or the input impedance of the external circuit connected to the output terminal and the output impedance of the semiconductor device , And a plurality of wires for electrically connecting parts to transmit a signal; In the plurality of wires, the inside of the package is brought into direct or indirect contact with parts electrically connected by at least one wire whose high frequency characteristics of the semiconductor device change over tolerance when the wire length changes. It has been arranged.
- the impedance of the semiconductor element whose reactance component is 0 or less is transformed by the inductance of the wire and the matching circuit of the internal matching circuit substrate.
- the inside of the package in a state in which the parts to which the wire closest to the semiconductor element is electrically connected are in direct or indirect contact It may be located at
- an impedance whose reactance component of the semiconductor element is 0 or less is transformed by the inductance of the wire and the matching circuit of the internal matching circuit substrate.
- the internal matching circuit board that transforms the reactance component of the semiconductor element from an impedance of 0 or less to an inductive impedance the wire immediately after being transformed to the inductive impedance by the internal matching circuit board closest to the semiconductor element is electrically
- the parts to be connected may be placed inside the package in direct or indirect contact with each other.
- the internal matching circuit board comprises: An input side internal matching circuit substrate disposed in a signal transmission path on the input side between the input terminal and the semiconductor element for matching the impedance on the input side; An output side matching circuit substrate disposed in the signal transmission path on the output side between the semiconductor element and the output terminal, for matching the impedance on the output side, Direct or indirect contact between the semiconductor element and the input side internal matching circuit substrate,
- the output side internal matching circuit substrate and the output terminal may be disposed inside the package with direct or indirect contact.
- the semiconductor device according to the fifth aspect of the present disclosure is the wire according to the first aspect, except that the high frequency characteristics of the semiconductor device change beyond an allowable value when the wire length changes.
- the components electrically connected by at least one wire may be arranged inside the package in a separated state.
- a semiconductor device has a transistor chip as the semiconductor element in any of the first to fifth aspects described above,
- the gate of the transistor chip is at the input terminal side, and
- the drain of the transistor chip may be on the output terminal side.
- the index of the high frequency characteristics of the semiconductor device is an input end or an output end at the input terminal, or an output It may be an impedance mismatch loss at the input or output end of the terminal.
- the index of the high frequency characteristics of the semiconductor device is between the input terminal and the semiconductor element or the semiconductor element It may be a transmission loss of the signal transmission path to the output terminal.
- the index of the high frequency characteristics of the semiconductor device is a power gain from the input terminal to the output terminal. It is also good.
- semiconductor device of the present disclosure a semiconductor device having a transistor chip as a semiconductor element in a package will be described with reference to the attached drawings.
- the semiconductor device of the present disclosure is not limited to the configuration of the semiconductor device described in the following embodiments, and is configured based on the technical idea equivalent to the technical idea described in the following embodiments. Devices are included.
- Embodiment 1 the semiconductor device according to the first embodiment of the present disclosure will be described with reference to the attached drawings.
- FIG. 1 is a top view of the semiconductor device of the first embodiment.
- FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG.
- a base portion 101 on which components are mounted and a region on the base portion 101 where components are mounted are clearly defined on the base portion 101.
- the package of the semiconductor device constituted by the base portion 101, the ceramic frame 104, the input terminal 102, and the output terminal 103, that is, in the region surrounded by the ceramic frame 104 on the base portion 101 As components disposed inside the package, a transistor chip 106 as a semiconductor element, a first internal matching circuit board 107, and a second internal matching circuit board 108 are mounted.
- the first internal matching circuit substrate 107 and the second internal matching circuit substrate 108 are formed on the input side internal matching circuit substrate provided between the input terminal 102 and the transistor chip 106. is there.
- the base portion 101 is provided with a notch 105 having a portion cut into an arc shape, and is screwed to another member via the notch 105 to modularly mount the semiconductor device.
- the input terminal 102 and the output terminal 103 are terminals for exchanging signals with an external circuit (not shown) outside the package, and electrically connect the external circuit to components in the package.
- the transistor chip 106 is formed of, for example, a semiconductor chip or the like for amplifying a high frequency signal using a semiconductor such as Si-LDMOS, GaAs, or GaN. Also, the transistor chip 106 is disposed on the signal transmission path between the input terminal 102 and the output terminal 103. Furthermore, the back surface of the transistor chip 106 in the first embodiment is disposed on the base portion 101, and is joined via a fixing means such as paste or solder, for example. Furthermore, the source terminal of the transistor chip 106 is electrically connected to the base portion 101 via, for example, a conductive layer formed on the back surface, a through via, or a wire.
- the first and second inner matching circuit boards 107 and 108 are formed by forming a pattern of a conductor layer on the front and back of a high dielectric constant ceramic substrate made of, for example, alumina or titanium oxide.
- the semiconductor device in the semiconductor device according to the first embodiment, matching of the input impedance of the transistor chip 106 with the output impedance of the external circuit connected to the input terminal 102 by the first and second internal matching circuit substrates 107 and 108 is performed.
- the signal transmission path on the input side between the input terminal 102 and the transistor chip 106 is provided in order to obtain
- the first internal matching circuit board 107 is disposed on the transistor chip 106 side
- the second internal matching circuit board 108 is on the input terminal 102 side. It is arranged.
- the back surfaces of the first and second internal matching circuit boards 107 and 108 are joined to the base portion 101 by, for example, a conductive paste, a solder or the like. That is, the conductor layer formed on the back surface of each of the first and second internal matching circuit substrates 107 and 108 and the base portion 101 are electrically connected.
- the input terminal 102 and the conductor layer pattern on the surface of the second internal matching circuit board 108 are electrically connected by a plurality of first wires 109 such as gold wires.
- the conductor layer pattern on the surface of the first inner matching circuit board 107 and the conductor layer pattern on the surface of the second inner matching circuit board 108 are electrically connected by the plurality of second wires 110. It is done.
- the conductor layer pattern on the surface of the first internal matching circuit substrate 107 and the gate terminal of the transistor chip 106 are electrically connected by the plurality of third wires 111.
- the drain terminal of the transistor chip 106 and the output terminal 103 are electrically connected by the plurality of fourth wires 112.
- the semiconductor device according to the first embodiment is mounted on the base portion 101 in a state in which the components of the first internal matching circuit board 107 and the transistor chip 106 are in direct contact with each other. .
- each of the first inner matching circuit substrate 107 and the transistor chip 106 is the outer surface of each component, and is a predetermined position on the outer surface of each component.
- a straight line connecting the connection point of the conductor layer pattern of the first internal matching circuit board 107 connected by the third wire 111 and the gate terminal of the transistor chip 106 is viewed from above.
- the surface intersecting the line is the contact surface of each part.
- the first internal matching circuit substrate 107 connected by the third wire 111 and the transistor chip 106 are in direct contact with each other, and the semiconductor device is configured.
- the impedance of the external circuit connected to the input terminal 102 of the semiconductor device is 50 ⁇ .
- FIG. 3 shows an equivalent circuit of the semiconductor device of the first embodiment shown in FIG. 1 and FIG. In each element in FIG. 3, the component numbers of the semiconductor device of the first embodiment shown in FIG. 1 and FIG. 2 are attached.
- the input terminal 102 and the output terminal 103 can be regarded as a microstrip line on the ceramic frame 104 because the base portion 101 is grounded.
- FIG. 4 is a Smith chart showing the impedance seen from the side of the transistor chip 106 at each of the connection points A to F between the plurality of components shown in the equivalent circuit of FIG. FIG. 4 shows, as an example, the case where the input impedance of the transistor chip 106 is (2.000 + j0) ⁇ and the signal frequency is 2 GHz. That is, the reactance component in the impedance of the transistor chip 106 is less than or equal to zero.
- the impedance seen from the connection point A between the transistor chip 106 and the third wire 111 to the side of the transistor chip 106 is the input impedance of the transistor chip 106 itself, and so the point A in FIG. ) It was ⁇ .
- the transistor chip 106 side is connected to the connection point B between the third wire 111 and the matching circuit of the first internal matching circuit board 107.
- the impedance seen was (2.000 + j6.283) ⁇ indicated by point B in FIG.
- the transistor chip 106 side is connected to the connection point C between the matching circuit of the first internal matching circuit substrate 107 and the second wire 110.
- the impedance seen was (18.614 + j7.627) ⁇ indicated by point C in FIG.
- the transistor chip 106 side is viewed from the connection point D between the second wire 110 and the matching circuit of the second internal matching circuit substrate 108
- the impedance was (18.614 + j23.964) ⁇ , which is indicated by point D in FIG.
- the transistor chip from the connection point E between the matching circuit of the second internal matching circuit board 108 and the first wire 109 The impedance seen on the side 106 was (48.484-j6.897) ⁇ indicated by point E in FIG.
- the impedance seen from the connection point F of the first wire 109 and the input terminal 102 to the transistor chip 106 is the point F in FIG. It is (48.484-j0.614) ohm shown by and was about 50 ohm.
- This 50 ⁇ is approximately equal to the impedance of the external circuit connected to the input terminal 102 of the semiconductor device in the present example, whereby impedance matching between the semiconductor device and the external circuit can be achieved.
- the inductance value of the wire can be adjusted by changing the length of the wire, the number of wires, and the distance between the wires.
- the capacitance values of the first and second internal matching circuit substrates 107 and 108 are respectively the relative permittivity of the high dielectric constant substrate, the thickness of the high dielectric constant substrate, and the conductive layer formed on the front and back surfaces thereof. It can be adjusted by changing the area.
- FIG. 5 shows the impedance mismatch loss at the connection point F when the inductance value of any one of the first wire 109, the second wire 110, and the third wire 111 changes with respect to the design value. Is shown.
- the horizontal axis indicates the change in the inductance value of the wires 109 to 111
- the vertical axis indicates the impedance mismatch loss at the connection point F.
- FIG. 5 shows the case where the inductance values of the wires 109 to 111 change within the range of ⁇ 0.1 nH with respect to the design value.
- the design value referred to here is the inductance value of the wire on the design (calculation) that can match the input impedance of the transistor chip 106 and the output impedance of the external circuit connected to the input terminal 102.
- the characteristic of the mismatching loss of the impedance in the connection point F is used as an example of a parameter
- the impedance mismatch loss can be calculated by ⁇ 10 ⁇ log (1 ⁇ 2 ), where ⁇ is the reflection coefficient at the connection point F.
- the broken line graph (circle) shown in FIG. 5 indicates the change in the inductance of the first wire 109 electrically connecting the input terminal 102 to the matching circuit of the second internal matching circuit board 108 at the connection point F. It shows a change in impedance mismatch loss. Specifically, if the inductance of the first wire 109 changes within a designed value of 0.5 nH to ⁇ 0.1 nH, that is, substantially unavoidable errors that occur in the manufacture of semiconductor devices (for example, parts) Change in impedance mismatch loss at connection point F assuming that the effective inductance value changes within the range of 0.4 to 0.6 nH due to the dimensional tolerance of the There is.
- the dotted line graph (square mark) shown in FIG. 5 indicates a second wire 110 electrically connecting the matching circuit of the second internal matching circuit board 108 and the matching circuit of the first internal matching circuit board 107.
- the change in the impedance mismatch loss at the connection point F with respect to the change in the inductance of FIG. Specifically, when the inductance of the second wire 110 changes in the range of ⁇ 0.1 nH with respect to the designed value of 1.3 nH, that is, the effective inductance value is 1.2 to 1.4 nH. It shows a change in impedance mismatch loss at the connection point F when it is assumed to change within the range.
- the solid line graph (triangular mark) shown in FIG. 5 indicates a connection point F with respect to a change in inductance of the third wire 111 electrically connecting the matching circuit of the first internal matching circuit board 107 and the transistor chip 106.
- the variation in inductance of the third wire 111 is mainly caused by the variation in length of the third wire 111.
- the variation in the length of the third wire 111 mainly relates to the relative position between the first internal matching circuit board 107 and the transistor chip 106 electrically connected to each other through the third wire 111. Caused by variations in the relationship.
- the semiconductor device of the first embodiment in order to suppress the variation in relative positional relationship between the first internal matching circuit substrate 107 and the transistor chip 106, the internal matching circuit substrate 107 and the transistor chip 106 are disposed on the base portion 101 in contact with each other.
- transistor chip 106, first internal matching circuit substrate 107, and second internal matching circuit substrate 108 are joined to base portion 101 via, for example, paste or solder.
- a paste in a molten state is applied onto the base portion 101, and the transistor chip 106 and the first internal matching circuit substrate 107 are disposed on the applied paste in contact with each other.
- the transistor chip 106 and the first internal matching circuit board 107 are disposed in the package of the semiconductor device in a contact state.
- the relative relationship between the transistor chip 106 and the first internal matching circuit substrate 107 can be obtained.
- the variation in positional relationship can be significantly suppressed as compared to the case where the transistor chip 106 and the first internal matching circuit board 107 are separated and disposed inside the package. That is, even if the positions of the transistor chip 106 and the first internal matching circuit substrate 107 with respect to the base portion 101 vary, the relative positional relationship between the transistor chip 106 and the first internal matching circuit substrate 107 Does not change.
- the first embodiment it is possible to provide a semiconductor device in which variations in high frequency characteristics are suppressed without processing the base portion 101, that is, at low cost.
- FIG. 6 is a top view of the semiconductor device of the second embodiment according to the present disclosure.
- elements having substantially the same functions and configurations as those of the first embodiment described above are given the same reference numerals.
- elements in the base portion 101, the input terminal 102, the output terminal 103, the ceramic frame 104, the transistor chip 106, the first wire 109, the second wire 110, and the third wire 111 Is the same as the elements, functions and configurations in the semiconductor device of the first embodiment described above, and therefore the description thereof is omitted in the second embodiment.
- one matching circuit 107a, 108a similar to the matching circuit (conductor layer pattern) in the first and second internal matching circuit boards 107, 108 in the first embodiment is provided on one substrate.
- a third matching circuit board 601 is formed.
- the third matching circuit substrate 601 is provided on the signal transmission path on the input side between the input terminal 102 and the transistor chip 106.
- the fourth internal matching circuit substrate 602 and the fifth internal matching circuit substrate 603 are provided on the signal transmission path on the output side between the transistor chip 106 and the output terminal 103. It is provided.
- the fourth internal matching circuit substrate 602 is disposed on the transistor chip 106 side, and the fifth internal matching circuit substrate 603 is on the output terminal 103 side. It is arranged.
- the third, fourth and fifth internal matching circuit boards 601, 602 and 603 have their back surfaces joined to the base portion 101 by, for example, conductive paste or solder. It is done.
- the fourth internal matching circuit substrate 602 is configured by forming a pattern of a conductive layer on the surface of a high dielectric constant ceramic substrate made of, for example, alumina or titanium oxide, and forming a conductive layer on the entire back surface. ing.
- the fifth inner matching circuit substrate 603 is configured by forming a pattern of a conductive layer on the surface of the high dielectric constant ceramic substrate and forming a conductive layer on the entire back surface. Specifically, a main path pattern 603a used as a microstrip line and an island pattern 603b used as a parallel capacitance are formed on the surface of the high dielectric constant ceramic substrate.
- the conductor layer pattern on the surface of the fourth internal matching circuit substrate 602 is electrically connected to the drain terminal of the transistor chip 106 by a plurality of fifth wires 604 such as gold wires. Furthermore, the conductor layer pattern on the surface of the fourth inner matching substrate 602 is electrically connected to the main path pattern 603 a of the fifth inner matching circuit substrate 603 by a plurality of sixth wires 605. That is, the conductor layer pattern on the surface of the fourth inner matching circuit substrate 602 functions as a microstrip line.
- the main path pattern 603a of the fifth internal matching circuit substrate 603 is electrically connected to the output terminal 103 by the plurality of seventh wires 606, and the fourth interior by the plurality of sixth wires 605. By being electrically connected to the conductor layer pattern on the surface of the matching circuit substrate 602, it functions as a microstrip line.
- the island pattern 603 b of the fifth internal matching circuit substrate 603 is electrically connected to the output terminal 103 by the plurality of eighth wires 607, and the conductor on the back surface of the fifth internal matching circuit substrate 603.
- the parallel plate type capacitance generated between the layers functions as a parallel capacitance.
- FIG. 7 shows an equivalent circuit of the semiconductor device of the second embodiment shown in FIG.
- the circuit of the signal transmission path on the input side from input terminal 102 to transistor chip 106 is the same as the equivalent circuit shown in FIG. ing.
- the fifth to eighth wires 604 to 607 can be regarded as inductances as shown in FIG. 7 in order to transmit high frequency signals.
- the conductor pattern on the surface of the fourth inner matching circuit board 602 functions as a microstrip line as described above.
- the main path pattern 603a of the fifth internal matching circuit board 603 functions as a microstrip line as described above.
- the island pattern 603b of the fifth inner matching path substrate 603 functions as a parallel capacitance as described above.
- the external circuit electrically connected to the output terminal 103 is a series inductor 701 whose one end is connected to the output terminal 103.
- the semiconductor device according to the second embodiment is configured such that the impedance seen from the connection point N of the inductor 701 and the capacitor 702 to the transistor chip 106 is 50 ⁇ .
- FIG. 8 shows, on a Smith chart, the impedance seen from the side of the transistor chip 106 at each of connection points G to N between the plurality of components shown in the equivalent circuit of FIG.
- FIG. 8 shows, as an example, the case where the output impedance of the transistor chip 106 is (2.00 to j6.00) and the signal frequency is 2 GHz. That is, the reactance component in the impedance of the transistor chip 106 is negative, which is less than or equal to zero.
- the transistor chip 106 side is connected to the connection point H between the fifth wire 604 and the matching circuit of the fourth internal matching circuit substrate 602.
- the impedance seen was (2.00-j 4.743) ⁇ indicated by point H in FIG.
- the matching circuit of the fourth internal matching circuit substrate 602 when the characteristic impedance of the microstrip line of the fourth internal matching circuit substrate 602 is 10 ⁇ and the phase rotation amount at 2 GHz is 8 °, the matching circuit of the fourth internal matching circuit substrate 602 and The impedance seen from the connection point I with the sixth wire 605 to the side of the transistor chip 106 was (1.791 ⁇ j3.177) ⁇ indicated by a point I in FIG.
- the transistor chip 106 side is viewed from the connection point J of the sixth wire 605 and the matching circuit of the fifth internal matching circuit substrate 603.
- the impedance was (1.791-j1.920) ⁇ indicated by point J in FIG.
- the matching circuit of the fifth internal matching circuit substrate 603 is (1.596 + j0.931) ⁇ indicated by a point K in FIG.
- the impedance seen from the connection point L of the seventh wire 606 and the output terminal 103 to the transistor chip 106 is a point in FIG. It was (1.596 + j2.816) ⁇ shown by L.
- the inductance value of the eighth wire 607 (the total inductance value of the two eighth wires 607 shown in FIG. 6) is 0.15 nH, and the effective capacitance value of the island pattern 603b is
- the impedance seen from the connection point M of the eighth wire 607 and the output terminal 103 to the side of the transistor chip 106 is (6.459 + j0.823) ⁇ indicated by a point M in FIG. .
- the connection between the inductor 701 and the capacitor 702 was (48.761-j0.710) ⁇ indicated by the point N in FIG.
- the impedance seen from the connection point N to the side of the transistor chip 106 has a value substantially equal to 50 ⁇ which is the impedance of the external circuit.
- the inductance value of the wire can be adjusted by changing the length of the wire, the number of wires, and the distance between the wires.
- the capacitance value of the island pattern 603 b can be adjusted by the relative permittivity and thickness of the high dielectric constant ceramic substrate of the fifth inner matching circuit substrate 603 and the area of the conductor layer pattern.
- each matching circuit (conductor layer pattern) is divided into one high It may be formed on a dielectric constant ceramic substrate.
- FIG. 9 shows the impedance mismatch at the connection point N when the inductance value of any one of the fifth wire 604, the sixth wire 605, and the seventh wire 606 changes relative to the design value. Indicates a loss.
- the horizontal axis indicates the change in the inductance value of the wires 604 to 606, and the vertical axis indicates the impedance mismatch loss at the connection point N.
- FIG. 9 shows the case where the inductance values of the wires 604 to 606 change within the range of ⁇ 0.05 nH with respect to the design value.
- the solid line graph (triangular mark) shown in FIG. 9 is a connection point for the change in inductance of the fifth wire 604 electrically connecting the drain terminal of the transistor chip 106 and the matching circuit of the fourth internal matching circuit substrate 602.
- the change in impedance mismatch loss at N is shown. Specifically, if the inductance of the fifth wire 604 changes by a designed value of 0.1 nH to ⁇ 0.05 nH, that is, substantially unavoidable errors that occur in the manufacture of the semiconductor device (for example, dimensional tolerances of the respective parts)
- the figure shows the change in impedance mismatch loss at the connection point N when it is assumed that the effective inductance value changes in the range of 0.05 to 0.15 nH due to the positioning tolerance of parts, etc.).
- the dotted line graph (square mark) shown in FIG. 9 is a sixth wire 605 for electrically connecting the fourth internal matching circuit board 602 and the fifth internal matching circuit board 603 (main path pattern 603a).
- the broken line graph (circle) shown in FIG. 9 is for the change in inductance of the seventh wire 606 that electrically connects the fifth internal matching circuit board 603 (main path pattern 603a) and the output terminal 103.
- the change in the impedance mismatch loss at the connection point N is shown. Specifically, it is assumed that when the inductance of the seventh wire 606 changes from the designed value of 0.15 nH to ⁇ 0.05 nH, that is, the effective inductance value changes within the range of 0.1 to 0.2 nH. Shows the change in the impedance mismatch loss at the connection point N in the case of FIG. As shown in FIG.
- both the seventh wire 606 and the eighth wire 607 electrically connect the matching circuit of the fifth internal matching circuit board 603 to the output terminal 103. Therefore, when the positional relationship between the fifth internal matching circuit board 603 and the output terminal 103 changes, the length of the seventh wire 606 changes, and the length of the eighth wire 607 also changes.
- the broken line graph (circle) shown in FIG. 9 shows the case where the inductance of the seventh wire 606 changes, and the connection point N at the same time when the inductance of the eighth wire 607 changes. Shows the change in the impedance mismatch loss.
- the fifth internal matching circuit is used to suppress the variation in inductance of the seventh wire 606 which is the wire that most affects the high frequency characteristics of the semiconductor device, that is, the variation in wire length.
- the substrate 603 and the output terminal 103 are disposed in the semiconductor device in contact with each other.
- the fifth internal matching circuit board 603 is disposed on the base portion 101 in a state of being in contact with a predetermined position of the ceramic frame body 104 holding the output terminal 103 as shown in FIG. There is.
- the variation in relative positional relationship between the fifth internal matching circuit substrate 603 and the output terminal 103 can be suppressed, and the variation in length of the seventh wire 606 electrically connecting these can be suppressed.
- the reactance component at the connection point K between the main path pattern 603a of the fifth internal matching circuit board 603 and the output terminal 103 Is transformed into a positive state, which is an inductive impedance. Therefore, the parts electrically connected by the seventh wire 606 immediately after the connection point K, that is, the fifth internal matching circuit board 603 and the output terminal 103 are substantially brought into contact with each other. Is mounted on the base unit 105.
- the fifth internal matching circuit substrate 603 closest to the semiconductor element is used as the internal matching circuit substrate for transforming the reactance component of the semiconductor element from an impedance of 0 or less to an inductive impedance.
- the seventh wire 606 immediately after being transformed to the inductive impedance is disposed inside the package in a state where the parts to be electrically connected are in direct or indirect contact with each other.
- the input terminal 102 and the output terminal 103 are bonded in advance to the ceramic frame 104, and the positions of the lead terminals in the input terminal 102 and the output terminal 103 are accurately positioned in the ceramic frame 104.
- each of the ceramic frame body 104 and the fifth internal matching circuit board 603 is formed with accuracy higher than the mounting position accuracy of the component, and the fifth internal matching corresponding to each lead terminal in the output terminal 103
- the contact surfaces are formed such that the distance between the circuit board 603 and the connection terminals is always constant.
- the configuration including the transistor chip 106 as the semiconductor element has been described, but the present invention is not limited to such a configuration.
- the semiconductor element may be any element that performs signal processing, in particular, processing of a high frequency signal.
- the semiconductor device of Embodiment 1, 2 demonstrated the ceramic package type
- the input terminal 102 is opposite to the transistor chip 106 side
- the output terminal 103 is the input terminal on the transistor chip 106 side
- the output terminal 103 is opposite to the transistor chip 106 side It may be a characteristic of impedance mismatch loss at a side output end or the like.
- the power gain from the input terminal 102 to the output terminal 103 or the input / output impedance of the semiconductor device itself may be used as an index of the high frequency characteristics of the semiconductor device. That is, the index of the high frequency characteristics of the semiconductor device may be a characteristic represented by a physical quantity that is affected by the variation of the wire length and affects the performance of the semiconductor device that handles high frequency signals.
- two internal matching circuit boards 107 and 108 are arranged on the signal transmission path on the input side between the input terminal 102 and the transistor chip 106.
- one third internal matching circuit substrate 601 is arranged on the signal transmission path on the input side between the input terminal 102 and the transistor chip 106, and the transistor chip 106 and the output terminal Fourth and fifth internal matching circuit boards 602 and 603 are disposed on the signal transmission path on the output side between 103 and 103.
- the arrangement of the internal matching circuit board of the semiconductor device of the present invention is not limited to the arrangement of the first and second embodiments.
- an external electrically connected to output terminal 103 instead or in addition thereto.
- an external electrically connected to output terminal 103 In order to match the input impedance of the circuit with the output impedance of the transistor chip 106, at least at least on the signal transmission path between the input terminal 102 and the transistor chip 106 and between the transistor chip 106 and the output terminal 103.
- One internal matching circuit board may be disposed.
- the wire that most changes the high frequency characteristics of the semiconductor device when the wire length changes electrically connects the transistor chip 106 and the matching circuit of the first internal matching circuit substrate 107.
- the third wire 111 to be connected is different depending on the configuration of the transistor chip 106 and the first and second internal matching circuit boards 107 and 108, the material and number of the first to fourth wires 109 to 112, and the like. It is clear that the wire that changes the high frequency properties most may be different from the third wire 111.
- the input terminal 102 and the matching circuit of the second internal matching circuit board 108 are electrically
- the first wires 109 connected in series can be wires that most change the high frequency characteristics of the semiconductor device when the wire length changes. That is, it is noted that among the plurality of wires electrically connecting the plurality of parts of the semiconductor device, the wire that most changes the high frequency characteristics of the semiconductor device when the wire length changes differs depending on the configuration of the parts of the semiconductor device. It should.
- the parts electrically connected by the wire that most changes the high frequency characteristics of the semiconductor device when the wire length changes are in direct or indirect contact with each other. It is disposed inside the package of the semiconductor device.
- the package In the case of the first embodiment, as shown in FIG. 1, the package is in a state where the first internal matching circuit substrate 107 electrically connected by the third wire 111 and the transistor chip 106 are in direct contact with each other. It is located inside.
- the fifth internal matching circuit board 603 electrically connected by the seventh wire 606 and the output terminal 103 are indirectly connected via the ceramic frame 104. In contact with the package. That is, in the case of the first and second embodiments, an example in which the parts arranged in contact with each other is one set is described. However, the configuration of the semiconductor device according to the present invention is not limited to one set of parts arranged in contact.
- FIG. 10 shows a semiconductor device in a configuration in which two sets of parts are in contact with each other.
- the semiconductor device shown in FIG. 10 as in the first embodiment shown in FIG. 1, first and second signal transmission paths on the input side between the input terminal 102 and the transistor chip (semiconductor element) 106 are provided.
- Internal matching circuit boards 107 and 108 are provided, and the fourth signal transmission path between the transistor chip (semiconductor element) 106 and the output terminal 103 is provided as in the second embodiment shown in FIG.
- the first internal matching circuit substrate 107 and the transistor chip 106 are in direct contact with each other. is there. Further, in the signal transmission path on the output side between the transistor chip (semiconductor element) 106 and the output terminal 103, the fifth internal matching circuit substrate 603 and the output terminal 103 make indirect contact through the ceramic frame 104. It is in a state of
- a configuration example is shown in which the components of the semiconductor element and the internal matching circuit substrate are in direct contact with each other.
- the position and orientation of the components are unique.
- other components for example, a spacer or the like
- the intermediate member ceramic frame 104
- the output terminal 103 and the ceramic frame body 104 as an intermediate member are integrally formed, and the positions and postures of the output terminal and the internal matching circuit board are uniquely determined.
- the substrate is substantially in the same state as in direct contact.
- the third wire 111 electrically connecting the transistor chip 106 and the matching circuit of the first internal matching circuit substrate 107 is the most characteristic that is an index in the high frequency characteristics of the semiconductor device. It is changing.
- the seventh wire 606 for electrically connecting the matching circuit of the fifth internal matching circuit board 603 and the output terminal 103 is a characteristic serving as an index in the high frequency characteristics of the semiconductor device. Most changed.
- only the third wire 111 and the seventh wire 606 have been described as being changed beyond the allowable value in the characteristic serving as an index in the high frequency characteristic.
- the semiconductor device there may be a plurality of wires in the plurality of wires which change as the wire length changes, exceeding the allowable value of the characteristic serving as an index in the high frequency characteristics of the semiconductor device.
- the maximum value of the impedance mismatch loss caused by the wire length variation of one wire and the maximum value of the impedance mismatch loss caused by the wire length variation of another wire both exceed the allowable value.
- the components electrically connected by one wire are disposed in contact with each other in the package of the semiconductor device, and the components electrically connected by another wire are also in contact with each other. You may arrange in the state which That is, in the configuration of the semiconductor device of the present disclosure, a plurality of sets of components may be arranged in contact.
- the components electrically connected by the wires closest to the semiconductor element are connected It may be disposed inside the package in direct or indirect contact so that the length between the terminals is constant.
- the change in the characteristic that is an indicator of the high frequency characteristic changes depending on the wire
- the amount may be very small and below the tolerance value. In parts electrically connected by such wires, it is not always necessary to place the parts directly or indirectly in contact with each other.
- a range of a plurality of wires caused by substantially unavoidable errors for example, dimensional tolerances of parts, positioning tolerances of parts, etc.
- the parts to which the wires are electrically connected are disposed in the package of the semiconductor device in direct or indirect contact with each other.
- the second internal matching circuit board 108 and the first internal matching circuit board 108 are disposed between the input terminal 102 (ceramic frame 104) and the second internal matching circuit board 108.
- the gap between the internal matching circuit board 107, the first internal matching circuit board 107 and the transistor chip 106, and the transistor chip 106 and the output terminal 103 (ceramic frame 104) is eliminated, and these parts are eliminated. It is conceivable to bring all of them into direct contact. That is, a configuration is conceivable in which the internal matching circuit board on the input side and / or the output side and the semiconductor element are mounted in the internal space of the ceramic frame body 104 without a gap.
- the component mounted on the base portion may not be mounted due to the variation of the dimensions of the previously mounted components, which may narrow the mounting space in the internal space of the ceramic frame.
- a component electrically connected by at least one wire other than a wire that changes the high frequency characteristics of the semiconductor device beyond the allowable value when the wire length changes It is preferable to arrange them inside the package with a gap therebetween. In particular, it is preferable that components electrically connected by a wire with the smallest amount of change in high frequency characteristics of the semiconductor device due to a change in wire length be disposed inside the package in a separated state.
- the components electrically connected by the wire that changes the high frequency characteristics of the semiconductor device beyond the allowable value when the wire length changes directly or indirectly. Contact is preferred.
- the transistor chip 106 and the first internal matching circuit substrate 107 are in direct contact with each other.
- the fifth internal matching circuit board 603 and the output terminal 103 are indirectly in contact with each other through the ceramic frame body 104.
- the output terminal 103 and the ceramic frame 104 are integrally formed, and the fifth internal matching circuit board 603 and the output terminal 103 are in a substantially direct contact state.
- the transistor chip 106 and the first internal matching circuit board 107 are the other component (first internal) with respect to one component (transistor chip 106). If the position and attitude of the matching circuit board 107) are uniquely determined, other members (for example, spacers and the like) may be interposed to indirectly contact the parts connected by the wires.
- the present invention has such a configuration. It is not limited to That is, a semiconductor element (for example, a transistor chip 106) is provided on a signal transmission path between the input terminal 102 and the output terminal 103, and between the input terminal 102 and the semiconductor element and the semiconductor element and the output terminal 103.
- the internal matching circuit board may be provided on at least one of the two.
- the present invention is not limited to such a configuration.
- the components may be kept in contact with each other by being engaged with each other.
- a molten paste (or paste applied on the base of the package, as in the transistor chip 106 and the first internal matching circuit substrate 107 of the first embodiment). If the components of the transistor chip 106 and the first internal matching circuit substrate 107 are placed in contact on the solder) and then the paste is cured, the components are displaced before the paste is cured. There may be gaps between parts. However, the amount of displacement of the component until the paste hardens can be controlled to a small fixed amount by adjusting the amount of paste. That is, by controlling the gap between the parts to, for example, about several tens of ⁇ m, the parts can be brought into a substantially in contact state.
- the semiconductor device of the present disclosure can be applied to various electronic devices such as a mobile communication base station that handles high frequency signals with high output or microwave household appliances such as a microwave oven.
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Abstract
Description
パッケージ内部に配置される部品として、
パッケージ外部の外部回路と信号をやりとりするための入力端子および出力端子と、
前記入力端子と前記出力端子との間の信号伝送経路上に配置されて信号処理を行う半導体素子と、
前記入力端子と前記半導体素子との間の入力側の信号伝送経路、および前記半導体素子と前記出力端子との間の出力側の信号伝送経路の少なくとも一方の信号伝送経路に配置され、前記入力端子に接続される外部回路の出力インピーダンスと当該半導体デバイスの入力インピーダンス、または前記出力端子に接続される外部回路の入力インピーダンスと当該半導体デバイスの出力インピーダンスの少なくとも一方を整合させるための内部整合回路基板と、
部品間を電気的に接続して信号を伝送する複数のワイヤと、を有し、
前記複数のワイヤにおいて、ワイヤ長が変化すると半導体デバイスの高周波特性が許容値を超えて変化する少なくとも1つのワイヤにより電気的に接続される部品同士を直接的または間接的に接触した状態でパッケージ内部に配置している。
パッケージを有する半導体デバイスであって、
パッケージ内部に配置される部品として、
パッケージ外部の外部回路と信号をやりとりするための入力端子および出力端子と、
前記入力端子と前記出力端子との間の信号伝送経路上に配置されて信号処理を行う半導体素子と、
前記入力端子と前記半導体素子との間の入力側の信号伝送経路、および前記半導体素子と前記出力端子との間の出力側の信号伝送経路の少なくとも一方の信号伝送経路に配置され、前記入力端子に接続される外部回路の出力インピーダンスと当該半導体デバイスの入力インピーダンス、または前記出力端子に接続される外部回路の入力インピーダンスと当該半導体デバイスの出力インピーダンスの少なくとも一方を整合させるための内部整合回路基板と、
部品間を電気的に接続して信号を伝送する複数のワイヤと、を有し、
前記複数のワイヤにおいて、ワイヤ長が変化すると半導体デバイスの高周波特性が許容値を超えて変化する少なくとも1つのワイヤにより電気的に接続される部品同士を直接的または間接的に接触した状態でパッケージ内部に配置している。
このように構成された第1の観点の半導体デバイスは、低コストで製造することが可能となり、高周波特性のバラツキを抑制することができる。
前記半導体素子のリアクタンス成分を0以下のインピーダンスから誘導性のインピーダンスへ変成するワイヤにおいて、前記半導体素子に最も近いワイヤが電気的に接続する部品同士を直接的または間接的に接触した状態でパッケージ内部に配置してもよい。
前記半導体素子のリアクタンス成分を0以下のインピーダンスから誘導性のインピーダンスへ変成する前記内部整合回路基板において、前記半導体素子に最も近い内部整合回路基板によって誘導性のインピーダンスへ変成された直後のワイヤが電気的に接続する部品同士を直接的または間接的に接触した状態でパッケージ内部に配置してもよい。
前記入力端子と前記半導体素子との間の入力側の信号伝送経路に配置され、入力側のインピーダンスを整合させるための入力側内部整合回路基板と、
前記半導体素子と前記出力端子との間の出力側の信号伝送経路に配置され、出力側のインピーダンスを整合させるための出力側整合回路基板と、を含み、
前記半導体素子と前記入力側内部整合回路基板とが直接的または間接的に接触し、
前記出力側内部整合回路基板と前記出力端子とが直接的または間接的に接触した状態でパッケージ内部に配置されてもよい。
前記トランジスタチップのゲートが入力端子側であって、
前記トランジスタチップのドレインが出力端子側であってもよい。
以下、本開示に係る実施の形態1の半導体デバイスを添付の図面を参照しながら説明する。
次に、本開示に係る実施の形態2の半導体デバイスについて添付の図面を参照して説明する。図6は、本開示に係る実施の形態2の半導体デバイスの上面図である。図6において、前述の実施の形態1と実質的に同一の機能、構成を有する要素には同じ番号を付与している。
102 入力端子
103 出力端子
104 セラミック枠体
105 切欠き
106 トランジスタチップ(半導体素子)
107 第1の内部整合回路基板
108 第2の内部整合回路基板
109 第1のワイヤ
110 第2のワイヤ
111 第3のワイヤ
112 第4のワイヤ
601 第3の内部整合回路基板
602 第4の内部整合回路基板
603 第5の内部整合回路基板
604 第5のワイヤ
605 第6のワイヤ
606 第7のワイヤ
607 第8のワイヤ
701 外部回路の直列インダクタ
702 外部回路の並列容量
Claims (9)
- パッケージを有する半導体デバイスであって、
パッケージ内部に配置される部品として、
パッケージ外部の外部回路と信号をやりとりするための入力端子および出力端子と、
前記入力端子と前記出力端子との間の信号伝送経路上に配置されて信号処理を行う半導体素子と、
前記入力端子と前記半導体素子との間の入力側の信号伝送経路、および前記半導体素子と前記出力端子との間の出力側の信号伝送経路の少なくとも一方の信号伝送経路に配置され、前記入力端子に接続される外部回路の出力インピーダンスと当該半導体デバイスの入力インピーダンス、または前記出力端子に接続される外部回路の入力インピーダンスと当該半導体デバイスの出力インピーダンスの少なくとも一方を整合させるための内部整合回路基板と、
部品間を電気的に接続して信号を伝送する複数のワイヤと、を有し、
前記複数のワイヤにおいて、ワイヤ長が変化すると半導体デバイスの高周波特性が許容値を超えて変化する少なくとも1つのワイヤにより電気的に接続される部品同士を直接的または間接的に接触した状態でパッケージ内部に配置した半導体デバイス。 - 前記半導体素子のリアクタンス成分が0以下のインピーダンスを、前記ワイヤのインダクタンスと前記内部整合回路基板の整合回路とにより変成して、前記入力端子に接続される外部回路の出力インピーダンスまたは前記出力端子に接続される外部回路の入力インピーダンスと整合させるよう構成されており、
前記半導体素子のリアクタンス成分を0以下のインピーダンスから誘導性のインピーダンスへ変成するワイヤにおいて、前記半導体素子に最も近いワイヤが電気的に接続する部品同士を直接的または間接的に接触した状態でパッケージ内部に配置した請求項1記載の半導体デバイス。 - 前記半導体素子のリアクタンス成分が0以下のインピーダンスを、前記ワイヤのインダクタンスと前記内部整合回路基板の整合回路により変成して、前記入力端子に接続される外部回路の出力インピーダンスまたは前記出力端子に接続される外部回路の入力インピーダンスと整合させるよう構成されており、
前記半導体素子のリアクタンス成分を0以下のインピーダンスから誘導性のインピーダンスへ変成する前記内部整合回路基板において、前記半導体素子に最も近い内部整合回路基板によって誘導性のインピーダンスへ変成された直後のワイヤが電気的に接続する部品同士を直接的または間接的に接触した状態でパッケージ内部に配置した請求項1記載の半導体デバイス。 - 前記内部整合回路基板は、
前記入力端子と前記半導体素子との間の入力側の信号伝送経路に配置され、入力側のインピーダンスを整合させるための入力側内部整合回路基板と、
前記半導体素子と前記出力端子との間の出力側の信号伝送経路に配置され、出力側のインピーダンスを整合させるための出力側内部整合回路基板と、を含み、
前記半導体素子と前記入力側内部整合回路基板とが直接的または間接的に接触し、
前記出力側内部整合回路基板と前記出力端子とが直接的または間接的に接触した状態でパッケージ内部に配置されている請求項1記載の半導体デバイス。 - 前記複数のワイヤにおいて、ワイヤ長が変化すると半導体デバイスの高周波特性が許容値を超えて変化する特性を有するワイヤ以外の少なくとも1つのワイヤによって電気的に接続されている部品同士が、離れた状態でパッケージ内部に配置されている請求項1に記載の半導体デバイス。
- 前記半導体素子としてトランジスタチップを有し、
前記トランジスタチップのゲートが入力端子側であって、
前記トランジスタチップのドレインが出力端子側である、請求項1から5のいずれか一項に記載の半導体デバイス。 - 半導体デバイスの高周波特性の指標が、前記入力端子における入力端若しくは出力端、または出力端子における入力端若しくは出力端のインピーダンスの不整合損失である請求項1から6のいずれか一項に記載の半導体デバイス。
- 半導体デバイスの高周波特性の指標が、入力端子と半導体素子との間または半導体素子と出力端子との間の信号伝送経路の伝送損失である請求項1から6のいずれか一項に記載の半導体デバイス。
- 半導体デバイスの高周波特性の指標が、入力端子から出力端子までの電力利得である請求項1から6のいずれか一項に記載の半導体デバイス。
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JP2017045957A (ja) * | 2015-08-28 | 2017-03-02 | 株式会社東芝 | 高周波半導体装置 |
JP2017054892A (ja) * | 2015-09-08 | 2017-03-16 | 株式会社東芝 | 高周波半導体装置 |
CN107871731A (zh) * | 2016-09-27 | 2018-04-03 | 三菱电机株式会社 | 半导体装置 |
JP2019186926A (ja) * | 2018-04-13 | 2019-10-24 | エヌエックスピー ユーエスエイ インコーポレイテッドNXP USA,Inc. | 組み合わせローパス・ハイパス段間回路を備えたハイブリッド電力増幅器回路またはシステムおよびその動作方法 |
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US11749578B2 (en) * | 2019-02-22 | 2023-09-05 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor module, power semiconductor module, and power electronic equipment using the semiconductor module or the power semiconductor module |
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JP2001230640A (ja) * | 2000-02-16 | 2001-08-24 | Mitsubishi Electric Corp | 半導体装置 |
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JPS61224344A (ja) | 1985-03-28 | 1986-10-06 | Sumitomo Electric Ind Ltd | 高周波集積デバイス用パツケ−ジ |
JP2685941B2 (ja) | 1989-12-14 | 1997-12-08 | 株式会社東芝 | マイクロ波半導体素子用キャリアプレート |
JPH06275736A (ja) | 1993-03-24 | 1994-09-30 | Mitsubishi Electric Corp | 半導体装置 |
JP5806464B2 (ja) * | 2010-02-03 | 2015-11-10 | 株式会社東芝 | 半導体素子収納用パッケージ及びそれを用いた半導体装置 |
JP5648295B2 (ja) * | 2010-02-19 | 2015-01-07 | 富士通株式会社 | インピーダンス変換器、集積回路装置、増幅器および通信機モジュール |
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JPH0774517A (ja) * | 1993-09-03 | 1995-03-17 | Toshiba Corp | マイクロ波半導体装置 |
JP2001230640A (ja) * | 2000-02-16 | 2001-08-24 | Mitsubishi Electric Corp | 半導体装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2017045957A (ja) * | 2015-08-28 | 2017-03-02 | 株式会社東芝 | 高周波半導体装置 |
JP2017054892A (ja) * | 2015-09-08 | 2017-03-16 | 株式会社東芝 | 高周波半導体装置 |
CN107871731A (zh) * | 2016-09-27 | 2018-04-03 | 三菱电机株式会社 | 半导体装置 |
CN107871731B (zh) * | 2016-09-27 | 2020-06-16 | 三菱电机株式会社 | 半导体装置 |
JP2019186926A (ja) * | 2018-04-13 | 2019-10-24 | エヌエックスピー ユーエスエイ インコーポレイテッドNXP USA,Inc. | 組み合わせローパス・ハイパス段間回路を備えたハイブリッド電力増幅器回路またはシステムおよびその動作方法 |
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US9668338B2 (en) | 2017-05-30 |
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JP6226143B2 (ja) | 2017-11-08 |
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