WO2014154978A1 - Procede de fabrication d'une structure composite - Google Patents
Procede de fabrication d'une structure composite Download PDFInfo
- Publication number
- WO2014154978A1 WO2014154978A1 PCT/FR2014/050666 FR2014050666W WO2014154978A1 WO 2014154978 A1 WO2014154978 A1 WO 2014154978A1 FR 2014050666 W FR2014050666 W FR 2014050666W WO 2014154978 A1 WO2014154978 A1 WO 2014154978A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- dielectric layer
- dielectric
- useful
- composite structure
- Prior art date
Links
- 239000002131 composite material Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 119
- 230000002093 peripheral effect Effects 0.000 claims abstract description 45
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 47
- 235000012239 silicon dioxide Nutrition 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- 239000003989 dielectric material Substances 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 7
- 230000003313 weakening effect Effects 0.000 claims description 7
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910000676 Si alloy Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 245
- 206010017076 Fracture Diseases 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 206010072395 Atypical fracture Diseases 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/62—Manufacture or treatment of semiconductor devices or of parts thereof the devices having no potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Definitions
- a manufacturing method, illustrated in FIG. 1, of a composite structure comprising from its rear face towards its front face a support substrate 1, a covering layer 2, at least one dielectric layer 3 and a useful layer 4, and known of the state of the art (see, for example, EP1780794), comprises the following steps:
- the present invention aims to overcome the aforementioned drawbacks, and relates to a method of manufacturing a composite structure comprising from its rear face to its front face a support substrate, a cover layer, at least one dielectric layer and a useful layer, said process comprising the following steps:
- steps b) and e) are performed so that the contour of the dielectric layer is inscribed in the contour of the contact surface, and step c) is performed so that the covering layer covers the peripheral surface of the dielectric layer.
- the support substrate comprises:
- steps b) and e) are executed so that the contour of the dielectric layer and the peripheral zone of the support substrate delimit a substantially annular surface with a width of between 105 and 150%, preferably between 1 and 140%, even more preferably between 1 and 15%.
- the donor substrate comprises at least one of the following materials: silicon, germanium, germanium silicon alloy.
- the donor substrate comprises an additional layer, the additional layer being in contact with the dielectric layer, the additional layer having the same chemical composition as the covering layer.
- the donor substrate comprises silicon
- the additional layer comprises silicon dioxide
- the dielectric layer comprises silicon nitride
- the covering layer comprises silicon dioxide.
- the invention also relates to a composite structure comprising from its rear face towards its front face a support substrate, a covering layer, at least one dielectric layer and a useful layer, the dielectric layer having:
- said composite structure being remarkable in that the covering layer covers in its entirety the peripheral surface of the dielectric layer, so that the useful layer and the covering layer encapsulate the dielectric layer.
- the transferred layer stack comprises a central portion and a peripheral portion.
- the peripheral portion comprises only the useful layer and the covering layer.
- the dielectric layer comprises silicon nitride.
- the useful layer covering the peripheral surface of the covering layer.
- the useful layer comprises monocrystalline silicon
- the additional layer comprises thermal silicon dioxide
- the dielectric layer comprises silicon nitride
- the covering layer comprises silicon dioxide
- FIG. 2 is a view of the front face of a composite structure obtained by a manufacturing method according to the techniques known from the prior art
- FIG. 3 is a sectional view of a substrate used in a manufacturing method according to the techniques known from the prior art
- FIGS. 4a and 4b are a schematic representation of a first embodiment of the invention.
- FIG. 5 is a cross-sectional view of a composite structure obtained by a manufacturing method according to the invention and having undergone an encapsulation treatment;
- steps b) and e) are carried out so that the contour Cz of the dielectric layer 30 is inscribed in the contour Cs of the contact surface 70, and step c ) is executed so that the cover layer 20 covers the peripheral surface of the dielectric layer 30.
- a step of determining the contour Cs of the contact surface can be performed prior to the implementation of the manufacturing method according to the invention.
- This determination step is particularly advantageous when it comes to implementing the method for manufacturing a plurality of composite structures.
- a plurality of donor substrates 50 and a plurality of support substrates 10 are chosen so that the contour Cs of the contact surface is substantially equivalent, or even identical, a composite structure to another.
- the donor substrates 50 of the plurality of donor substrates 50 are then chosen so as to have substantially equivalent or equal geometric characteristics.
- Another solution would be to perform the method of manufacturing a composite structure by omitting the formation of the dielectric layer 30, and measure at all points of the edge of the support substrate the width of the peripheral ring.
- a cover layer 20 is formed in overlap of the dielectric layer 30.
- the weakening zone 60 delimits, in the donor substrate 50, a useful layer 40, the useful layer being in contact with the dielectric layer 30.
- the useful layer 40 is intended to be transferred onto the support substrate 10.
- Introduced species may include at least one of the following species: hydrogen, helium.
- the hydrogen can be introduced with an energy of between 10 and 210 keV, and a dose of between 7x10 15 and 1 x 10 17 at / cm 2 .
- the fracture step f) may advantageously be thermal annealing carried out at a temperature of between 300 and 600 ° C.
- the composite structure comprises from its front face towards its rear face the useful layer 40, the dielectric layer 30, the covering layer 20, and the support substrate 10.
- the first embodiment is illustrated in Figures 4a and 4b.
- the dielectric layer 30 can be formed in two steps:
- Step b2) can advantageously be performed by a chemical etching solution.
- dielectric layers 30 may be formed successively.
- a dielectric layer 30 comprising silicon nitride, and another dielectric layer 30 comprising silicon dioxide.
- the chemical etching solution may be distributed by a nozzle on the edge of the donor substrate 50 in rotation, so as to etch the dielectric layer 30 only on the peripheral surface of the donor substrate 50 delimited by the edge of the donor substrate 10 and the contour cz.
- the additional layer 90 and the cover layer 20 comprise silicon oxide.
- the additional layer 90 is formed directly on the donor substrate 50, before the dielectric layer 30.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Micromachines (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG11201507963QA SG11201507963QA (en) | 2013-03-29 | 2014-03-21 | Process for manufacturing a composite structure |
US14/780,467 US9799549B2 (en) | 2013-03-29 | 2014-03-21 | Process for manufacturing a composite structure |
JP2016504722A JP6306684B2 (ja) | 2013-03-29 | 2014-03-21 | 複合構造の製造方法 |
RU2015141124A RU2645895C2 (ru) | 2013-03-29 | 2014-03-21 | Способ изготовления композитной структуры |
EP14718659.7A EP2979296A1 (fr) | 2013-03-29 | 2014-03-21 | Procede de fabrication d'une structure composite |
KR1020157030956A KR20150140313A (ko) | 2013-03-29 | 2014-03-21 | 합성 구조물의 제조 방법 |
CN201480018752.9A CN105074895A (zh) | 2013-03-29 | 2014-03-21 | 用于制造复合结构的方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1300738 | 2013-03-29 | ||
FR1300738A FR3003997B1 (fr) | 2013-03-29 | 2013-03-29 | Procede de fabrication d'une structure composite |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014154978A1 true WO2014154978A1 (fr) | 2014-10-02 |
Family
ID=48856695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/FR2014/050666 WO2014154978A1 (fr) | 2013-03-29 | 2014-03-21 | Procede de fabrication d'une structure composite |
Country Status (9)
Country | Link |
---|---|
US (1) | US9799549B2 (fr) |
EP (1) | EP2979296A1 (fr) |
JP (1) | JP6306684B2 (fr) |
KR (1) | KR20150140313A (fr) |
CN (1) | CN105074895A (fr) |
FR (1) | FR3003997B1 (fr) |
RU (1) | RU2645895C2 (fr) |
SG (1) | SG11201507963QA (fr) |
WO (1) | WO2014154978A1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3326818C2 (de) * | 1983-07-26 | 1986-11-06 | Rudolf 8729 Zeil Weigmann | Krückenpaar für Steh- und Gehbehinderte mit einer Sitzfläche |
US20180175008A1 (en) * | 2015-01-09 | 2018-06-21 | Silicon Genesis Corporation | Three dimensional integrated circuit |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2852143A1 (fr) | 2003-03-04 | 2004-09-10 | Soitec Silicon On Insulator | Procede de traitement preventif de la couronne d'une tranche multicouche |
EP1780794A1 (fr) | 2004-06-17 | 2007-05-02 | Shin-Etsu Handotai Company Limited | Procede de fabrication de plaquette liee |
US20080308897A1 (en) * | 2007-06-15 | 2008-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Substrate for manufacturing semiconductor device and manufacturing method thereof |
US20120001293A1 (en) * | 2010-06-30 | 2012-01-05 | Nadia Ben Mohamed | Semiconductor on glass substrate with stiffening layer and process of making the same |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003224247A (ja) * | 2002-01-29 | 2003-08-08 | Shin Etsu Handotai Co Ltd | Soiウエーハ及びsoiウエーハの製造方法 |
JP4854917B2 (ja) * | 2003-03-18 | 2012-01-18 | 信越半導体株式会社 | Soiウェーハ及びその製造方法 |
JP2006173354A (ja) * | 2004-12-15 | 2006-06-29 | Canon Inc | Soi基板の製造方法 |
US7781309B2 (en) * | 2005-12-22 | 2010-08-24 | Sumco Corporation | Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method |
CN101669193B (zh) * | 2007-04-27 | 2012-02-15 | 株式会社半导体能源研究所 | Soi衬底及其制造方法和半导体器件 |
JP5498670B2 (ja) * | 2007-07-13 | 2014-05-21 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法 |
TWI493609B (zh) * | 2007-10-23 | 2015-07-21 | Semiconductor Energy Lab | 半導體基板、顯示面板及顯示裝置的製造方法 |
FR2967295B1 (fr) * | 2010-11-05 | 2013-01-11 | Soitec Silicon On Insulator | Procédé de traitement d'une structure multicouche |
RU2469433C1 (ru) * | 2011-07-13 | 2012-12-10 | Юрий Георгиевич Шретер | Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты) |
-
2013
- 2013-03-29 FR FR1300738A patent/FR3003997B1/fr not_active Expired - Fee Related
-
2014
- 2014-03-21 CN CN201480018752.9A patent/CN105074895A/zh active Pending
- 2014-03-21 SG SG11201507963QA patent/SG11201507963QA/en unknown
- 2014-03-21 US US14/780,467 patent/US9799549B2/en active Active
- 2014-03-21 RU RU2015141124A patent/RU2645895C2/ru not_active IP Right Cessation
- 2014-03-21 WO PCT/FR2014/050666 patent/WO2014154978A1/fr active Application Filing
- 2014-03-21 KR KR1020157030956A patent/KR20150140313A/ko not_active Application Discontinuation
- 2014-03-21 EP EP14718659.7A patent/EP2979296A1/fr not_active Withdrawn
- 2014-03-21 JP JP2016504722A patent/JP6306684B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2852143A1 (fr) | 2003-03-04 | 2004-09-10 | Soitec Silicon On Insulator | Procede de traitement preventif de la couronne d'une tranche multicouche |
EP1780794A1 (fr) | 2004-06-17 | 2007-05-02 | Shin-Etsu Handotai Company Limited | Procede de fabrication de plaquette liee |
US20080308897A1 (en) * | 2007-06-15 | 2008-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Substrate for manufacturing semiconductor device and manufacturing method thereof |
US20120001293A1 (en) * | 2010-06-30 | 2012-01-05 | Nadia Ben Mohamed | Semiconductor on glass substrate with stiffening layer and process of making the same |
Also Published As
Publication number | Publication date |
---|---|
US20160042989A1 (en) | 2016-02-11 |
FR3003997B1 (fr) | 2015-03-20 |
CN105074895A (zh) | 2015-11-18 |
EP2979296A1 (fr) | 2016-02-03 |
SG11201507963QA (en) | 2015-10-29 |
US9799549B2 (en) | 2017-10-24 |
KR20150140313A (ko) | 2015-12-15 |
JP6306684B2 (ja) | 2018-04-04 |
RU2645895C2 (ru) | 2018-02-28 |
JP2016519431A (ja) | 2016-06-30 |
RU2015141124A (ru) | 2017-05-04 |
FR3003997A1 (fr) | 2014-10-03 |
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