WO2014136393A1 - Substrat traité et dispositif semi-conducteur l'utilisant - Google Patents

Substrat traité et dispositif semi-conducteur l'utilisant Download PDF

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WO2014136393A1
WO2014136393A1 PCT/JP2014/000897 JP2014000897W WO2014136393A1 WO 2014136393 A1 WO2014136393 A1 WO 2014136393A1 JP 2014000897 W JP2014000897 W JP 2014000897W WO 2014136393 A1 WO2014136393 A1 WO 2014136393A1
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Prior art keywords
processed substrate
equilateral triangle
protrusions
substrate
gan
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PCT/JP2014/000897
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English (en)
Japanese (ja)
Inventor
成仁 岡田
只友　一行
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国立大学法人山口大学
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Priority to JP2015504152A priority Critical patent/JPWO2014136393A1/ja
Publication of WO2014136393A1 publication Critical patent/WO2014136393A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a processed substrate and a semiconductor device using the processed substrate.
  • a semiconductor layer having a nonpolar surface can be crystal-grown on the substrate, and dislocations of the semiconductor layer to be crystal-grown on the substrate can be reduced. It has been known.
  • Patent Document 1 discloses a processed substrate in which a crystal growth surface of a sapphire substrate has an irregular structure by etching or the like.
  • Non-Patent Document 1 discloses a processed substrate in which a plurality of randomly arranged cone-shaped protrusions are formed on the substrate surface.
  • the present invention is a processed substrate in which a plurality of protrusions arranged to form an equilateral triangular lattice in a plan view are formed on a substrate surface, and a GaN crystal whose principal surface is c-plane can be grown on the substrate.
  • the plurality of protrusions are arranged such that three sides of an equilateral triangle in an equilateral triangular lattice constituted by the plurality of protrusions are relative to the a-axis of GaN when GaN whose principal surface is c-plane is grown on the substrate.
  • the smallest angle is 10 to 50 °.
  • a processed substrate having a plurality of protrusions formed so as to form an equilateral triangular lattice in a plan view is formed on the surface of the substrate, and a GaN crystal whose principal surface is c-plane is grown on the processed substrate.
  • a plurality of protrusions of the processed substrate, wherein three sides of an equilateral triangle in an equilateral triangle lattice constituted by the plurality of protrusions are formed on the GaN layer.
  • the smallest angle is arranged to be 10 to 50 °.
  • FIG. 1 is a longitudinal sectional view of a semiconductor light emitting device according to an embodiment. It is a top view of a part of a processed substrate.
  • FIG. 3 is a sectional view taken along line III-III in FIG. 2.
  • (A) is the 1st longitudinal cross-sectional view which shows the preparation methods of a wafer processing board
  • (A) is the 2nd longitudinal cross-sectional view which shows the preparation methods of a wafer processing board
  • A)-(d) is explanatory drawing which shows the manufacturing method of the semiconductor light-emitting device based on Embodiment.
  • FIG. 1 shows a semiconductor light emitting device 10 according to an embodiment.
  • the u-GaN layer 13, the n-type GaN layer 14, the multiple quantum well layer 15, and the p-type GaN layer 16 are sequentially stacked on the processing substrate 11, and An n-type electrode 17 is provided on the n-type GaN layer 14 exposed by etching, and a p-type electrode 18 is provided on the p-type GaN layer 16, for example, used as a light emitting diode It is.
  • 2 and 3 show the processed substrate 11.
  • 2 and 3 show crystal plane orientations using a sapphire processed substrate whose main surface is a-plane as an example (the same applies to FIGS. 4 and 5 below).
  • the processed substrate 11 is capable of crystal growth of GaN having a c-plane main surface on the substrate.
  • the processed substrate 11 include a sapphire processed substrate (PSS: Patterned Sapphire Substrate), a Si processed substrate, and a SiC processed substrate. More specifically, the main surface has a c-plane sapphire processed substrate, a-plane sapphire substrate, main surface is n-plane sapphire substrate, main surface is (111) Si substrate, main surface is (110) Si substrate, 3C-SiC substrate, 4C-SiC Examples thereof include a processed substrate, a 6H—SiC processed substrate, and a SiC processed substrate having a c-plane main surface.
  • a sapphire processed substrate having a c-plane principal surface is preferable.
  • the processed substrate 11 is formed in a rectangular plate shape in the state of the semiconductor light emitting element 10, and in this case, the vertical and horizontal dimensions are 200 to 1000 ⁇ m, and the thickness is 50 to 300 ⁇ m.
  • a plurality of protrusions 12 are formed on the substrate surface of the processed substrate 11.
  • Examples of the shape of the protrusion 12 include a pyramid, a truncated cone, a truncated pyramid, a cylinder, a prism, and a hemisphere in addition to the cone shown in FIGS.
  • the shape of the protrusion 12 preferably has a side surface that is inclined with respect to the main surface of the processed substrate 11. From this viewpoint, a cone, a pyramid, a truncated cone, a truncated pyramid, and a hemisphere are preferable.
  • the shape of the projection 12 is preferably a curved surface formed in the circumferential direction and having a side surface with a continuously changing crystal plane.
  • the shape of the protrusion 12 is preferably a cone, a truncated cone, or a hemisphere, and a cone is particularly preferable.
  • the “cone” and the “conical frustum” in the present application include those in which a contour of a side surface in a side view is a curved curve bulging outward.
  • the shape of the some protrusion 12 is the same, the thing from which a shape differs may be mixed.
  • the maximum outer diameter of the protrusion 12 (in the case of the conical protrusion 12, the diameter of the bottom surface) is preferably 1 ⁇ m or more, more preferably 2 ⁇ m or more.
  • the height of the protrusion 12 is preferably 0.5 ⁇ m or more, more preferably 1.5 ⁇ m or more.
  • the maximum outer diameter of the protrusion 12 is preferably larger than the height of the protrusion 12.
  • the dimension structure of the some protrusion 12 is the same, the thing from which a dimension structure differs may be mixed.
  • the plurality of protrusions 12 are arranged so as to form an equilateral triangular lattice in a plan view. That is, an equilateral triangular lattice is formed by combining the positions of the centers of gravity of the projections 12 in the plan view.
  • the length of one side of the equilateral triangle in the equilateral triangle lattice is preferably 2 ⁇ m or more, more preferably 3 ⁇ m or more.
  • the length of one side of the equilateral triangle is larger than the maximum outer diameter of the projection 12, and therefore, the pair of projections 12 at the two vertices included in the same equilateral triangle are arranged with a space between each other. .
  • the interval is, for example, 0.1 to 2.0 ⁇ m.
  • the plurality of protrusions 12 have crystal growth of GaN whose three sides of the equilateral triangle in the equilateral triangular lattice formed by the plurality of protrusions 12 are c-plane on the processed substrate 10.
  • the a-axis of GaN that is, the normal axis of the a-plane (in the case of the sapphire processed substrate 11 whose main surface is the c-plane, the m-axis on the main surface of the sapphire processed substrate, that is, the normal axis of the m-plane)
  • the smallest angle ⁇ among the angles ⁇ counterclockwise is 10 to 50 °.
  • This smallest angle ⁇ is preferably 20 ° or more and preferably 40 ° or less from the viewpoint of the effect of reducing the dislocation density of the semiconductor layer 13 formed on the processed substrate 11 described later. Most preferably, this smallest angle ⁇ is 30 °. It should be noted that the three sides of the equilateral triangle change every 60 ° with the side having the smallest angle ⁇ counterclockwise with respect to the a-axis of GaN. The above conditions for the processed substrate 11 are 10 ° ⁇ ⁇ ⁇ 50 °.
  • the arrangement density of the plurality of protrusions 12 is preferably 1 ⁇ 10 6 pieces / cm 2 or more, more preferably 1 ⁇ 10 7 pieces / cm 2 or more.
  • the exclusive area ratio of the main surface portion excluding the protrusions 12 in a plan view of the substrate surface of the processed substrate 11 is preferably 70% or less, more preferably 55% or less.
  • the constituent material of the u-GaN layer 13 is undoped GaN that is not doped with a dopant.
  • the u-GaN layer 13 is formed by crystal growth of GaN starting from a crystal plane included in the substrate surface on the processed substrate 11, and the main surface is a c-plane.
  • the thickness of the u-GaN layer 13 is, for example, 2 to 20 ⁇ m.
  • the processed substrate 11 is such that GaN whose principal surface is c-plane can grow on the substrate, and is disposed on the substrate surface so as to form an equilateral triangular lattice in plan view.
  • the plurality of protrusions 12 are formed, and the plurality of protrusions 12 are formed of GaN whose three sides of an equilateral triangle in the equilateral triangle lattice formed by them are c-plane GaN on the processed substrate 10. Is formed on the processed substrate 11 by arranging the smallest angle of 10 to 50 ° among the angles formed counterclockwise with respect to the a-axis of GaN when the crystal grows.
  • the dislocation density of the u-GaN layer 13 is reduced.
  • the dark spot density on the surface of the u-GaN layer 13 measured by the cathodoluminescence (CL) method is 1.15 ⁇ 10 8 pieces / cm 2 or less.
  • the number is preferably 1.00 ⁇ 10 8 pieces / cm 2 or less, and more preferably 9.90 ⁇ 10 7 pieces / cm 2 or less.
  • a low-temperature buffer layer having a thickness of about 20 to 30 nm may be provided between the processed substrate 11 and the u-GaN layer 13.
  • the constituent material of the n-type GaN layer 14 is GaN doped with an n-type dopant.
  • the n-type dopant include Si and Ge.
  • the concentration of the n-type dopant is, for example, 1.0 ⁇ 10 17 to 20 ⁇ 10 17 / cm 3 .
  • the n-type GaN layer 14 may be composed of a single layer, or may be composed of a plurality of layers having different n-type dopant types and concentrations.
  • the thickness of the n-type GaN layer 14 is 2 to 10 ⁇ m, for example.
  • the multiple quantum well layer 15 has an alternate stacked structure of well layers 15a and barrier layers 15b.
  • the number of well layers 15a and barrier layers 15b is, for example, 5 to 15.
  • Examples of the constituent material of the well layer 15a include InGaN and InGaAlN.
  • the thickness of the well layer 15a is, for example, 1 to 20 nm.
  • Examples of the constituent material of the barrier layer 15b include GaN, InGaN (however, larger than the band gap of the well layer 15a).
  • the thickness of the barrier layer 15b is, for example, 5 to 20 nm.
  • the constituent material of the p-type GaN layer 16 is GaN doped with a p-type dopant.
  • the p-type dopant include Mg and Cd.
  • the free hole concentration measured by the Hall effect measurement is, for example, 2.0 ⁇ 10 17 to 10 ⁇ 10 17 / cm 3 .
  • the p-type GaN layer 16 may be composed of a single layer, or may be composed of a plurality of layers having different types and concentrations of the p-type dopant.
  • the thickness of the p-type GaN layer 16 is, for example, 50 to 200 nm.
  • n-type electrode 17 examples include a laminated structure such as Ti / Al, Ti / Al / Mo / Au, and Hf / Au, or an alloy.
  • the thickness of the n-type electrode 17 is, for example, 10 nm / 500 nm in the laminated structure of Ti / Al.
  • Examples of the p-type electrode 18 include a laminated structure such as Pd / Pt / Au, Ni / Au, and Pd / Mo / Au, an alloy, or an oxide-based transparent conductive material such as ITO (indium tin oxide). It is done.
  • the thickness of the p-type electrode 18 is 10 to 200 nm for ITO, for example.
  • the processed substrate 11 is capable of crystal growth of GaN having a c-plane main surface on the substrate, and is positive on the substrate surface in plan view.
  • a plurality of projections 12 are formed so as to form a triangular lattice, and the three sides of the regular triangle in the regular triangular lattice constituted by the plurality of projections 12 are formed on the processed substrate 10.
  • the smallest angle among the angles formed counterclockwise with respect to the a-axis of GaN when the GaN crystal having the c-plane principal surface is grown is 10 to 50 °
  • the dislocation density of the u-GaN layer 13 which is a semiconductor layer formed on the processed substrate 11 is reduced, and accordingly, the n-type GaN layer 14, the multiple quantum well layer 15, and the p-type GaN layer formed thereon. 16 semiconductors It becomes the crystallinity of the layer is excellent. As a result, it is possible to improve the luminous efficiency.
  • a wafer processed substrate 11 ′ (processed substrate 11) is manufactured, and a u-GaN layer 13, an n-type GaN layer 14 (Si-doped), and a light emitting layer are formed thereon.
  • the multiple quantum well layer 15 well layer 15a: InGaN, barrier layer 15b: GaN
  • the p-type GaN layer 16 (Mg doped) are formed in order
  • the n-type GaN layer 14 and the p-type GaN layer 16 are formed.
  • the n-type electrode 17 and the p-type electrode 18 are formed respectively.
  • a wafer W having a c-plane main surface is prepared.
  • the wafer W has a thickness of 0.3 to 3.0 mm and a diameter of 50 to 300 mm, although it varies depending on the diameter. In the case of a wafer W having a diameter of 50 mm, 5000 to 12000 semiconductor light emitting elements 10 can be formed on one wafer W.
  • a protrusion 12 is formed on the surface of the wafer W to produce a wafer processing substrate 11 '.
  • an equilateral triangular lattice is formed on the surface of the wafer W by the photoresist R by a photolithography process.
  • the sapphire processed substrate 11 in which the three sides of the equilateral triangle are grown on the surface of the wafer W, and the GaN having the c-plane as the main surface is grown on the surface.
  • the angles formed counterclockwise with respect to the m-axis on the main surface of the sapphire substrate a plurality of dots arranged so that the smallest angle is 10 to 50 ° is patterned. This angle can be arbitrarily set by rotating the wafer W in-plane with respect to the fixed photomask.
  • the photoresist R a positive type can be suitably used.
  • the diameter of the dot of the photoresist R is, for example, 0.5 to 4 ⁇ m and the thickness is 0.5 to 4 ⁇ m, for example, although it depends on the size of the projection 12 to be formed.
  • the inter-dot distance of the photoresist R is, for example, 0.5 to 4 ⁇ m although it depends on the size of the projection 12 to be formed.
  • the photoresist R is pre-baked before exposure / development and post-baked after exposure / development.
  • the pre-baking and post-baking temperatures are, for example, 80 to 130 ° C. In post-baking, the dots of the photoresist R may be thermally deformed into a dome shape by setting the temperature higher.
  • the surface of the wafer W is subjected to reactive ion etching by inductively coupled plasma (Inductive Coupled Plasma Reactive Ion Etching).
  • the protrusion 12 is formed by etching.
  • the portion of the surface of the wafer W where the photoresist R is not provided is etched, while the portion where the photoresist R is provided remains and is formed on the protrusion 12. If the etching conditions are adjusted, the photo The frustoconical protrusions 12 with the resist R remaining on the top surface can be formed, or the conical protrusions 12 can be formed by etching enough to remove the photoresist R.
  • the etching time is, for example, 1 to 30 minutes.
  • the antenna power is, for example, 100 to 1000 W
  • the bias power is, for example, 50 to 500 W.
  • the pressure is, for example, 0.05 to 0.8 Pa.
  • As the etching gas various halogen-based gases such as Cl 2 and BCl 3 and Ar gas can be used.
  • MOVPE metal organic vapor phase epitaxy
  • MBE molecular beam epitaxy
  • HVPE hydride vapor phase epitaxy
  • metalorganic vapor phase epitaxy is the most common.
  • the MOVPE apparatus used for forming the u-GaN layer 13 and the like includes a wafer transfer system, a wafer heating system, a gas supply system, and a gas exhaust system that are electronically controlled.
  • the wafer heating system is composed of a thermocouple, a resistance heater, and a carbon or SiC susceptor provided thereon.
  • the MOVPE apparatus is configured to grow a semiconductor crystal with a reactive gas on a wafer processing substrate 11 ′ set on a susceptor of a quartz tray to be conveyed.
  • the wafer processing substrate 11 ′ having the protrusions 12 is set on the quartz tray so that the surface on which the protrusions 12 are formed faces upward, and then the wafer processing substrate 11 ′ is 1050 to 1150 ° C.
  • the pressure in the reaction vessel is set to 10 to 100 kPa, and H 2 is circulated as a carrier gas in a flow channel installed in the reaction vessel, and this state is maintained for several minutes to maintain the wafer processing substrate 11 ′. Perform thermal cleaning.
  • the temperature of the wafer processing substrate 11 ′ is set to 1050 to 1150 ° C.
  • the pressure in the reaction vessel is set to 10 to 100 kPa
  • the carrier gas H 2 is set to 10 slm (slm is 25 ° C. and 1 atm at 1 atmosphere).
  • a group V element supply source (NH 3 ) and a group III element supply source (TMG) are supplied as reaction gases to the respective supply flow rates of 0.1 to The flow rate is 5 slm and 50 to 150 ⁇ mol / min.
  • undoped GaN grows on the substrate surface of the wafer processing substrate 11 ′, and as shown in FIG. 6A, the u-GaN layer 13 whose principal surface is the c-plane is formed on the wafer processing substrate 11 ′. It is formed.
  • a low-temperature buffer layer may be formed on the wafer processing substrate 11 ′ before forming the u-GaN layer 13.
  • the temperature of the wafer processing substrate 11 ′ is set to 400 to 500 ° C., and GaN is crystal-grown. Just do it.
  • n-type GaN layer- The pressure in the reaction vessel is set to 10 to 100 kPa, and the carrier gas H 2 is circulated in the reaction vessel at a flow rate of 5 to 15 slm, and there as a reaction gas, a group V element supply source (NH 3 ), a group III Element supply source 1 (TMG) and n-type doping element supply source (SiH 4 ) are supplied at a supply flow rate of 0.1 to 5 slm, 50 to 150 ⁇ mol / min, and 1 to 5 ⁇ 10 ⁇ 3 ⁇ mol / min, respectively. Let it flow.
  • NH 3 group V element supply source
  • TMG group III Element supply source 1
  • SiH 4 n-type doping element supply source
  • the n-type GaN crystal grows continuously on the u-GaN layer 13 to form the n-type GaN layer 14.
  • the temperature of the wafer processing substrate 11 ′ is set to about 800 ° C.
  • the pressure in the reaction vessel is set to 10 to 100 kPa
  • the carrier gas N 2 is allowed to flow through the reaction vessel at a flow rate of 5 to 15 slm, and as a reaction gas there.
  • Group V element supply source (NH 3 ), Group III element supply source 1 (TMG), and Group III element supply source 2 (TMI) are supplied at a flow rate of 0.1 to 5 slm, 5 to 15 ⁇ mol / min, And 2 to 30 ⁇ mol / min.
  • InGaN crystal grows continuously on the n-type GaN layer 14 to form the well layer 15a.
  • a group V element supply source (NH 3 ) and a group III element supply source (TMG) are flowed so that the respective supply flow rates are 0.1 to 5 slm and 5 to 15 ⁇ mol / min.
  • NH 3 group V element supply source
  • TMG group III element supply source
  • the multiple quantum well layer 15 is formed by alternately forming the well layers 15a and the barrier layers 15b as shown in FIG. 6C.
  • the emission wavelength of the multiple quantum well layer 15 depends on the well width of the well layer 15a (the thickness of the well layer 15a) and the InN mixed crystal ratio, and the higher the InN mixed crystal ratio, the longer the emission wavelength.
  • the InN mixed crystal ratio is determined by the TMI molar flow rate / (TMG molar flow rate + TMI molar flow rate) and the growth temperature.
  • the temperature of the wafer processing substrate 11 ′ is set to 1000 to 1100 ° C.
  • the pressure in the reaction vessel is set to 10 to 100 kPa
  • the carrier gas H 2 is circulated in the reaction vessel at a flow rate of 5 to 15 slm.
  • a group V element supply source (NH 3 ), a group III element supply source 1 (TMG), and a p-type doping element supply source (Cp 2 Mg) are supplied at a supply flow rate of 0.1 to 5 slm, 50 It is made to flow so that it may become -150 micromol / min and 0.03-30 micromol / min.
  • the p-type GaN crystal grows continuously on the multiple quantum well layer 15 to form the p-type GaN layer 16.
  • n-type GaN layer 14 is exposed by partially reactive ion etching the wafer processing substrate 11 'on which the u-GaN layer 13 and the like are laminated, vacuum deposition, sputtering, CVD (Chemical Vapor Deposition), etc.
  • the n-type electrode 17 and the p-type electrode 18 are formed on the n-type GaN layer 14 and the p-type GaN layer 16, respectively.
  • the wafer processing substrate 11 ′ is cleaved to be divided into individual semiconductor light emitting elements 10.
  • the semiconductor light emitting element 10 is used as an example.
  • the semiconductor light emitting element 10 is not particularly limited thereto, and may be other semiconductor devices such as an electronic device.
  • the u-GaN layer 13 is formed as a semiconductor layer on the processed substrate 11.
  • the present invention is not limited to this, and an AlGaN layer, an InGaN layer, or the like is formed as the semiconductor layer. It may be a configuration.
  • a positive type photoresist was used.
  • the diameter of the photoresist dots was 2 ⁇ m and the thickness was 2 ⁇ m.
  • the distance between the dots of the photoresist was 3 ⁇ m.
  • the pre-baking and post-baking temperatures were 130 ° C.
  • the exposure amount was 90 mJ / cm 2 .
  • the etching time was 20 minutes.
  • the antenna power was 500 W and the bias power was 350 W.
  • the pressure was 0.6 Pa.
  • Ar, Cl 2 , and BCl 3 were used, and the flow rates were 20 sccm, 30 sccm, and 5 sccm, respectively.
  • the maximum outer diameter of the protrusion was 2.1 ⁇ m, the height was 1.1 ⁇ m, and the inclination angle of the side surface with respect to the main surface of the sapphire substrate was 59 °.
  • the length of one side of the equilateral triangle in the equilateral triangle lattice was 3.0 ⁇ m. Therefore, the distance between a pair of adjacent protrusions was 0.9 ⁇ m.
  • the exclusive area ratio of the main surface portion excluding protrusions in plan view of the substrate surface of the processed substrate was 54.7%.
  • sapphire processed substrates having an angle ⁇ of 30 ° and 45 ° were prepared. Further, as a reference, a sapphire processed substrate having an angle ⁇ of 0 ° (60 °) was also produced.
  • FIG. 10 shows the relationship between the angle ⁇ and the dark spot density on the surface of the GaN layer formed on the sapphire processed substrate.
  • the dark spot density was 1.19 ⁇ 10 8 pieces / cm 2 .
  • the dark spot density was 9.90 ⁇ 10 7 pieces / cm 2 .
  • the dark spot density was 9.69 ⁇ 10 7 pieces / cm 2 .
  • the dark spot density was 1.10 ⁇ 10 8 pieces / cm 2 .
  • the angle ⁇ is preferably 10 to 40 °, more preferably 15 to 35 °, further preferably 25 to 35 °, and most preferably 30 °. .
  • the present invention is useful for a processed substrate and a semiconductor device using the processed substrate.
  • Photoresist 10 Semiconductor light emitting element 11 Processing substrate 11 ′ Wafer processing substrate 12 Protrusion 13 u-GaN layer 14 n-type GaN layer 15 Multiple quantum well layer 15a Well layer 15b Barrier layer 16 p-type GaN layer 17 n-type electrode 18 p-type electrode

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Abstract

L'invention concerne un substrat traité (11), la surface principale de celui-ci étant un plan c, et une pluralité de saillies (12) disposée de façon à constituer un réseau triangulaire régulier dans une vue du plan étant formée sur la surface du substrat. La pluralité de saillies (12) est disposée de telle sorte que le plus petit angle parmi les angles que les trois côtés, d'un triangle régulier dans le réseau triangulaire régulier constitué par la pluralité de saillies, forme dans le sens inverse des aiguilles d'une montre avec l'axe a de GaN lorsque le GaN, dont la surface principale est un plan c, a été formé par croissance cristalline sur le substrat, devient entre 10° et 50°.
PCT/JP2014/000897 2013-03-08 2014-02-21 Substrat traité et dispositif semi-conducteur l'utilisant WO2014136393A1 (fr)

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Cited By (4)

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