Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
  • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C16/40—Oxides
  • C23C16/409—Oxides of the type ABO3 with A representing alkali, alkaline earth metal or lead and B representing a refractory metal, nickel, scandium or a lanthanide
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
  • C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
  • C23C18/12—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material
  • C23C18/1204—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material inorganic material, e.g. non-oxide and non-metallic such as sulfides, nitrides based compounds
  • C23C18/1208—Oxides, e.g. ceramics
  • C23C18/1216—Metal oxides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
  • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
  • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers

Definitions

• This relates to integrated circuit manufacture and, more specifically, to formation of capacitor plates in memory devices such as ferroelectric memories.
• MOS metal-oxide-semiconductor
• CMOS logic and memory devices are prevalent in modern electronic devices and systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration.
• CMOS complementary metal-oxide-semiconductor
• those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power.
• the ability to store memory and logic states in a non-volatile fashion is very desirable.
• various technologies for constructing non-volatile devices have been developed in recent years.
• a recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead-zirconium-titanate (PZT) or strontium- bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors.
• PZT lead-zirconium-titanate
• SBT strontium- bismuth-tantalate
• Hysteresis in the charge-vs. -voltage (Q-V) characteristic based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors.
• conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits.
• Non-volatile solid-state read/write random access memory (RAM) devices based on ferroelectric capacitors such memory devices commonly referred to as ferroelectric RAM, FeRAM or FRAM devices, have been implemented in many electronic systems, particularly portable electronic devices and systems. FRAMs are especially attractive in implantable medical devices, such as pacemakers and defibrillators.
• Various memory cell architectures including ferroelectric capacitors are known in the art, including the well-known 2T2C (two transistor, two capacitor) cells.
• FRAM cell is based on the well-known 6T CMOS static RAM cell, which operates as an SRAM cell during normal operation, but in which ferroelectric capacitors coupled to each storage node can be programmed with the stored data state to preserve memory contents in non-volatile fashion. Ferroelectric capacitors are also implemented in some integrated circuits as programmable analog capacitors.
• FIG. 1 illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor.
• the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a coercive voltage +V a , the capacitor polarizes into the state. According to this characteristic, once polarized to the state, so long as voltage V remains above coercive voltage -Vp, the capacitor exhibits a stored charge of +Qi. Conversely, if the voltage V applied across the capacitor plates is more negative than coercive voltage -Vp, the capacitor is polarized into the state, and will exhibit a stored charge of -Q 2 for applied voltage V below +V a .
• ferroelectric capacitors An important characteristic of ferroelectric capacitors, for purposes of nonvolatile storage in integrated circuits, is the difference in capacitance that a ferroelectric capacitor exhibits between its polarized states.
• the logic state stored by a memory cell is read by interrogating the capacitance, and thus the polarized state, of its ferroelectric capacitor. Referring to the example of FIG.
• a relatively large value of switching polarization Psw means will be reflected in a large value of capacitance C(-l) relative to the value of capacitance C(+l).
• switching polarization Psw is relatively low (and assuming that coercive voltages +V a and -Vp remain constant)
• the capacitance line C(-l) will have a flatter slope, reflecting a lower capacitance.
• the difference in capacitances between the two polarization states of the capacitor thus reduces as switching polarization parameter Psw decreases, which appears as a poorer read margin for the corresponding FRAM cell.
• a higher value for switching polarization parameter Psw corresponds to an improved read margin for the FRAM cell.
• the parameter of switching polarization Psw depends strongly on the manner in which the ferroelectric capacitor dielectric material is formed, particularly for the case of lead-zirconium-titanate (PZT).
• PZT lead-zirconium-titanate
• MOCVD metalorganic chemical vapor deposition
• the MOCVD conditions of low precursor flow (the collective flow rate of the lead, zirconium, and titanium precursors, and the appropriate solvent of less than about 1.1 ml/min) and a process temperature below about 640 degC can provide a thin PZT film that, as the dielectric of a ferroelectric capacitor, can exhibit a relatively high switching polarization Psw.
• MOCVD deposition of PZT necessarily results in a very low deposition rate and a corresponding high consumption of the precursors.
• the resulting low manufacturing throughput and high material costs increase the manufacturing cost of the FRAM devices.
• the deposition rate of MOCVD PZT at this low temperature cannot be increased by increasing the precursor flow rate, because of the inability to closely control the relative nucleation of lead, zirconium, and titanium at such higher flow rates under low temperature.
• the relative nucleation of lead and lead oxide tends to increase under low temperature, absent close control of the individual precursor flows.
• the increased nucleation of lead forms an undesired second phase with a rough spatial morphology, appearing as a "haze" in the deposited film when viewed using light-scattering techniques.
• This roughness of the "haze” defects is also reflected in degraded electrical performance of the ferroelectric elements, typically as increased leakage, and thus reduced electrical yield and poorer device performance.
• Disclosed embodiments provide a method of depositing lead-zirconium- titanate (PZT) ferroelectric material in the manufacture of an integrated circuit structure, and a structure so manufactured, in which high-polarization ferroelectric material is deposited at a relative high rate.
• PZT lead-zirconium- titanate
• Disclosed embodiments provide such a method and structure in which the formation of haze defects is avoided.
• Disclosed embodiments provide such a method and structure that provides very thin, high quality, ferroelectric films suitable for use in modern deep submicron integrated circuits.
• PZT ferroelectric material may be implemented by way of a plurality of metalorganic chemical vapor deposition (MOCVD) steps performed in sequence.
• a first deposition step forms a first layer of PZT over an electrode layer under low deposition rate conditions, followed by the deposition of a second layer of PZT under higher deposition rate conditions.
• FIG. 1 is a hysteresis diagram illustrating the electrical behavior of a conventional ferroelectric capacitor.
• FIG. 2 is a cross-sectional view of a portion of an integrated circuit including a ferroelectric capacitor at a selected stage of manufacture according to embodiments of this invention.
• FIG. 3 is a schematic diagram illustrating a chemical vapor deposition system for forming a ferroelectric film according to disclosed embodiments.
• FIG. 4 is a flow diagram illustrating a process of forming a ferroelectric capacitor according to disclosed embodiments.
• FIGS. 5a through 5d are flow diagrams illustrating a process of depositing lead-zirconium-titanate (PZT) ferroelectric material according to respective ones of the disclosed embodiments.
• PZT lead-zirconium-titanate
• FIGS. 6a and 6b are cross-sectional views of a portion of an integrated circuit including a ferroelectric film deposited according to respective ones of the disclosed embodiments.
• FIG. 2 illustrates a portion of an integrated circuit including a portion of a ferroelectric random access memory (FRAM), as may be constructed using embodiments disclosed in this specification.
• ferroelectric capacitor 15 and metal-oxide- semiconductor (MOS) transistor 17 are disposed at or near a semiconductor surface of a semiconductor substrate.
• MOS metal-oxide- semiconductor
• these embodiments may be used in the fabrication of integrated circuits in which a semiconductor layer itself overlies an insulator layer, such as according to a silicon-on-insulator (SOI) technology, as known in the art.
• SOI silicon-on-insulator
• isolation dielectric structures 11, gate electrode 16, and n-type source/drain regions 14 are disposed at or near the surface of substrate 10, in the conventional manner for MOS integrated circuits, as well- known in the art.
• N-channel MOS transistor 17 in the example of FIG. 2 includes n-type source/drain regions 14 at the surface of p-type substrate 10 (or of a p-type well formed into substrate 10, as the case may be), with gate electrode 16 overlying a channel region between source/drain regions 14, and separated from the channel region by a gate dielectric, as conventional.
• Interlevel dielectric 12 is disposed over transistor 17, with conductive plug 13 disposed in a contact opening through interlevel dielectric 12 to provide a conductive connection between one of source/drain regions 14 of transistor 17 and lower plate 20a of ferroelectric capacitor 15.
• ferroelectric capacitor 15 is formed of a ferroelectric sandwich stack of conductive plates 20a, 20b, between which ferroelectric material 22 is disposed.
• Lower plate 20a is formed at a location overlying conductive plug 13, as shown in FIG. 2, so as to be in electrical contact with the underlying source/drain region 14 by way of conductive plug 13.
• Conductive plates 20a, 20b are typically formed of the same conductive material or materials as one another. Often, conductive plates 20a, 20b are formed as stacks of conductive metals, metal oxides, and the like.
• one such stack forming lower plate 20a may include a conductive diffusion barrier (e.g., TiN, TiAlN, TiAlON, TaSiN, CrN, HfN, TaN, HfAlN, CrAlN, TiSiN, CrSiN) in contact with conductive plug 13, an intermediate layer of a noble metal (e.g., Ru, Pt, Ir, Rh, Pt, Pd, Au) or noble metal oxide (e.g., RuOx, IrOx, PdOx) disposed over the diffusion barrier, and a conductor such as iridium (Ir) or strontium ruthenate (SrRu0 3 ) overlying the intermediate layer and in contact with the ferroelectric material 22.
• a conductive diffusion barrier e.g., TiN, TiAlN, TiAlON, TaSiN, CrN, HfN, TaN, HfAlN, CrAlN, TiSiN, CrSiN
• Lower conductive plate 20a and upper conductive plate 20b are formed of the same material or materials, for purposes of symmetry, simplicity of the manufacturing flow, and improved ferroelectric polarization performance. In that case, the order in which the various materials of upper conductive plate 20b are formed will be reverse that of lower plate 20a. Lower conductive plate 20a and upper conductive plate 20b are typically formed by way of sputter deposition.
• ferroelectric material 22 is lead-zirconium-titanate, commonly referred to as PZT. It is desirable for ferroelectric material 22 in capacitor 15 to be as thin as practicable, for purposes of electrical performance (e.g., capacitance), and for consistency with the deep sub-micron features used to realize modern integrated circuits. According to the embodiments disclosed in this specification, PZT ferroelectric material 22 is deposited by way of metalorganic chemical vapor deposition.
• FIG. 3 schematically illustrates the functional arrangement of an example of
• CVD system 5 for forming PZT films by liquid delivery metalorganic chemical vapor deposition according to embodiments of this invention.
• This example of CVD system 5 described in this specification and in U.S. Patent No. 6,730,354, incorporated herein by reference, is provided by way of context to the disclosed embodiments, as an example of a suitable system for depositing PZT ferroelectric material 22 according to those embodiments. It is of course contemplated that those skilled in the art having reference to this specification will readily comprehend that variations and alternatives to some or all of the elements of CVD system 5, and other types of MOCVD systems, may alternatively be used, such variations and alternatives remaining within the scope of the claims below.
• CVD system 5 includes chemical vapor deposition (CVD) chamber 13 coupled to dual precursor ampoule liquid delivery system 25 and vaporizer 27.
• CVD chamber 13 may, for example, be implemented as a conventional commercially available CVD chamber for wafers of the desired diameter (e.g., 200 mm, 300 mm, etc.).
• CVD chamber 13 includes gas distribution manifold 19 and showerhead 21, configured to introduce PZT precursor vapor into CVD chamber 13 under the appropriate conditions, from which PZT ferroelectric material 22 precipitates onto an exposed surface of wafer 23.
• Wafer 23 is supported by heated susceptor 24, which is spaced apart from showerhead 21, typically by several millimeters.
• the exposed surface of wafer 23 may correspond to the top surface of a silicon wafer, a layer of silicon dioxide formed on a silicon wafer, gallium arsenide, magnesium oxide, sapphire, or the top surface of a multilayer structure that includes, for example, a complex integrated circuit that is formed on a semiconductor wafer.
• wafer 23 when placed into chamber 13 corresponds to substrate 10 after the formation of transistor 17, interlevel dielectric 12, conductive plug 13, and lower plate 20a; at that stage of manufacture, the conductive layer or layers making up lower plate 20a extend across the entire surface of wafer 23, according to conventional processes in which the plates 20a, 20b and PZT ferroelectric material 22 are etched as a stack.
• liquid delivery system 25 includes solvent ampoule 31, and source reagent ampoules 26, 28, 30 containing respective metalorganic compounds or mixtures of the component metals needed to form PZT films.
• source reagent ampoule 26 will contain the lead precursor
• source reagent ampoule 28 will contain the zirconium precursor
• source reagent ampoule 30 will contain the titanium precursor; alternatively, one ampoule may contain a mixture of the zirconium and titanium precursors, or further in the alternative, a single ampoule may contain the precursors for all three of lead, zirconium, and titanium. Examples of particular precursors for lead, zirconium, and titanium, and of the solvent to be introduced into chamber 13 for deposition, are described in the above-incorporated U.S. Patent No. 6,730,354.
• source reagent and solvent ampoules 26, 28, 30, 31 are coupled to respective liquid flow controllers 32, 34, 36, 39, which are configured to meter precise quantities of fluid into manifolds 38, 40, 42, 43, respectively.
• the metered solvent and metalorganic mixtures are delivered to final mixing chamber 44, for mixing into a liquid PZT precursor composition.
• This precursor composition is introduced into vaporizer 27 for vaporizing into a precursor vapor, for example by flash vaporization on a vaporization element heated to a suitable temperature.
• Gas flow controller 46 controls the flow of a carrier gas (e.g., argon gas or helium gas), which transports the precursor vapor into CVD chamber 13 via valve 47.
• a carrier gas e.g., argon gas or helium gas
• An additional push gas source (e.g., argon or helium) also may be connected directly to vaporizer 27 via gas flow controller 45.
• Gas flow controllers 48, 49, 50 meter precise quantities of oxidizing co-reactant gases (e.g., 0 2 , 0 3 , N 2 0, or a combination of one or more of these gases) into gas distribution manifold 19, where the oxidizing gases mix with the precursor vapor before being introduced into CVD chamber 13.
• CVD system 5 also includes components used to evacuate and purge of chamber 13. As described in the above-incorporated U.S. Patent No. 6,730,354, by way of example, these components include purge gas flow control 60 and purge valve 47, and evacuation system 52 that includes cold traps 54, 56, 58, and valve 51. Other conventional features may be included in CVD system 5 for purposes of PZT deposition according to the embodiments disclosed in this specification, including those described in further detail in the above-incorporated U.S. Patent No. 6,730,354.
• a method of fabricating an integrated circuit including one or more ferroelectric capacitors 15 such as shown in FIG. 2 is illustrated by the process 62 shown in FIG. 4.
• transistors such as transistor 17 are formed at or near the semiconductor surface of substrate 10 or other support body, in the conventional manner.
• isolation dielectric structures 11, the appropriate doped wells (not shown), a gate dielectric layer, gate electrodes 16, and source/drain regions 14, among other structures, are formed at or near the surface of substrate 10 according to conventional MOS processes.
• gate electrode 16 may be formed in the conventional manner by deposition and photolithographic patterning and etch of polysilicon material to define gate electrode 16 overlying a gate dielectric, with n-type source/drain regions 14 formed on either side of gate electrode 16 by ion implantation and subsequent activation anneal, in the well-known self-aligned manner.
• first interlevel dielectric 12 is then deposited over the transistors such as transistor 17 that were formed in process 62, for example by way of chemical vapor deposition, followed by planarization if desired.
• contact openings i.e., vias
• conductive plugs 13 are formed into those openings in the conventional manner to provide an electrical contact between one of source/drain regions 14 of MOS transistor 17 and the eventual ferroelectric capacitor 15.
• Conductive plug 13 may be formed of a metal such as tungsten, titanium, and the like, or an alloy thereof,
• ferroelectric capacitor 15 is then formed in this example.
• one or more conductive layers are formed over first interlevel dielectric layer 12 and conductive plugs 13, to serve as the lower conductive plate layer for capacitor 15.
• process 68 will be performed by sputter deposition of one or more layers of the desired conductive material, such as one or more of strontium ruthenate (SrRu0 3 ), iridium (Ir), iridium oxide (Ir0 2 ), platinum (Pt), and other metals and metal oxides suitable for use in this application, along with the appropriate barrier metal layers disposed between the lower conductive plate layer and underlying structures, as conventional in the art.
• the particular conductors deposited in process 68 are selected for compatibility with the PZT ferroelectric material to be deposited over this layer, with the temperatures and other conditions that the structure will be exposed to in the remainder of the manufacturing process.
• PZT ferroelectric material 22 is deposited overall by way of metalorganic chemical vapor deposition, in process 70.
• process 70 will be carried out by way of a chemical vapor deposition system such as CVD system 5 described above, or variations and alternatives thereto. These systems are typically single-wafer systems, and as such it is contemplated that the necessary and conventional evacuation and purge operations will be performed as appropriate for the particular system prior to the performing of PZT deposition process 70 upon a given wafer. Alternatively, if the CVD system being used is arranged to accept multiple wafers, more than one such wafer may be subjected to process 70 simultaneously.
• process 70 will be described with reference to the example of single-wafer CVD system 5 described above relative to FIG. 3, it being contemplated that those skilled in the art having reference to this specification will be readily able to adapt the particular operations as appropriate for such variations in the CVD system presented in each specific implementation, without undue experimentation.
• deposition process 70 will first be described in a generalized sense. As shown, process 70 begins with the placement of wafer 23, including substrate 10 and the previously formed elements as discussed above, into chamber 13, and the heating of the interior of chamber 13 and wafer 23 to the desired temperature, in process 72. Wafer 23 is typically preheated during a preheating period prior to deposition, for example with part of this preheating performed prior to its placement on its placement on heated susceptor 24.
• the above-incorporated U.S. Patent No. 6,730,354 describes one approach for gradually heating wafer 23 to the desired processing temperature within chamber 13.
• process 72 raises chamber 13 and wafer 23 to the desired temperature prior to the initiation of deposition process 74.
• first deposition process 74 is performed by introducing into chamber 13 precursors and solvent at the desired flow rate, and oxidizing gas of the desired mixture, where reactions among those constituents result in the deposition of PZT onto wafer 23.
• the precursor and solvent flow rate, the oxidizing gas composition, and the conditions present in chamber 13, are selected for this process 74 to result in a relatively low deposition rate of the PZT material onto wafer 23.
• process 74 is continued for a first selected time duration. As a result of process 74, a first, lower, portion of the layer of PZT ferroelectric material 22 is deposited.
• second deposition process 76 is then performed to continue the deposition of the PZT layer.
• deposition process 76 is performed by introducing precursors, solvent, and oxidizing gas of a desired mixture into chamber 13.
• the deposition conditions e.g., precursor flow rate, oxidizing gas composition, temperature, etc.
• high deposition rate process 76 continues for a second selected time duration, resulting in the deposition of a second, upper, portion of the layer of PZT ferroelectric material 22.
• process 76 completes the deposition of PZT ferroelectric material 22 to its full thickness.
• the deposition conditions during process 76 differ from those during process 74, so that the deposition rate in process 76 is higher than that in process 74.
• embodiments of the invention may utilize different approaches, and combinations of those approaches, to implement deposition processes 74, 76 at differing deposition rates.
• PZT deposition process 70 begins with process 72, in which wafer 23 is placed into chamber 13, and chamber 13 is heated to the desired processing temperature.
• the processing temperature for CVD is typically measured at the susceptor upon which the wafer is placed for deposition, at which temperature sensors can be installed.
• the susceptor temperature is commonly used in the art to refer to the processing temperature; the actual temperature at the surface of the wafer will generally be less than this temperature of the susceptor, for example on the order of 20 degC. This specification will follow that convention, and will refer to the susceptor temperature as the processing temperature in describing the embodiments of process 70.
• process 72 heats chamber 13 to a temperature, at susceptor 24, below about 640 degC, for example at about 635 degC.
• heating process 72 is performed with wafer 23 in chamber 13, and may be performed in multiple stages (e.g., including a preheating step in which wafer 23 is supported above susceptor 24, as described in the above -incorporated U.S. Patent No. 6,730,354).
• Other conditions at chamber 13, such as pressure (e.g., at 2 torr), as suitable for CVD of PZT are also effected in this process 72.
• deposition process 74a is then performed to deposit a first thickness of PZT ferroelectric material 22 at the surface of the layer of lower conductive plate 20a material, with the deposition occurring at a relatively low deposition rate.
• process 74a is performed by introducing the lead, zirconium, and titanium precursors, and the solvent, at a relatively low flow rate.
• the flow rates for liquid precursor reactants are referred to by fluid flow units, such as ml/min.
• low deposition rate process 74a is carried out by introducing all precursors (lead, zirconium, and titanium) and the solvent from ampoules 26, 28, 30, 31 via vaporizer 27 at a collective flow rate at 1.1 ml/min or below.
• oxidizing gas is introduced into chamber 13 via one or more of gas flow controllers 48, 49, 50, according to the desired chemistry, along with carrier gas via gas flow controller 46 if desired.
• Process 74a at this flow rate and under these conditions, continues for a time duration selected according to the thickness of PZT to be deposited at this low deposition rate. For example, it is contemplated that the duration of process 74a will typically be on the order of from about 100 seconds to about 300 seconds. An expected deposition rate for this process 74a, under these conditions, will be about 0.5 to 1.5 A/sec.
• deposition of PZT ferroelectric material 22 at a higher deposition rate is then performed in process 76a.
• the higher deposition rate is achieved by increasing the collective flow rate of the precursors and solvent relative to that of process 74a.
• high deposition rate process 76a is performed by introducing all precursors (lead, zirconium, and titanium) and the solvent from ampoules 26, 28, 30, 31 via vaporizer 27 at a collective flow rate above 1.1 ml/min, for example at a rate between about 1.5 ml/min to about 2.5 ml/min, in combination with the oxidizing gas and the carrier gas as described above.
• process 76a The introduction of these reactants and carrier gas into chamber 13, and the resulting PZT deposition, continues in process 76a for a time duration selected according to the desired overall thickness of PZT ferroelectric material 22, for example for a time between about 150 seconds to about 250 seconds.
• An expected deposition rate for this process 74a, under these conditions, will be about 1.5 to 3.0 A/sec.
• the duration of low deposition rate process 74a relative to that of high deposition rate process 76a determines the proportion of PZT ferroelectric material 22 deposited in low deposition rate process 74a to that deposited in high deposition rate process 76a.
• the relative thicknesses of these constituent sub-layers of PZT ferroelectric material 22 can vary widely, for example from about 10% to about 50% of the overall thickness formed by low deposition rate process 76a.
• FIGS. 6a and 6b illustrate examples of PZT ferroelectric material 22 as formed according to embodiments of this invention, but at different relative deposition times for processes 74a, 74b in this embodiment.
• PZT ferroelectric material 22 is shown as deposited over lower conductive plate layer 20a, and underlying upper conductive plate layer 22a.
• PZT ferroelectric material 22 in the example of FIG. 6a includes a relatively thin PZT layer 22LFR formed in low deposition rate process 74a in contact with lower conductive plate layer 20a, and a relatively thick PZT layer 22RFR formed in high deposition rate process 76a overlying PZT layer 22 L FR and underlying upper conductive plate layer 20b.
• the thickness t 22L FR of PZT layer 22 L FR is about one-tenth the overall thickness t 22 of PZT ferroelectric material 22, with PZT layer 22RFR at a thickness t 22 HFR that is about nine -tenths the overall thickness t 22 .
• the duration of low deposition rate process 74a is no greater than that of high deposition rate process 76a, for example as short as one-half the duration of high deposition rate process 76a.
• PZT layer 22 L FR formed in low deposition rate process 74a is about the same thickness as PZT layer 22RFR formed in high deposition rate process 76a, for example with thicknesses t 22 LFR and t 22 HFR each at about one-half the overall thickness t 22 .
• the time duration of low deposition rate process 74a will be longer than that of high deposition rate process 76a, for example twice as long, to construct layers 22LFR, 22RFR at the same thickness, given the different deposition rates.
• FIG. 5b illustrates an alternative embodiment, in which the composition of
• PZT ferroelectric material 22 also varies, along with the rate at which it was deposited.
• heating process 72 is performed as described above relative to FIG. 5a, elevating the temperature of the interior of chamber 13 to a temperature below about 640 degC, as measured at susceptor 24.
• low deposition rate process 74b again introduces the precursors (lead, zirconium, titanium) and the solvent at a low collective flow rate, and at a selected ratio of the precursors among themselves, along with oxidizing gas as described above; the deposition conditions in chamber 13 otherwise correspond to those described above for process 74a of FIG. 5a.
• lead- zirconium-titanate typically has a perovskite crystalline structure, in which lead is generally assigned to the "A" sites of the crystal unit cell, while zirconium and titanium are assigned to the "B” cell sites.
• the stoichiometry of PZT material can somewhat vary, and as such the A/B ratio of deposited PZT can vary in a way that is dependent on the relative flow rates of the "A" constituent (Pb) to the "B” constituents (Zr and Ti).
• low deposition rate process 74b introduces the precursors (lead, zirconium, titanium) and the solvent at a collective flow rate at or below 1.1 ml/min, as in process 74a of FIG.
• low deposition rate process 74b continues for a selected time duration to deposit a first portion of PZT ferroelectric material 22 to the desired thickness.
• High deposition rate process 76b is then performed, by increasing the collective flow rate of the precursors (lead, zirconium, titanium) and the solvent, in which the relative flow rates of lead, zirconium, and titanium are changed to a higher Pb/(Zr + Ti) (i.e., A/B) ratio.
• the collective flow rate of the precursors and solvent in process 76b can range from about 1.5 ml/min. to about 2.5 ml/min., and the Pb/(Zr + Ti) (i.e., A/B) ratio is about 1.10. Under these conditions, high deposition rate process 76b is performed for another selected time duration, in the presence of oxidizing gas, to complete the deposition of PZT ferroelectric material 22 to the desired overall thickness.
• PZT ferroelectric material 22 deposited in processes 74b, 76b will differ in composition, specifically in the lead content of the resulting portions of the overall film. As a result, it is contemplated that the performance of the resulting PZT ferroelectric material 22 can reflect positive attributes of the structure of each portion, namely the high switching polarization Psw of the upper lead-rich portion of the layer, and also the low leakage characteristics of the lower portion with lower lead content.
• the resulting PZT ferroelectric material 22 has been observed to be substantially free of the "haze" defects to which low temperature PZT films are vulnerable, and which adversely affect device yield. Indeed, it has been observed from experiments that the switching polarization of PZT ferroelectric material deposited according to this embodiment is higher than that of a single PZT layer deposited under the higher (e.g., 1.10) A/B ratio and higher deposition rate conditions of process 76b throughout, and at a device yield at least as high as that attained by a single PZT layer deposited with lower collective flow rate conditions of process 74b throughout. It is contemplated that the differences in lead composition between the low deposition rate and high deposition rate portions of PZT ferroelectric material 22, deposited according to this embodiment, can be observed using modern analytical equipment.
• Heating process 72 is performed as described above relative to FIGS. 5a and 5b, in which the temperature of chamber 13 containing wafer 23 is raised to a susceptor temperature below about 640 degC, under similar pressure and other conditions as described above relative to FIG. 5a.
• Low deposition rate process 74c is then performed, in which the precursors (lead, zirconium, titanium) and the solvent are introduced at a low collective flow rate, for example at or below about 1.1 ml/min.
• the oxygen concentration in the oxidizing gas introduced during low deposition rate process 74c is relatively low.
• the oxygen concentration of the oxidizing gas introduced in process 74c is about 33% 0 2 , with the rest of the oxidizing gas made up of a diluting inert gas, such as argon; in this example, this diluted oxidizing gas is introduced as the combination of 0 2 at a flow rate of about 1500 seem and Ar at a flow rate of about 3000 seem.
• low deposition rate process 74c is performed for a selected time duration to deposit a first portion of PZT ferroelectric material 22 at the desired thickness.
• high deposition rate process 76c is then performed by increasing the collective flow rate of the precursors (lead, zirconium, titanium) and the solvent to from about 1.5 ml/min. to about 2.5 ml/min, for example.
• the oxygen concentration in the oxidizing gas is increased relative to that in process 74c, for example to 100% oxygen with no inert gas dilution (e.g., 0 2 at 4500 seem, and Ar at 0 seem). This increase in oxygen concentration is contemplated to increase the oxidation reaction rate, and thus the rate at which the PZT material is deposited.
• Other conditions in chamber 13 may be maintained as in process 74c.
• High deposition rate process 76c is then performed for its selected time duration, completing the deposition of the desired overall thickness of PZT ferroelectric material 22.
• FIG. 5d illustrates PZT deposition process 70 according to another embodiment.
• heating process 72 is performed as described above relative to FIG. 5a, elevating the temperature of the interior of chamber 13 to a susceptor temperature below about 640 degC.
• Low deposition rate process 74a is then performed according to this embodiment, in which the precursors (lead, zirconium, titanium) and the solvent are introduced at a low collective flow rate, for example at or below 1.1 ml/min, along with oxidizing gas, and under the appropriate deposition conditions in chamber 13 as described above.
• This low deposition rate process 74a continues for a selected time duration to deposit a first portion of PZT ferroelectric material 22 to the desired thickness, as discussed above.
• process 77 is then performed to increase the temperature of chamber 13 and wafer 23.
• the temperature at susceptor 24 may be raised, in process 77, from about 635 degC to about 645 degC.
• high deposition rate process 76a is then performed to deposit the upper portion of PZT ferroelectric material 22 at an increased collective flow rate of the precursors (lead, zirconium, titanium) and the solvent, for example ranging from about 1.5 ml/min. to about 2.5 ml/min. as described above.
• High deposition rate process 76b is performed for another selected time duration, in the presence of oxidizing gas, to complete the deposition of PZT ferroelectric material 22 to the desired overall thickness.
• one or more of the deposition conditions may be changed in a continuous fashion during deposition, resulting in a "single" deposition process that begins under low deposition rate conditions and finishes under higher deposition rate conditions.
• upper conductive plate layer 20b is then deposited over PZT ferroelectric material 22 in process 78. It is contemplated that the composition of upper conductive plate layer 20b will typically be the same as that of lower conductive plate layer 20a, for symmetry and to allow the use of the same materials and processes for each. If lower and upper conductive plate layers 20a, 20b are composed of a stack of multiple conductive materials, the order of those materials in layers 20a, 20b will typically be reversed. It is contemplated that deposition process 78 will typically be performed by sputter deposition, although other techniques for depositing conductive materials may alternatively be used.
• ferroelectric capacitor 15 is then completed by photolithographic patterning of photoresist or another mask layer to define its size and location, followed by a single masked stack etch of conductive plates 20a, 20b, and ferroelectric material 22.
• Commonly assigned U.S. Patent No. 6,656,748, incorporated herein by reference describes an example of ferroelectric stack formation and etch process 80, suitable for use in connection with embodiments of this invention. Additional processing to complete ferroelectric capacitor 15, such as the formation of passivation films such as described in commonly assigned copending U.S. patent application S.N. 13/432,736, incorporated herein by this reference, may also be performed.
• the manufacture of the integrated circuit is then completed in process 82, by conventional processes for forming the various levels of interlevel dielectrics, conductors, and the like.
• the disclosed embodiments can enable one or more advantages in the manufacture of ferroelectric materials and integrated circuits incorporating those materials, as compared with conventional deposition processes and technologies.
• the disclosed embodiments enable the deposition of a ferroelectric material with high switching polarization in combination with low leakage characteristics.
• the overall deposition rate attainable by the disclosed embodiments is significantly higher than that of a low deposition rate single layer film; as a result, the manufacturing throughput of the ferroelectric deposition process can significantly increase, for example by on the order of 30 to 80%.
• ferroelectric material deposited according to disclosed embodiments has been observed to be substantially free of the "haze" defects that often occur at low deposition temperatures, such as below about 640 degC.
• the disclosed embodiments are capable of depositing a ferroelectric film that can be readily scaled to thicknesses on the order of ⁇ and thinner, as compatible with modern integrated circuits with feature sizes in the deep sub-micron region, It is contemplated that these and other important benefits may be enabled by the disclosed embodiments.

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