US20040152214A1 - Method of making a haze free, lead rich PZT film - Google Patents

Method of making a haze free, lead rich PZT film Download PDF

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US20040152214A1
US20040152214A1 US10/356,092 US35609203A US2004152214A1 US 20040152214 A1 US20040152214 A1 US 20040152214A1 US 35609203 A US35609203 A US 35609203A US 2004152214 A1 US2004152214 A1 US 2004152214A1
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pzt film
pzt
lead rich
stoichiometric
film
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US10/356,092
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Sanjeev Aggarwal
Kelly Taylor
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Texas Instruments Inc
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Texas Instruments Inc
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Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AGGARWAL, SANJEEV, TAYLOR, KELLY J.
Priority to JP2004020653A priority patent/JP2004235645A/en
Priority to EP04002053A priority patent/EP1443545A3/en
Publication of US20040152214A1 publication Critical patent/US20040152214A1/en
Priority to US11/046,568 priority patent/US7361949B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/409—Oxides of the type ABO3 with A representing alkali, alkaline earth metal or lead and B representing a refractory metal, nickel, scandium or a lanthanide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material

Definitions

  • PbO is deposited on the walls of the deposition chamber. Thereafter, the PbO deposits will dislodge from the deposition chamber walls and settle onto any semiconductor wafer contained in the chamber. This deposition of PbO on the wafer causes the PZT layer to have haze (roughness). The haze is undesirable and degrades the properties of the ferroelectric capacitor.
  • This invention concerns the fabrication of a lead rich PZT semiconductor wafer layer that is haze free.
  • FIG. 1 is a cross-section view of a semiconductor wafer having a PZT film.
  • FIG. 2 is a flow diagram illustrating the process flow of the present invention.
  • FIG. 3 is a cross-section view of a partially fabricated ferroelectric memory device that is fabricated in accordance with the present invention.
  • FIG. 1 depicts a cross-section of a portion of a semiconductor wafer, 2 , having a haze free, phase pure, PZT layer, 3 , in accordance with the invention. More specifically, FIG. 1 shows a partially fabricated FeRAM (ferroelectric memory) array and periphery (which includes most of the rest of the logic chip). In the best mode application the FeRAM module is located between the standard logic front end and back end. The transistor logic is contained in the front-end portion of the wafer (closest to the substrate). The memory module contains non-volatile memory. The device's interconnects and metal lines—used to move electrical signals and power throughout the device—are contained in the back end portion of the wafer.
  • FeRAM ferroelectric memory
  • the single capacitor memory cell (referred to as a “1T/1C” or “1C” memory cell) has one transistor and one storage capacitor.
  • the bottom electrode of the storage capacitor is connected to the drain of the transistor.
  • the FeRAM memory module is located between the front-end module and the back end module.
  • the FeRAM module may be placed over the first level of metallization, 6 , or near the end of the back end module, 7.
  • the FeRAM memory module contains numerous FeRAM memory cells.
  • the ferroelectric capacitor contained within the ferroelectric memory cell is comprised of ferroelectric material, such as lead zirconate titanate (called “PZT” based on its chemical formula: Pb(Zr, Ti)O 3 ) that functions as a capacitor dielectric, 3 , situated between a bottom electrode, 4 , and a top electrode, 5.
  • PZT lead zirconate titanate
  • the bottom electrode, 4 is comprised of iridium, iridium oxide, or a stack thereof.
  • the top electrode, 5 is comprised of iridium, iridium oxide, or a stack thereof.
  • a barrier layer, 8 formed (step 204 ) over the contacts, 9 (which are connected to the substrate and gates contained in the front-end module).
  • the conductive barrier, 8 may be formed by a reactive sputter deposition of TiAlN; however, other deposition techniques or barrier materials may be used. For example, instead of using TIAlN as the barrier material, TiAlON, TiN, or a stack having any combination of these three materials may be used.
  • the bottom electrode, 4 is formed (step 206 ) on the barrier layer, 8 .
  • the bottom electrode, 4 is formed by sputter deposition of Ir (using Ar as the inert gas, but other inert gases may be used).
  • the bottom electrode, 4 may be formed by reactive sputter deposition of IrO, (using (Ar+O 2 ) as the gas mixture, but inert gases other than Ar may be used in the mixture).
  • other deposition techniques may be used to form the bottom electrode, 4 , such as chemical vapor deposition.
  • other materials may be used for the bottom electrode, such as Pt, Pd, PdOx, Au, Ru, RuOx, Rh, or RhOx.
  • the next step during the manufacturing process is the deposition of the capacitor dielectric PZT layer, 3 , over the bottom electrode, 4 .
  • the PZT layer, 3 formed during this deposition process has two PZT films, namely a stoichiometric film, 101 , and a lead rich film, 102 .
  • a stoichiometric PZT film, 101 is now formed (step 208 ) over the bottom electrode, 4.
  • stoichiometric film 101 is formed by a deposition technique called metal organic chemical vapor deposition (“MOCVD”).
  • the MOCVD deposition process involves delivering PbO+ZrO 2 +TiO 2 into the deposition chamber containing the semiconductor wafer, 2 , to create a Pb(ZrTi)O 3 film.
  • the MOCVD may be performed using a machine such as the Centura manufactured by AMAT (Applied Materials).
  • AMAT Applied Materials
  • another technique such as chemical solution deposition (sol-gel or metal organic decomposition) can also be used.
  • the Zr to Ti ratio is 20/80; alternatively, pure PbTiO 3 may be used (to maximize switched polarization), or PbZrO 3 may be used—depending on the electronic device.
  • the MOCVD deposition process for the PZT film, 101 is done at a wafer temperature of approximately 600° C., a deposition pressure of 8 Torr, with a precursor flow of 200 mg/min, and a deposition rate of 140 ⁇ /min.
  • the wafer temperature may be anything below 700° C.
  • the pressure may be anything greater than 2 Torr
  • the precursor flow can be anything greater than 100 mg/min
  • the deposition rate can be anything greater than 80 ⁇ /min.
  • an Ar or He carrier gas is used to deliver the precursors to the reactor chamber through the showerhead where they are mixed with an oxidizer such as O 2 .
  • an oxidizer such as O 2 .
  • N 2 O or O 3 may be used as the oxidizer.
  • the PZT film, 101 created by this process is stoichiometric (i.e. haze free and phase pure).
  • the Pb content of the film may be from Pb 0.98 (Zr,Ti)O 3 to Pb 1.0 (Zr,Ti)O 3 .
  • Film 101 is generally 50-100 ⁇ thick. However, it is within the scope of the invention to have a stoichiometric film, 101 , with a thickness anywhere between 50-1400 ⁇ .
  • the PZT film, 101 may be doped with up to 5% donor dopant. The donor dopant improves the reliability of the PZT by helping to control the point defect concentrations.
  • a lead rich film of PZT, 102 is now formed (step 210 ) over the haze free, phase pure PZT film, 101 .
  • the lead rich film, 102 is also formed by MOCVD.
  • another technique such as chemical solution deposition (sol-gel or metal organic decomposition) can also be used.
  • the MOCVD deposition process of lead rich film, 102 involves delivering PbO+ZrO 2 +TiO 2 into the deposition chamber containing the semiconductor wafer, 2.
  • the Zr to Ti ratio is 20/80; alternatively, pure PbTiO 3 may be used (to maximize switched polarization), or PbZrO 3 may be used—depending on the electronic device.
  • the content of Pb is Pb 1.02 (Zr,Ti)O 3 ; however the amount of Pb can range from 1 to 1.02.
  • the lead rich PZT film, 102 may be doped with up to 5% donor dopant. The donor dopant improves the reliability of the PZT by helping to control the point defect concentrations.
  • the MOCVD deposition process for the PZT film, 102 is done at a wafer temperature of approximately 600° C., a deposition pressure of 8 Torr, with a precursor flow of 200 mg/min, and a deposition rate of 140 ⁇ /min.
  • wafer temperatures may be anything below 700° C.
  • the pressure may be anything greater than 2 Torr
  • the precursor flow can be anything greater than 100 mg/min
  • the deposition rate can be anything greater than 80 ⁇ /min.
  • an Ar or He carrier gas is used to deliver the precursors to the reactor chamber through the showerhead where they are mixed with an oxidizer such as O 2 .
  • an oxidizer such as O 2 .
  • N 2 O or O 3 may be used as the oxidizer.
  • the PZT layer, 102 created by this process is lead rich. However it is also haze free and phase pure because it was deposited on top of the perovskite film, 101 .
  • Film 102 is generally 600-650 ⁇ thick. (As an example, if the PZT layer, 3 , is 700 ⁇ and the stoichiometric film, 101 , is 50 ⁇ ; then the lead rich film, 102 , is 650 ⁇ .) However, it is within the scope of the invention to have a lead rich PZT film, 102 , with a thickness anywhere between 0-1400 ⁇ .
  • the stoichiometric PZT film, 101 , and the lead rich PZT film, 102 comprise the lead rich ferroelectric capacitor dielectric layer, 3. It is within the scope of the invention to use any combination of the above inventive techniques to create the high lead content capacitor dielectric layer, 3 .
  • the lead rich dielectric layer, 3 may be created using only the two film structure, using the two film structure manufactured using an increased deposition pressure (i.e. changing from 2 Torr to 4 Torr), or using the two film structure manufactured with an increased precursor flow (i.e. changing form 100 mg/min to 200 mg/min).
  • the high lead content PZT dielectric layer, 3 will cause the ferroelectric capacitor to have desirable endurance, durability, and reliability.
  • the haze free, phase pure PZT film, 3 formed in accordance with the present invention will operate at a lower operating voltage and therefore reduce the power consumption of electronic devices.
  • the top electrode, 5 is formed (step 212 ) on the capacitor dielectric layer, 3.
  • the top electrode, 5 is formed by sputter deposition of Ir (using Ar as the inert gas, but other inert gases may be used).
  • the top electrode, 5 may be formed by reactive sputter deposition of IrO x (using (Ar+O 2 ) as the gas mixture, but inert gases other than Ar may be used in the mixture).
  • other deposition techniques may be used to form the top electrode, 5 , such as chemical vapor deposition.
  • other materials may be used for the top electrode, such as Pt, Pd, PdOx, Au, Ru, RuOx, Rh, or RhOx.
  • the entire capacitor stack (comprised of barrier, 8 , bottom electrode, 4 , capacitor dielectric, 3 , and tope electrode, 5 ) is patterned, etched, and cleaned to form (step 214 ) the final ferroelectric capacitor structure.
  • the formation (step 216 ) of the final electronic device structure continues, including the completion of the FeRAM module and the back-end module.
  • the instant invention can be used to fabricate standalone FeRAM devices or FeRAM devices integrated into a semiconductor chip that has many other device functions than those described herein.
  • the bottom electrode, 4 instead of forming the bottom electrode, 4 , on the barrier layer, 8 ; the bottom electrode, 4 , may be formed directly on the front-end module.
  • this invention description focuses on the formation of planar capacitors, a three-dimensional capacitor using a post or cup structure can be fabricated with the same inventive process.
  • the invention is applicable to semiconductor wafers having different well and substrate technologies, transistor configurations, and metal connector materials or configurations.
  • the invention is applicable to other semiconductor technologies such as BiCMOS, bipolar, SOI, strained silicon, pyroelectric sensors, opto-electronic devices, microelectrical mechanical system (“MEMS”), or SiGe.

Abstract

An embodiment of the invention is a method of fabricating a haze free, phase pure, PZT layer, 3, where a lead rich PZT film, 102, is formed over a phase pure stoichiometric PZT film, 101.

Description

    CROSS-REFERENCE To RELATED APPLICATIONS
  • This application is related to application Ser. No. ______ (Attorney Docket Number TI-34784) filed on the same date as this application and entitled “Method of Making a Haze Free PZT Film”. With its mention in this section, this patent application is not admitted to be prior art with respect to the present invention.[0001]
    • BACKGROUND OF THE INVENTION
  • During the deposition of the PZT capacitor dielectric layer of a ferroelectric capacitor, PbO is deposited on the walls of the deposition chamber. Thereafter, the PbO deposits will dislodge from the deposition chamber walls and settle onto any semiconductor wafer contained in the chamber. This deposition of PbO on the wafer causes the PZT layer to have haze (roughness). The haze is undesirable and degrades the properties of the ferroelectric capacitor. This invention concerns the fabrication of a lead rich PZT semiconductor wafer layer that is haze free.[0002]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-section view of a semiconductor wafer having a PZT film. [0003]
  • FIG. 2 is a flow diagram illustrating the process flow of the present invention. [0004]
  • FIG. 3 is a cross-section view of a partially fabricated ferroelectric memory device that is fabricated in accordance with the present invention. [0005]
    • DETAILED DESCRIPTION OF THE INVENTION
  • The present invention is described with reference to the attached figures, wherein similar reference numerals are used throughout the figures to designate like or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the instant invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. [0006]
  • Referring to the drawings, FIG. 1 depicts a cross-section of a portion of a semiconductor wafer, [0007] 2, having a haze free, phase pure, PZT layer, 3, in accordance with the invention. More specifically, FIG. 1 shows a partially fabricated FeRAM (ferroelectric memory) array and periphery (which includes most of the rest of the logic chip). In the best mode application the FeRAM module is located between the standard logic front end and back end. The transistor logic is contained in the front-end portion of the wafer (closest to the substrate). The memory module contains non-volatile memory. The device's interconnects and metal lines—used to move electrical signals and power throughout the device—are contained in the back end portion of the wafer. Other than the best mode process of forming the PZT film located in the FeRAM module (described herein), the processing steps for creating the ferroelectric memory device is described in commonly assigned patent/patent application having the application Ser. No. 09/702,985 (TI Docket number TI-29970, filed Oct. 31, 2000), incorporated herein by reference, and not admitted to be prior art with respect to the present invention by its mention in this section.
  • The single capacitor memory cell (referred to as a “1T/1C” or “1C” memory cell) has one transistor and one storage capacitor. The bottom electrode of the storage capacitor is connected to the drain of the transistor. In this example application, shown in FIG. 1, the FeRAM memory module is located between the front-end module and the back end module. However, other locations for the FeRAM memory module are within the scope of this invention. For example, the FeRAM module may be placed over the first level of metallization, [0008] 6, or near the end of the back end module, 7. Furthermore, it is within the scope of this invention to have a FeRAM module containing a dual capacitor memory cell (comprising two transistors and two ferroelectric capacitors) instead of a single capacitor memory cell.
  • The FeRAM memory module contains numerous FeRAM memory cells. The ferroelectric capacitor contained within the ferroelectric memory cell is comprised of ferroelectric material, such as lead zirconate titanate (called “PZT” based on its chemical formula: Pb(Zr, Ti)O[0009] 3) that functions as a capacitor dielectric, 3, situated between a bottom electrode, 4, and a top electrode, 5. In the best mode application, the bottom electrode, 4, is comprised of iridium, iridium oxide, or a stack thereof. Similarly, the top electrode, 5, is comprised of iridium, iridium oxide, or a stack thereof.
  • Referring now to FIGS. 2 and 3, after the formulation of the front-end module (step [0010] 202), there is a barrier layer, 8, formed (step 204) over the contacts, 9 (which are connected to the substrate and gates contained in the front-end module). The conductive barrier, 8, may be formed by a reactive sputter deposition of TiAlN; however, other deposition techniques or barrier materials may be used. For example, instead of using TIAlN as the barrier material, TiAlON, TiN, or a stack having any combination of these three materials may be used.
  • Next, the bottom electrode, [0011] 4, is formed (step 206) on the barrier layer, 8. The bottom electrode, 4, is formed by sputter deposition of Ir (using Ar as the inert gas, but other inert gases may be used). Conversely, the bottom electrode, 4, may be formed by reactive sputter deposition of IrO, (using (Ar+O2) as the gas mixture, but inert gases other than Ar may be used in the mixture). However, other deposition techniques may be used to form the bottom electrode, 4, such as chemical vapor deposition. Moreover, other materials may be used for the bottom electrode, such as Pt, Pd, PdOx, Au, Ru, RuOx, Rh, or RhOx.
  • The next step during the manufacturing process is the deposition of the capacitor dielectric PZT layer, [0012] 3, over the bottom electrode, 4. In the best mode application, the PZT layer, 3, formed during this deposition process has two PZT films, namely a stoichiometric film, 101, and a lead rich film, 102. In accordance with the invention, a stoichiometric PZT film, 101, is now formed (step 208) over the bottom electrode, 4. In the best mode application, stoichiometric film 101 is formed by a deposition technique called metal organic chemical vapor deposition (“MOCVD”). The MOCVD deposition process involves delivering PbO+ZrO2+TiO2 into the deposition chamber containing the semiconductor wafer, 2, to create a Pb(ZrTi)O3 film. As an example, the MOCVD may be performed using a machine such as the Centura manufactured by AMAT (Applied Materials). However, another technique such as chemical solution deposition (sol-gel or metal organic decomposition) can also be used. Moreover, in the example application the Zr to Ti ratio is 20/80; alternatively, pure PbTiO3 may be used (to maximize switched polarization), or PbZrO3 may be used—depending on the electronic device.
  • In the best mode application the MOCVD deposition process for the PZT film, [0013] 101, is done at a wafer temperature of approximately 600° C., a deposition pressure of 8 Torr, with a precursor flow of 200 mg/min, and a deposition rate of 140 Å/min. However variations of these parameters are within the scope of this invention. For example, the wafer temperature may be anything below 700° C., the pressure may be anything greater than 2 Torr, the precursor flow can be anything greater than 100 mg/min, and the deposition rate can be anything greater than 80 Å/min. In this best mode application, an Ar or He carrier gas is used to deliver the precursors to the reactor chamber through the showerhead where they are mixed with an oxidizer such as O2. However, N2O or O3 may be used as the oxidizer.
  • In accordance with the invention, the PZT film, [0014] 101, created by this process is stoichiometric (i.e. haze free and phase pure). The Pb content of the film may be from Pb0.98(Zr,Ti)O3 to Pb1.0(Zr,Ti)O3. Film 101 is generally 50-100 Å thick. However, it is within the scope of the invention to have a stoichiometric film, 101, with a thickness anywhere between 50-1400 Å. Additionally, the PZT film, 101, may be doped with up to 5% donor dopant. The donor dopant improves the reliability of the PZT by helping to control the point defect concentrations.
  • Further in accordance with the invention, a lead rich film of PZT, [0015] 102, is now formed (step 210) over the haze free, phase pure PZT film, 101. In the best mode application, the lead rich film, 102, is also formed by MOCVD. However, another technique such as chemical solution deposition (sol-gel or metal organic decomposition) can also be used.
  • The MOCVD deposition process of lead rich film, [0016] 102, involves delivering PbO+ZrO2+TiO2 into the deposition chamber containing the semiconductor wafer, 2. In the example application, the Zr to Ti ratio is 20/80; alternatively, pure PbTiO3 may be used (to maximize switched polarization), or PbZrO3 may be used—depending on the electronic device. The content of Pb is Pb1.02(Zr,Ti)O3; however the amount of Pb can range from 1 to 1.02. Additionally, the lead rich PZT film, 102, may be doped with up to 5% donor dopant. The donor dopant improves the reliability of the PZT by helping to control the point defect concentrations.
  • In the best mode application the MOCVD deposition process for the PZT film, [0017] 102, is done at a wafer temperature of approximately 600° C., a deposition pressure of 8 Torr, with a precursor flow of 200 mg/min, and a deposition rate of 140 Å/min. However variations of these parameters are within the scope of this invention. For example, wafer temperatures may be anything below 700° C., the pressure may be anything greater than 2 Torr, the precursor flow can be anything greater than 100 mg/min, and the deposition rate can be anything greater than 80 Å/min. In this best mode application, an Ar or He carrier gas is used to deliver the precursors to the reactor chamber through the showerhead where they are mixed with an oxidizer such as O2. However, N2O or O3 may be used as the oxidizer.
  • The PZT layer, [0018] 102, created by this process is lead rich. However it is also haze free and phase pure because it was deposited on top of the perovskite film, 101. Film 102 is generally 600-650 Å thick. (As an example, if the PZT layer, 3, is 700 Å and the stoichiometric film, 101, is 50 Å; then the lead rich film, 102, is 650 Å.) However, it is within the scope of the invention to have a lead rich PZT film, 102, with a thickness anywhere between 0-1400 Å.
  • Together, the stoichiometric PZT film, [0019] 101, and the lead rich PZT film, 102, comprise the lead rich ferroelectric capacitor dielectric layer, 3. It is within the scope of the invention to use any combination of the above inventive techniques to create the high lead content capacitor dielectric layer, 3. For example, the lead rich dielectric layer, 3, may be created using only the two film structure, using the two film structure manufactured using an increased deposition pressure (i.e. changing from 2 Torr to 4 Torr), or using the two film structure manufactured with an increased precursor flow (i.e. changing form 100 mg/min to 200 mg/min). The high lead content PZT dielectric layer, 3, will cause the ferroelectric capacitor to have desirable endurance, durability, and reliability. Furthermore the haze free, phase pure PZT film, 3, formed in accordance with the present invention will operate at a lower operating voltage and therefore reduce the power consumption of electronic devices.
  • Next, the top electrode, [0020] 5, is formed (step 212) on the capacitor dielectric layer, 3. In the example application, the top electrode, 5, is formed by sputter deposition of Ir (using Ar as the inert gas, but other inert gases may be used). Conversely, the top electrode, 5, may be formed by reactive sputter deposition of IrOx (using (Ar+O2) as the gas mixture, but inert gases other than Ar may be used in the mixture). However, other deposition techniques may be used to form the top electrode, 5, such as chemical vapor deposition. Furthermore, other materials may be used for the top electrode, such as Pt, Pd, PdOx, Au, Ru, RuOx, Rh, or RhOx.
  • Next, the entire capacitor stack (comprised of barrier, [0021] 8, bottom electrode, 4, capacitor dielectric, 3, and tope electrode, 5) is patterned, etched, and cleaned to form (step 214) the final ferroelectric capacitor structure. Lastly, the formation (step 216) of the final electronic device structure continues, including the completion of the FeRAM module and the back-end module.
  • Various modifications to the invention as described above are within the scope of the claimed invention. As an example, the instant invention can be used to fabricate standalone FeRAM devices or FeRAM devices integrated into a semiconductor chip that has many other device functions than those described herein. In addition, instead of forming the bottom electrode, [0022] 4, on the barrier layer, 8; the bottom electrode, 4, may be formed directly on the front-end module. Although this invention description focuses on the formation of planar capacitors, a three-dimensional capacitor using a post or cup structure can be fabricated with the same inventive process. Furthermore, the invention is applicable to semiconductor wafers having different well and substrate technologies, transistor configurations, and metal connector materials or configurations. Moreover, the invention is applicable to other semiconductor technologies such as BiCMOS, bipolar, SOI, strained silicon, pyroelectric sensors, opto-electronic devices, microelectrical mechanical system (“MEMS”), or SiGe.
  • While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents. [0023]

Claims (50)

What is claimed is:
1. A method of fabricating a layer of PZT on a semiconductor wafer comprising:
forming a front-end structure over a semiconductor substrate;
forming a bottom electrode over said front-end structure;
forming a phase pure stoichiometric PZT film over said bottom electrode; and
forming a lead rich PZT film over said phase pure stoichiometric PZT film.
2. The method of claim 1 wherein a thickness of said phase pure stoichiometric PZT film is less than a thickness of said lead rich PZT film.
3. The method of claim 1 wherein said phase pure stoichiometric PZT film has a thickness less than a total thickness of said layer of PZT.
4. The method of claim 1 wherein said lead rich PZT film has a thickness less than a total thickness of said layer of PZT.
5. The method of claim 1 wherein said phase pure stoichiometric PZT film is deposited by MOCVD.
6. The method of claim 1, wherein said lead rich PZT film is deposited by MOCVD.
7. The method of claim 1 wherein said lead rich PZT film has a Pb concentration greater than the Pb concentration of said phase pure stoichiometric PZT film.
8. The method of claim 1 wherein the phase pure stoichiometric PZT film is formed with a deposition pressure of 2 Torr or more.
9. The method of claim 1 wherein the lead rich PZT film is formed under a deposition pressure of 2 Torr or more.
10. The method of claim 1 wherein the phase pure stoichiometric PZT film is formed with a deposition rate of at least 80 Å/min.
11. The method of claim 1 wherein the lead rich PZT film is formed with a deposition rate of at least 80 Å/min.
12. The method of claim 1 wherein the phase pure stoichiometric PZT film is formed using a precursor flow of 100 mg/min or more.
13. The method of claim 1 wherein the lead rich PZT film is formed using a precursor flow of 100 mg/min or more.
14. The method of claim 1 wherein a ferroelectric capacitor is fabricated by further forming a top electrode over said PZT layer.
15. The method of claim 1 wherein said bottom electrode is comprised of a material selected from the group consisting of: Ir, IrOx, or a stack thereof.
16. The method of claim 14 wherein said top electrode is comprised of a material selected from the group consisting of: Ir, IrOx, or a stack thereof.
17. The method of claim 1 wherein said stoichiometric PZT film can be PbZrO3.
18. The method of claim 1 wherein said stoichiometric PZT film can be PbTiO3.
19. The method of claim 1 wherein said stoichiometric PZT film is a solid solution of the component end members PbZrO3 and PbTiO3.
20. The method of claim 1 wherein said stoichiometric PZT film is doped up to 5% with either La or Nb.
21. The method of claim 1 wherein said lead rich PZT film can be PbZrO3.
22. The method of claim 1 wherein said lead rich PZT film can be PbTiO3.
23. The method of claim 1 wherein said lead rich PZT film is a solid solution of the component end members PbZrO3 and PbTiO3.
24. The method of claim 1 wherein said lead rich PZT film is doped up to 5% with either La or Nb.
25. A method of fabricating an electronic device that includes a layer of PZT situated over a semiconductor substrate comprising:
forming a front-end structure over a semiconductor substrate;
forming a bottom electrode over said front-end structure;
forming a phase pure stoichiometric PZT film over said bottom electrode; and
forming a lead rich PZT film over said phase pure stoichiometric PZT film.
26. The method of claim 25 wherein a thickness of said phase purestoichiometric PZT film is less than a thickness of said lead rich PZT film.
27. The method of claim 25 wherein said phase pure stoichiometric PZT film has a thickness less than a total thickness of said layer of PZT.
28. The method of claim 25 wherein said lead rich PZT film has a thickness less than a total thickness of said layer of PZT.
29. The method of claim 25 wherein said phase pure stoichiometric PZT film is deposited by MOCVD.
30. The method of claim 25, wherein said lead rich PZT film is deposited by MOCVD.
31. The method of claim 25 wherein said lead rich PZT film has a Pb concentration greater than the Pb concentration of said phase pure stoichiometric PZT film.
32. The method of claim 25 wherein the phase pure stoichiometric PZT film is formed with a deposition pressure of 2 Torr or more.
33. The method of claim 25 wherein the lead rich PZT film is formed under a deposition pressure of 2 Torr or more.
34. The method of claim 25 wherein the phase pure stoichiometric PZT film is formed with a deposition rate of at least 80 Å/min.
35. The method of claim 25 wherein the lead rich PZT film is formed with a deposition rate of at least 80 Å/min.
36. The method of claim 25 wherein the phase pure stoichiometric PZT film is formed using a precursor flow of 100 mg/min or more.
37. The method of claim 25 wherein the lead rich PZT film is formed using a precursor flow of 100 mg/min or more.
38. The method of claim 25 wherein a ferroelectric capacitor is fabricated by further forming a top electrode over said PZT layer.
39. The method of claim 25 wherein said bottom electrode is comprised of a material selected from the group consisting of: Ir, IrOx, or a stack thereof.
40. The method of claim 38 wherein said top electrode is comprised of a material selected from the group consisting of: Ir, IrOx, or a stack thereof.
41. The method of claim 25 wherein said stoichiometric PZT film can be PbZrO3.
42. The method of claim 25 wherein said stoichiometric PZT film can be PbTiO3.
43. The method of claim 25 wherein said stoichiometric PZT film is a solid solution of the component end members PbZrO3 and PbTiO3.
44. The method of claim 25 wherein said stoichiometric PZT film is doped up to 5% with either La or Nb.
45. The method of claim 25 wherein said lead rich PZT film can be PbZrO3.
46. The method of claim 25 wherein said lead rich PZT film can be PbTiO3.
47. The method of claim 25 wherein said lead rich PZT film is a solid solution of the component end members PbZrO3 and PbTiO3.
48. The method of claim 25 wherein said lead rich PZT film is doped up to 5% with either La or Nb.
49. A haze free PZT layer prepared in accordance with claim 1.
50. A haze free PZT layer prepared in accordance with claim 25.
US10/356,092 2003-01-30 2003-01-30 Method of making a haze free, lead rich PZT film Abandoned US20040152214A1 (en)

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US7361949B2 (en) 2008-04-22

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