WO2014112166A1 - Dispositif électronique, procédé de fabrication correspondant, structure de substrat et procédé de fabrication correspondant - Google Patents

Dispositif électronique, procédé de fabrication correspondant, structure de substrat et procédé de fabrication correspondant Download PDF

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Publication number
WO2014112166A1
WO2014112166A1 PCT/JP2013/078044 JP2013078044W WO2014112166A1 WO 2014112166 A1 WO2014112166 A1 WO 2014112166A1 JP 2013078044 W JP2013078044 W JP 2013078044W WO 2014112166 A1 WO2014112166 A1 WO 2014112166A1
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substrate
thermal conductivity
electronic device
high thermal
hole
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PCT/JP2013/078044
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English (en)
Japanese (ja)
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元伸 佐藤
二瓶　瑞久
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独立行政法人産業技術総合研究所
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Publication of WO2014112166A1 publication Critical patent/WO2014112166A1/fr
Priority to US14/802,248 priority Critical patent/US9991187B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
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    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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Definitions

  • the present invention relates to an electronic device and a manufacturing method thereof, and a substrate structure and a manufacturing method thereof.
  • Patent Documents 1 and 2 Recently, in an electronic device, for example, a semiconductor device, as a heat dissipation technique, there has been an improvement in the connection between a semiconductor substrate and a heat sink (see Patent Documents 1 and 2). In addition, a configuration has been devised in which a material having high thermal conductivity is directly connected to a heating element of a semiconductor device to perform heat dissipation (see Patent Document 3).
  • the present invention has been made in view of the above problems, and provides a highly reliable electronic device that realizes extremely efficient heat dissipation with a relatively simple configuration, a manufacturing method thereof, a substrate structure, and a manufacturing method thereof.
  • the purpose is to do.
  • the electronic device of the present invention includes a substrate having a heat dissipation mechanism formed on the back surface and an element layer including functional elements formed on the surface of the substrate, and the heat dissipation mechanism is formed on the back surface of the substrate.
  • a first high thermal conductive material having a higher thermal conductivity than the substrate, formed in a plurality of first holes, and thermally connected to the first high thermal conductive material so as to cover the back side of the substrate.
  • the substrate structure of the present invention includes a substrate and a heat dissipation mechanism formed on the back surface of the substrate, and the heat dissipation mechanism is embedded from the bottom surfaces of a plurality of holes formed on the back surface of the substrate to a midway depth of the holes.
  • a high thermal conductivity material having a higher thermal conductivity than the substrate, and a sealing material that embeds the remaining portion in the hole from the surface of the substrate and seals the high thermal conductivity material in the substrate. Have.
  • the method for manufacturing an electronic device includes a step of forming a plurality of first holes on the back surface of a substrate, and a first highly thermally conductive material having a higher thermal conductivity than the substrate is formed in the first holes.
  • the substrate structure manufacturing method of the present invention includes a step of forming a plurality of holes on the back surface of the substrate, and a high thermal conductivity material having a higher thermal conductivity than the substrate so as to be embedded from the bottom surface of the hole to a midpoint of the hole. And a step of filling the hole from the surface of the substrate with a sealing material and sealing the high thermal conductivity material in the substrate.
  • FIG. 1 is a schematic cross-sectional view showing a method of manufacturing a substrate structure according to the first embodiment in the order of steps.
  • FIG. 2 is a schematic cross-sectional view showing the method for manufacturing the substrate structure according to the first embodiment in the order of steps, following FIG. 1.
  • FIG. 3 is a schematic cross-sectional view illustrating the method for manufacturing the substrate structure according to the first embodiment in the order of steps, following FIG. 2.
  • FIG. 4 is a schematic cross-sectional view illustrating the method for manufacturing the substrate structure according to the first embodiment in the order of steps, following FIG. 3.
  • FIG. 5 is a schematic cross-sectional view of the substrate structure manufacturing method according to the first embodiment in the order of steps, following FIG. FIG.
  • FIG. 6 is a schematic plan view showing the state of the back surface of the silicon substrate of FIG.
  • FIG. 7 is a schematic cross-sectional view showing the semiconductor device manufacturing method according to the second embodiment in the order of steps.
  • FIG. 8 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps, following FIG.
  • FIG. 9 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps, following FIG.
  • FIG. 10 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment in the order of steps, following FIG. 9.
  • FIG. 11 is a schematic cross-sectional view showing a step performed in place of the step of FIG. FIG.
  • FIG. 12 is a schematic cross-sectional view showing a process performed in place of the process of FIG.
  • FIG. 13 is a schematic cross-sectional view showing a process performed in place of the processes shown in FIGS.
  • FIG. 14 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps, following FIG.
  • FIG. 15 is a schematic cross-sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment in the order of steps, following FIG.
  • FIG. 16 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps, following FIG.
  • FIG. 17A is a schematic cross-sectional view showing the process of FIG. 7 in detail.
  • FIG. 17B is a schematic cross-sectional view showing the process of FIG. 7 in detail following FIG. 17A.
  • FIG. 17C is a schematic cross-sectional view illustrating the process of FIG. 7 in detail following FIG. 17B.
  • 18A is a schematic cross-sectional view illustrating the process of FIG. 7 in detail following FIG. 17C.
  • 18B is a schematic cross-sectional view showing the process of FIG. 7 in detail following FIG. 18A.
  • FIG. 19 is a cross-sectional view showing a schematic configuration of a laminated semiconductor device according to a modification of the second embodiment.
  • FIG. 20 is a cross-sectional view illustrating a schematic configuration of a laminated semiconductor device according to another example of the modification of the second embodiment.
  • FIG. 20 is a cross-sectional view illustrating a schematic configuration of a laminated semiconductor device according to another example of the modification of the second embodiment.
  • FIG. 21 is a schematic cross-sectional view showing the main steps of the semiconductor device manufacturing method according to the third embodiment.
  • FIG. 22 is a schematic cross-sectional view showing the main steps of the method of manufacturing the semiconductor device according to the third embodiment, following FIG.
  • FIG. 23 is a schematic cross-sectional view showing the main steps of the method of manufacturing the semiconductor device according to the third embodiment, following FIG.
  • FIG. 24 is a cross-sectional view illustrating a schematic configuration of a stacked semiconductor device according to a modification of the third embodiment.
  • FIG. 25 is a cross-sectional view showing a schematic configuration of a laminated semiconductor device according to another example of the modification of the third embodiment.
  • a plurality of holes 1 a are formed on the back surface of the silicon substrate 1.
  • a silicon substrate 10 is prepared as the substrate.
  • the silicon substrate 1 has a thickness of about 775 ⁇ m.
  • the back surface of the silicon substrate 1 is processed to a predetermined depth by lithography and dry etching. Thereby, a plurality of non-penetrating 1a are formed on the back surface of the silicon substrate 1.
  • the diameter of the hole 1a is, for example, about 20 ⁇ m to 100 ⁇ m, here about 50 ⁇ m, and the depth is equal to or less than the thickness of the substrate, for example, about 700 ⁇ m.
  • the base material 2 and the catalyst material 3 are sequentially formed on the bottom surface of the hole 1 a of the silicon substrate 1. Specifically, first, for example, Ta, TaN or the like is deposited to a thickness of about 15 nm by ALD, sputtering, or the like. As a result, the base material 2 which is a barrier metal is formed on the bottom and side surfaces of the hole 1a of the silicon substrate 1. Next, the catalyst material is deposited to a thickness of several nm, for example, about 1 nm by a vacuum evaporation method or the like.
  • the catalyst material a mixed material of one or more selected from Co, Ni, Fe and the like and one or more selected from Ti, TiN, TiO 2 , V, Al and the like is used. .
  • Co / Ti or Co / V is selected.
  • the catalyst material 3 is formed on the base material 2 on the bottom surface of the hole 1 a of the silicon substrate 1.
  • oblique milling is performed on the back surface of the silicon substrate 1 to remove the base material and the catalyst material deposited on the back surface of the silicon substrate 1.
  • oblique film formation may be performed on the back surface of the silicon substrate 1 to inactivate the catalyst material deposited on the back surface of the silicon substrate 1.
  • a high thermal conductivity material for example, CNT4 is formed in the hole 1a.
  • the growth temperature is set to be equal to or lower than the melting point of the substrate material, for example, about 800 ° C., and the direction of electric field application is the direction perpendicular to the substrate surface.
  • CNT growth processing is executed. Thereby, CNT4 is formed so that it may stand up from the catalyst material 2 which exists in the bottom face of the hole 1a.
  • the CNT 4 is formed to a length that does not fill the hole 1a, for example, a length of about 200 ⁇ m.
  • CNT is a material having a higher thermal conductivity and better heat dissipation than silicon, which is a substrate material, and the structure in which a plurality of holes 1a of the silicon substrate 1 are partially embedded with CNTs 4 is the heat dissipation mechanism of the applied electronic device. Become. The state of the back surface of the silicon substrate 1 at this time is shown in FIG.
  • the base material 2 and the catalyst material 3 may be formed in a state where the resist mask is formed without removing the resist mask used for the dry etching mask.
  • the resist mask is removed together with the underlying material and the catalyst material existing on the resist mask by ashing or wet etching using a predetermined chemical solution, and then the CNT 4 is formed as shown in FIG.
  • the holes 1 a are filled with the sealing material 5 from the back surface of the silicon substrate 1 to seal the CNTs 4.
  • the remaining part of the hole 1 a is embedded from the back surface of the silicon substrate 1 using a sealing material resistant to various contaminations, for example, an SOG (Spin On Glass) material as the sealing material 5.
  • SOG Spin On Glass
  • a material having good thermal conductivity, for example, Cu may be plated, or a nanodia material may be applied to be used as the sealing material 5.
  • the CNT 4 formed in the hole 1 a is sealed with the sealing material 5.
  • the substrate structure including the heat dissipation mechanism according to the present embodiment is formed.
  • the CNT 4 is sealed with the sealing material 5, and when the electronic device is subsequently formed using the substrate structure, the CNT 4 is kept in an expected state without being contaminated in the various steps. Is done. Therefore, a desired heat dissipation mechanism can be reliably formed in the electronic device.
  • the surface of the silicon substrate 1 may be ground by grinding or the like as long as the base material 2 is not exposed, and the silicon substrate 1 may be appropriately thinned.
  • the silicon substrate 1 itself is provided with a heat radiation mechanism having a relatively simple configuration using a high heat conductive material excellent in heat conduction, for example, CNT.
  • a heat radiation mechanism having a relatively simple configuration using a high heat conductive material excellent in heat conduction, for example, CNT.
  • a semiconductor device including a MOS structure transistor element as a functional element is disclosed as an electronic device together with a manufacturing method thereof.
  • a semiconductor device having various memory elements, capacitor elements, and the like as functional elements can be applied.
  • 7 to 16 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps.
  • symbol is attached
  • the substrate structure disclosed in the first embodiment is applied to a semiconductor device.
  • the substrate structure according to the first embodiment here, the substrate structure of FIG. 5 is used.
  • a MOS transistor element 20a as a functional element and its wiring structure are provided on the surface of the silicon substrate 1.
  • An element layer 31 having 20b is formed on the surface of the silicon substrate 1.
  • FIGS. 17A to 17C and FIGS. 18A to 18B The formation process of the element layer 31 will be described with reference to FIGS. 17A to 17C and FIGS. 18A to 18B. In FIGS. 17A to 17C and FIGS. 18A to 18B, only the surface layer portion of the silicon substrate 1 is shown.
  • a transistor element 20a is formed. Specifically, first, an element isolation structure 11 is formed on the surface layer of the silicon substrate 1 by, for example, an STI (Shallow Trench Isolation) method to determine an element active region. Next, an impurity of a predetermined conductivity type is ion-implanted into the element active region to form the well 12.
  • STI Shallow Trench Isolation
  • a gate insulating film 13 is formed in the element active region by thermal oxidation or the like, a polycrystalline silicon film and a film thickness such as a silicon nitride film are deposited on the gate insulating film 13 by a CVD method, and a silicon nitride film or a polycrystalline silicon film is deposited.
  • the gate electrode 14 is patterned on the gate insulating film 13 by processing the film and the gate insulating film 13 into an electrode shape by lithography and subsequent dry etching.
  • a cap film 15 made of a silicon nitride film is patterned on the gate electrode 14.
  • an impurity having a conductivity type opposite to that of the well 12 is ion-implanted into the element active region to form a so-called extension region 16.
  • a silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surfaces of the gate electrode 14 and the cap film 15 to form the sidewall insulating film 17. Form.
  • the transistor element 20a is formed.
  • an interlayer insulating film 19 is formed. Specifically, for example, silicon oxide is deposited so as to cover the transistor element 20a, and the interlayer insulating film 19 is formed. The surface of the interlayer insulating film 19 is polished by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • a contact hole 19 a is formed in the interlayer insulating film 19.
  • the interlayer insulating film 19 is processed by lithography and dry etching. Thereby, a contact hole 19a exposing a part of the surface of the source / drain region 18 is formed.
  • a contact plug 21 is formed.
  • a conductive material for example, tungsten (W) is deposited on the interlayer insulating film 19 by a CVD method or the like in a thickness for embedding the contact hole 19a.
  • the surface of W is polished by CMP to leave W only in the contact hole 19a.
  • the contact plug 21 formed by filling the contact hole 19a with W is formed.
  • a wiring structure 20b is formed. Specifically, first, a wiring material, for example, an aluminum (Al) alloy is deposited on the interlayer insulating film 19 by a sputtering method or the like, and the Al alloy is processed by lithography and dry etching. As described above, the wiring 22 electrically connected to the contact plug 21 is formed on the interlayer insulating film 19.
  • a wiring material for example, an aluminum (Al) alloy is deposited on the interlayer insulating film 19 by a sputtering method or the like, and the Al alloy is processed by lithography and dry etching.
  • Al aluminum
  • silicon oxide is deposited on the interlayer insulating film 19 so as to cover the wiring 22, thereby forming the interlayer insulating film 23.
  • the interlayer insulating film 23 is processed by lithography and dry etching to form a via hole 23 a that exposes a part of the surface of the wiring 22.
  • a conductive material such as tungsten (W) is deposited on the interlayer insulating film 23 by a CVD method or the like so as to fill the via hole 23a.
  • the surface of W is polished by CMP to leave W only in the via hole 23a.
  • the via plug 24 formed by filling the via hole 23a with W is formed.
  • a wiring material for example, an Al alloy is deposited on the interlayer insulating film 23 by sputtering or the like, and the Al alloy is processed by lithography and dry etching. As a result, the wiring 25 electrically connected to the via plug 24 is formed on the interlayer insulating film 23.
  • the element layer 31 including the transistor element 20a and the wiring structure 20b is formed in the interlayer insulating films 19 and 23.
  • the wiring structure 20b of the element layer 31 is formed of two layers of wiring.
  • the element layer may be formed by stacking wirings in multiple layers.
  • a plurality of holes for example, holes 1 b and 1 c, are formed in the element layer 31 and the silicon substrate 1.
  • the holes 1b and 1c are formed in portions where the transistor element 20a and the wiring structure 20b of the element layer 31 are not formed.
  • the hole 1b is formed so as to expose the surface of the base material 2 at a position corresponding to the non-formation portion on the hole 1a.
  • the hole 1c is the above-mentioned non-formed part, for example, a part corresponding to the two adjacent holes 1a so as to expose the surface of the base material 2.
  • the holes 1b and 1c are formed by partially removing the element layer 31 and the surface layer of the silicon substrate 1 by lithography and dry etching. Depending on the formation status of the transistor element 20a and the wiring structure 20b in the element layer 31, only the hole 1b or only the hole 1c may be formed.
  • a catalyst material 32 is formed on the bottom surfaces of the holes 1b and 1c.
  • the catalyst material is deposited to a thickness of several nm, for example, about 1 nm by a vacuum evaporation method or the like.
  • a mixed material of one or more selected from Co, Ni, Fe and the like and one or more selected from Ti, TiN, TiO 2 , V, Al and the like is used. .
  • Co / Ti or Co / V is selected.
  • the catalyst material 32 is formed on the bottom surfaces of the holes 1b and 1c.
  • oblique milling is performed on the surface of the element layer 31 to remove the base material and the catalyst material deposited on the back surface of the element layer 31.
  • oblique deposition may be performed on the surface of the element layer 31, and the catalyst material deposited on the back surface of the element layer 31 may be deactivated.
  • a high thermal conductive material for example, CNT 33 is formed in the holes 1b and 1c. More specifically, the temperature is set so as not to adversely affect the element layer 31 by plasma CVD or thermal CVD, for example, about 400 ° C., and the CNT growth process is performed with the direction of application of the electric field being perpendicular to the substrate surface. To do. Thereby, the CNT 33 is formed so as to stand up from the catalyst material 32 existing on the bottom surfaces of the holes 1b and 1c. The CNT 33 is formed to have a length that fills the holes 1b and 1c. The CNT 4 in the hole 1 a and the CNT 33 in the holes 1 b and 1 c are thermally connected via the catalyst materials 3 and 32 and the base material 2.
  • the catalyst material 32 may be formed in a state where the resist mask is formed without removing the resist mask.
  • CNTs 33 are formed as shown in FIG.
  • a plurality of holes are formed in the element layer 31 and the silicon substrate 1.
  • the holes 10d and 10e are formed in the portion where the transistor element 20a and the wiring structure 20b of the element layer 31 are not formed.
  • the hole 1d is formed so as to expose the surface of the catalyst material 3 at a position corresponding to the hole 1a, which is the above-mentioned non-formed part.
  • the hole 1e is formed in such a manner that the surface of the catalyst material 3 is exposed at a portion corresponding to the above-described non-formed portion, for example, on two adjacent holes 1a.
  • the holes 1d and 1e are formed by removing the element layer 31 and part of the surface layer of the silicon substrate 1 and the base material 2 by lithography and dry etching.
  • a catalyst material 32 is formed on the bottom surface of the hole 11e by vacuum deposition or the like. Thereafter, oblique milling is performed on the surface of the element layer 31 to remove the catalyst material deposited on the back surface of the element layer 31. Then, the CNTs 33 are formed as in FIG.
  • a heat conductive layer 34 is formed on the surface side of the silicon substrate 1.
  • a film having excellent thermal conductivity here DLC (Diamond Like Carbon)
  • DLC Diamond Like Carbon
  • the heat conductive layer 34 is thermally connected to the CNTs 33 in the holes 1c and 2d.
  • the back surface of the silicon substrate 1 is ground to remove the sealing material 5.
  • the back surface of the silicon substrate 1 is ground by grinding or the like until the tip of the CNT 4 in the hole 1a is exposed.
  • the silicon substrate 1 is appropriately thinned and the sealing material 5 is removed.
  • the total thickness of the silicon substrate 1 and the element layer 31 is, for example, about 50 ⁇ m to 100 ⁇ m.
  • the sealing material 5 in the hole 1a may remain.
  • a heat conductive layer 35 is formed on the back side of the silicon substrate 1.
  • a film having excellent thermal conductivity here DLC
  • the heat conductive layer 35 is thermally connected to the CNT 4 in the hole 1a. Thereafter, a dicing process is performed, and each semiconductor chip is cut out.
  • the thermally connected CNTs 4 and 33 and the heat conductive layers 34 and 35 constitute a heat dissipation mechanism for a semiconductor device on the front and back surfaces of the silicon substrate 1 through the silicon substrate 1.
  • the heat generated in the element layer 31 and the like is transmitted in the vertical direction by the CNTs 4 and 33 and transmitted in the horizontal direction by the heat conductive layers 34 and 35, and is efficiently exhausted.
  • FIG. 19 is a cross-sectional view showing a schematic configuration of a laminated semiconductor device according to a modification of the second embodiment.
  • a plurality of the semiconductor devices of FIG. 16 (referred to as semiconductor devices 41) manufactured according to the second embodiment are stacked via the adhesive layer 42 to manufacture a stacked semiconductor device.
  • the adhesive layer 42 is made of a material having excellent adhesion between the heat conductive layers 34 and 35 and high heat conductivity, for example, indium or a metal paste, and has a thickness of about several ⁇ m.
  • the heat conductive layer 34 of the lower semiconductor device 41 and the heat conductive layer 35 of the upper semiconductor device 41 are thermally connected via the adhesive layer 42, and the heat dissipation of each semiconductor device 41 is performed.
  • the mechanism is thermally integrated. With this configuration, extremely efficient exhaust heat is realized.
  • the upper and lower semiconductor devices 41 may be bonded and fixed by the adhesive layer 42 without forming the heat conductive layers 34 and 35 in the semiconductor device 41. good. With this configuration, a thin and small stacked semiconductor device is realized as a whole.
  • FIG. 21 to 23 are schematic cross-sectional views showing main steps of the semiconductor device manufacturing method according to the third embodiment.
  • the same components as those of the semiconductor device according to the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
  • an amorphous carbon layer 51 and a catalyst layer 52 are sequentially formed on the surface side of the silicon substrate 1. Specifically, first, an amorphous carbon layer 51 is formed to a thickness of, for example, about 60 nm by a sputtering method or the like so as to cover the surface of the element layer 31. The amorphous carbon layer 51 is in contact with the CNTs 33 in the holes 1c and 2d. Next, a catalyst layer 52 is formed on the amorphous carbon layer 51 as a catalyst for graphene growth described later. The catalyst layer 52 is formed to a thickness of, for example, about 100 nm by sputtering or the like using at least one selected from Co, Ni, Pt, Fe, and the like, for example, Co as a material.
  • an amorphous carbon layer 53 and a catalyst layer 54 are sequentially formed on the back side of the silicon substrate 1.
  • the amorphous carbon layer 53 is formed to a thickness of, for example, about (60 nm) by a (sputtering) method or the like so as to cover the back surface of the silicon substrate 1.
  • the amorphous carbon layer 53 is in contact with the CNT 4 in the hole 1a.
  • a catalyst layer 534 serving as a catalyst for graphene growth described later is formed on the amorphous carbon layer 53.
  • the catalyst layer 54 is formed to a thickness of, for example, about 100 nm by sputtering or the like using at least one selected from Co, Ni, Pt, Fe, and the like, for example, Co as a material.
  • graphene layers 55 and 56 are formed by heat treatment.
  • the structure of FIG. 22 is heat-treated at about 400 ° C. to 1000 ° C., for example, about 800 ° C.
  • the catalyst layer 52 functions as a catalyst, and the amorphous carbon of the amorphous carbon layer 51 becomes graphene, and the graphene layer 55 is formed.
  • the catalyst layer 54 functions as a catalyst, the amorphous carbon of the amorphous carbon layer 53 becomes graphene, and the graphene layer 56 is formed.
  • the CNT 33 is regrown at the contact portion with the CNT 33 and is integrally formed with the graphene. Thereby, the excellent thermal connection between the CNT 33 and the graphene layer 55 is ensured.
  • the CNT4 is regrown at the contact portion with the CNT4 and is integrally formed with the graphene. This ensures an excellent thermal connection between the CNT 4 and the graphene layer 56. Thereafter, a dicing process is performed, and each semiconductor chip is cut out.
  • the heat radiation mechanism of the semiconductor device is configured on the front and back surfaces of the silicon substrate 1 through the silicon substrate 1 by the CNTs 4 and 33 and the graphene layers 55 and 56 that are integrally and surely thermally connected. Is done.
  • the heat generated in the element layer 31 and the like is transmitted in the vertical direction by the CNTs 4 and 33, and is transmitted in the horizontal direction by the graphene layers 55 and 56, and is exhausted extremely efficiently.
  • FIG. 24 is a cross-sectional view illustrating a schematic configuration of a stacked semiconductor device according to a modification of the third embodiment.
  • a plurality of the semiconductor devices of FIG. 22 (referred to as semiconductor devices 61) manufactured according to the third embodiment are stacked via the adhesive layer 62 to manufacture a stacked semiconductor device.
  • the adhesive layer 62 is made of a material having excellent adhesion between the catalyst layers 52 and 54 and high thermal conductivity, for example, indium or a metal paste, and has a thickness of about several ⁇ m.
  • the catalyst layer 52 of the lower semiconductor device 61 and the catalyst layer 54 of the upper semiconductor device 61 are thermally connected via the adhesive layer 62, and the heat dissipation mechanism of each semiconductor device 61 is Thermally integrated. With this configuration, extremely efficient exhaust heat is realized.
  • Appendix 1 a substrate having a heat dissipation mechanism formed on the back surface; An element layer including a functional element formed on the surface of the substrate; The heat dissipation mechanism is A first highly thermally conductive material having a higher thermal conductivity than the substrate, formed in a plurality of first holes formed on the back surface of the substrate; An electronic device comprising: a first thermally conductive film thermally connected to the first high thermal conductivity material so as to cover a back surface side of the substrate.
  • Appendix 2 The electronic device as set forth in Appendix 1, wherein the first high thermal conductivity material is a first carbon nanotube.
  • the first thermal conductive film is formed with graphene,
  • the electronic device according to appendix 2 further comprising a first catalyst film for growing the graphene covering the first heat conductive film.
  • the heat dissipation mechanism includes a first catalyst for growing the first carbon nanotubes between a bottom surface of the first hole and an end portion of the first carbon nanotubes.
  • Appendix 5 The electronic device according to appendix 4, wherein the heat dissipation mechanism includes a first base material between the first catalyst and an end of the first carbon nanotube.
  • Appendix 8 The electronic device according to appendix 6 or 7, wherein the second high thermal conductivity material is a second carbon nanotube.
  • the second thermal conductive film is formed with graphene,
  • the electronic device according to appendix 8 further comprising a second catalyst film for growing the graphene covering the second heat conductive film.
  • a substrate (Appendix 11) a substrate; A heat dissipation mechanism formed on the back surface of the substrate, The heat dissipation mechanism is A high thermal conductivity material having a higher thermal conductivity than the substrate, formed so as to be embedded from the bottom surface of the plurality of holes formed on the back surface of the substrate to the middle depth of the hole; A substrate structure comprising: a sealing material that embeds a remaining portion in the hole from the surface of the substrate and seals the high thermal conductivity material in the substrate.
  • (Appendix 15) A step of forming a plurality of first holes on the back surface of the substrate; Forming a first high thermal conductivity material having a higher thermal conductivity than the substrate in the first hole; Forming an element layer including a functional element on the surface of the substrate; Forming a first thermally conductive film thermally connected to the first high thermal conductivity material so as to cover a back surface side of the substrate.
  • Appendix 17 A step of forming a first catalyst film for growing graphene so as to cover the first thermal conductive film; The method for manufacturing an electronic device according to appendix 16, further comprising a step of heat-treating the first thermally conductive film to form graphene.
  • the first high thermal conductive material is formed, Filling the first hole from the surface of the substrate with a sealing material, and further sealing the first high thermal conductivity material in the substrate; 18.
  • the supplementary note 19 further comprising a step of forming a second thermal conductive film thermally connected to the second high thermal conductivity material so as to cover the surface side of the substrate.
  • (Appendix 23) A step of forming a plurality of holes on the back surface of the substrate; Forming a high thermal conductivity material having a higher thermal conductivity than the substrate so as to be embedded from the bottom surface of the hole to an intermediate depth of the hole; Filling the inside of the hole with a sealing material from the surface of the substrate, and sealing the high thermal conductivity material within the substrate.

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

L'invention concerne un dispositif semi-conducteur comprenant un substrat en silicium (1) et une couche d'élément (31). Le substrat en silicium (1) présente un mécanisme de dissipation thermique formé sur la surface arrière. La couche d'élément (31) est formée sur une surface avant du substrat en silicium (1) et elle comprend un élément transistor (20a). Le mécanisme de dissipation thermique comprend un matériau en carbone, par exemple, un nanotube de carbone (NTC) et un matériau en carbone, par exemple, un film de graphène multicouche. Le matériau en carbone, par exemple le CNT (4), est un matériau hautement thermoconducteur formé dans une pluralité de premiers orifices (1a) formés sur une surface arrière du substrat en silicium et présente une conductivité thermique supérieure à celle du substrat en silicium (1). Le matériau en carbone, par exemple le film de graphène multicouche, est un film thermoconducteur qui est thermiquement connecté avec le CNT (4) de manière à recouvrir le côté surface arrière du substrat en silicium (1). Grâce à une telle configuration, il est possible d'obtenir un substrat en silicium dans lequel est intégré un matériau en carbone qui dissipe la chaleur à un rendement extrêmement favorable et présentant une configuration relativement simple, il également possible d'obtenir un dispositif électronique hautement fiable.
PCT/JP2013/078044 2013-01-18 2013-10-16 Dispositif électronique, procédé de fabrication correspondant, structure de substrat et procédé de fabrication correspondant WO2014112166A1 (fr)

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US9397023B2 (en) 2014-09-28 2016-07-19 Texas Instruments Incorporated Integration of heat spreader for beol thermal management
US9496198B2 (en) * 2014-09-28 2016-11-15 Texas Instruments Incorporated Integration of backside heat spreader for thermal management
JP2021019144A (ja) * 2019-07-23 2021-02-15 日立造船株式会社 電気デバイスユニット

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US9991187B2 (en) 2018-06-05
TW201431018A (zh) 2014-08-01

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