JP5355863B2 - 三次元半導体デバイスの製造方法、基板生産物の製造方法、基板生産物、及び三次元半導体デバイス - Google Patents
三次元半導体デバイスの製造方法、基板生産物の製造方法、基板生産物、及び三次元半導体デバイス Download PDFInfo
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Description
M.Kawano et al.,"A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer",International Electron Devices Meeting (IEDM) 2006, program No. 21.5
図4に示すように、シリコン基板80の表面80a上にシリコン酸化膜81を成膜する。シリコン酸化膜81は、後述する層間配線用の穴をエッチングにより形成する際のエッチングマスクとなる膜である。シリコン酸化膜81は、例えばプラズマCVDなどの化学気相成長法により形成される。なお、シリコン基板80をエッチングする際のエッチングマスクとして機能すれば、シリコン酸化膜81に代えて他の材料からなる膜(例えば、シリコン窒化膜など)を成膜してもよい。
続いて、図8に示すように、シリコン基板80の表面80a、および穴82の内面に絶縁膜(シリコン酸化膜)84を形成する。絶縁膜84は、例えばシリコン基板80を900℃〜1000℃といった高温の環境におき、酸素、もしくは酸素と水素の混合ガスを供給してシリコン基板80の表面80aおよび穴82の内面を熱酸化させるとよい。このとき、上述したような高温で処理するのは、絶縁膜84が微細な穴82の内面に均一に形成されるようにするためである。
続いて、図9に示すように、シリコン基板80の穴82を犠牲材料85により埋め込む。犠牲材料85としては、後述する集積回路形成工程において半導体の熱処理に耐えられる材料であり、且つ、後述する配線形成工程において絶縁膜84に対し選択的に除去可能な材料であれば良い。このような材料としては、例えば多結晶シリコン(ポリシリコン)及びシリコンゲルマニウム(SiGe)のうち少なくとも一方を主に含む材料が好適である。この埋込工程では、例えば犠牲材料85としてシリコンゲルマニウム(SiGe)をCVD法によりシリコン基板80の表面80a上に堆積させつつ、穴82を埋め込む。なお、このとき、犠牲材料85のうち穴82の第2の部分82bに埋め込まれた部分は、犠牲材料85の他の部分より径が大きい拡径部85aとなる。また、穴82(特に第2の部分82b)に埋め込まれた犠牲材料85の内部には、ボイド(空洞)85bが形成される場合があるが、何ら支障はない。
続いて、図11に示すように、集積回路を含む集積回路層90をシリコン基板80の表面80a上に形成する。まず、FEOL(Front End of Line)と呼ばれる、トランジスタなどの複数の半導体素子86を形成する工程を中心としたプロセスを実施する。すなわち、半導体素子86が有する各種半導体層(例えば、シリコン基板80の表面80aの所定領域に不純物を添加して形成されたp型半導体層やn型半導体層)、ゲート絶縁膜、各種電極などを形成する。n型半導体層やp型半導体層を形成する際には、フォトレジストを介して不純物イオンを注入したのち、この不純物イオンをシリコン原子と結合させるため加熱処理(アニール)を行うが、このとき、シリコン基板80は例えば800℃〜1000℃といった高温の環境下におかれる。半導体素子86を形成した後、半導体素子86を覆うようにシリコン酸化膜を堆積させることにより絶縁層87の下層部を形成する。
続いて、シリコン基板80の裏面80bよりシリコン基板80を薄化(シニング)する。薄化の前に、図13に示すように、シリコン基板80の表面80a側、すなわち集積回路層90の上面を、接着剤層91を介してガラス製の支持材92に貼り付ける。支持材92としては、平坦な表面92aを有する板状の部材が用いられ、また、接着剤層91を構成する接着剤としては、UV照射や熱処理により剥離可能な材料が好適である。
続いて、図16に示すように、シリコン基板80の裏面80b上にシリコン酸化膜93を成膜する。シリコン酸化膜93は、後の工程において犠牲材料85をエッチングにより除去する際のエッチングマスクとなる膜である。シリコン酸化膜93は、例えばプラズマCVDなどの化学気相成長法により形成される。なお、犠牲材料85をエッチングする際のエッチングマスクとして機能すれば、シリコン酸化膜93に代えて他の材料からなる膜(例えば、シリコン窒化膜など)を成膜してもよい。
続いて、図22に示すように、基板生産物100Aをビルドアップ基板101上に実装する。このとき、ビルドアップ基板101に設けられたバンプ102の位置と基板生産物100Aの層間配線98の位置とが一致するように、ビルドアップ基板101と基板生産物100Aとの相対位置を調整する。そして、加熱等によりバンプ102を溶融させてバンプ102と層間配線98とを接合することにより、基板生産物100Aの集積回路とビルドアップ基板101上の回路とを層間配線98を介して電気的に接続する。その後、基板生産物100Aに接着剤層91を介して接合されていた支持材92を基板生産物100Aから取り外す(図23)。
Claims (4)
- 基板の表面に、最初に、反応性イオンエッチングにより、次に、プラズマエッチングにより、有底の穴を形成する穴形成工程と、前記穴形成工程において形成される前記穴は、前記基板の表面から前記基板の厚さ方向に垂直に延びる円柱形状を有する第1の部分と、前記第1の部分より内径が大きい第2の部分とを有し、
CVD法により多結晶シリコン及びシリコンゲルマニウムのうち少なくとも一方を含む犠牲材料を前記基板の表面上に堆積させつつ、前記犠牲材料により前記穴を埋め込む埋込工程と、
前記基板の表面上に堆積した前記犠牲材料を化学機械研磨により除去する工程と、
前記犠牲材料と接する配線パターンを有する集積回路を前記基板の表面に形成する集積回路形成工程と、
前記基板の裏面より前記基板を薄化することにより、前記穴を貫通させると共に前記基板の裏面から前記犠牲材料の一部を露出させる薄化工程と、
前記犠牲材料を除去して金属材料を埋め込むことにより前記基板を貫通する層間配線を形成する配線形成工程と、
前記基板を他の基板上に積み重ね、前記集積回路と前記他の基板上の回路とを前記層間配線を介して電気的に接続する積層工程と
を備えることを特徴とする、三次元半導体デバイスの製造方法。 - 前記穴の内面に絶縁膜を形成する絶縁膜形成工程を、前記穴形成工程と前記埋込工程との間に更に備えることを特徴とする、請求項1に記載の三次元半導体デバイスの製造方法。
- 前記基板がシリコン基板であり、前記絶縁膜がシリコン酸化膜であることを特徴とする、請求項2に記載の三次元半導体デバイスの製造方法。
- 基板の表面に、最初に、反応性イオンエッチングにより、次に、プラズマエッチングにより、有底の穴を形成する穴形成工程と、前記穴形成工程において形成される前記穴は、前記基板の表面から前記基板の厚さ方向に垂直に延びる円柱形状を有する第1の部分と、前記第1の部分より内径が大きい第2の部分とを有し、
CVD法により多結晶シリコン及びシリコンゲルマニウムのうち少なくとも一方を含む犠牲材料を前記基板の表面上に堆積させつつ、前記犠牲材料により前記穴を埋め込む埋込工程と、
前記基板の表面上に堆積した前記犠牲材料を化学機械研磨により除去する工程と、
前記犠牲材料と接する配線パターンを有する集積回路を前記基板の表面に形成する集積回路形成工程と、
前記基板の裏面より前記基板を薄化することにより、前記穴を貫通させると共に前記基板の裏面から前記犠牲材料の一部を露出させる薄化工程と、
前記犠牲材料を除去して金属材料を埋め込むことにより前記基板を貫通する層間配線を形成する配線形成工程と
を備えることを特徴とする、基板生産物の製造方法。
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JPH047845A (ja) * | 1990-04-25 | 1992-01-13 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
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JP2004128063A (ja) * | 2002-09-30 | 2004-04-22 | Toshiba Corp | 半導体装置及びその製造方法 |
CN101048868B (zh) * | 2004-08-20 | 2010-06-09 | 佐伊科比株式会社 | 具有三维层叠结构的半导体器件的制造方法 |
JP4365750B2 (ja) * | 2004-08-20 | 2009-11-18 | ローム株式会社 | 半導体チップの製造方法、および半導体装置の製造方法 |
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