Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
  • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
  • G01N21/84—Systems specially adapted for particular applications
  • G01N21/88—Investigating the presence of flaws or contamination
  • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/302—Contactless testing
  • G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
  • G01R31/311—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Definitions

• Embodiments of the present invention generally relate to integrated circuit analysis techniques and, more particularly, a method and apparatus for conducting automated integrated circuit analysis.
• Embodiments of the present invention generally comprise an apparatus and/or method for conducting non-invasive automated integrated circuit analysis, substantially as shown in the and/or described in connection with at least one of the figures, as set forth more completely in the claims.
• Figure 1 depicts a block diagram of an system for conducting automated integrated circuit analysis in accordance with at least one embodiment of the invention
• Figure 2 depicts a block diagram of the pump probe assembly of Figure 1 in accordance with at least one embodiment of the invention
• Figure 3 depicts a block diagram of one ultrafast laser pump/probe detector assembly of Figure 1 in accordance with at least one embodiment of the invention
• Figure 4 depicts a block diagram of the system and apparatus for performing super-resolved imaging in accordance with at least one embodiment of the invention
• Figure 5 depicts a block diagram of the data processor subsystem in accordance with at least one embodiment of the invention.
• Figure 6 depicts the autonomous device netlist extractor subsystem in accordance with at least one embodiment of the invention
• Figure 7 depicts a flow diagram of a method for automatically and noninvasive ⁇ extracting a device netlist in accordance with at least one embodiment of the invention
• Figure 8 depicts a flow diagram of a method for detecting logic cells using a recognition algorithm in accordance with at least one embodiment of the invention.
• Figure 9 depicts a flow diagram of a method for identifying logic cell interconnects in accordance with at least one embodiment of the invention.
• Figure 10 depicts a flow diagram of a method for identifying activity in logic cells in accordance with at least one embodiment of the invention.
• Figure 1 1 depicts a flow diagram of a method for rapidly simulating object reflectivity using an electromagnetic simulator in accordance with at least one embodiment of the invention.
• Embodiments of the present invention comprise a method and simultaneously scannable dual laser confocal microscope apparatus for conducting automated integrated circuit analysis.
• the apparatus employs a plurality of methods in order to create a plurality of images of an integrated circuit collected under varied operational conditions, which are then combined and stored in a database as a hyper-dimensional representation (also referred to as hyper-dimensional imagery) of the integrated circuit under test.
• a recognition algorithm processes the hyper- dimensional imagery stored in the database structure to extract the presence and identity of logic cell elements of the integrated circuit under test.
• the recognition algorithm operates a control loop that sequentially detects the location of device activity within a logic cell followed by detection of electronic waveforms at those locations that exhibit sufficient activity above a threshold.
• FIG. 1 depicts a block diagram of a system 100 for conducting automated integrated circuit analysis in accordance with at least one embodiment of the invention.
• the system 100 comprises an analyzer apparatus 104 and an integrated circuit (IC) assembly under test 102.
• IC integrated circuit
• the IC assembly under test 102 comprises a functional integrated circuit mounted to a 6-axis (x, y, z, anglel , angle2, angle3) positioning stage.
• the analyzer apparatus 104 comprises a pump/probe assembly 1 18, a controller and data processor 1 16, autonomous device netlist extractor 120, distributed computing cluster 140, and database 130.
• the pump/probe assembly contains pump laser 108, probe laser 109, optics 1 10 for simultaneously scanning and coupling the pump and probe beams, DC reflectivity emission detector 1 12 and AC-coupled RF emission detectors 1 13.
• the analyzer apparatus 104 is capable of performing several types of laser scanning of the IC under test 102, whereby the pump laser is able to locally change the way the device functions, by altering the timing or logic state of the device 102, while simultaneously measuring the effect of the change elsewhere on the device 102 using the probe laser.
• the pump/probe assembly 1 18 generates a plurality of images of the IC under test.
• the pump/probe images and waveform data are then stored and combined with standard DC reflectivity images and electronic waveform data by the autonomous device netlist extractor (ADNE) 120 to create a netlist of the integrated circuit under test.
• ADNE autonomous device netlist extractor
• the controller and data processor 1 16 processes the measured RF power from the AC- coupled RF emission detectors 1 13 (which measure RF in selected frequency ranges) to produce a spatio-temporal evolution of the voltage on the integrated circuit under test as an activity map.
• the ADNE 120 may use the activity map to determine interconnections between elements of the integrated circuit under test.
• the pump/probe assembly 1 18 forms a laser-scanning microscope that scans a focused probe laser spot 109 over the integrated circuit (IC) under test 102 while simultaneously altering the functionality of the IC 102 using the pump laser 108.
• the simultaneous scanning and altering of functionality adds additional dimensions to the hyper-dimensional imagery of the IC under test 102, resulting in increased accuracy of logic cell detections.
• the pump/probe assembly 1 18 uses the pump laser (a first laser) to pump a selected region of the integrated circuit under test with photocarriers and uses the probe laser (a second laser) to monitor the effect the pumping has on the integrated circuit under test.
• the laser used to generate the plurality of images is at least one of continuous wave, modulated, or a pulsed laser.
• FIG. 2 depicts a block diagram of the pump/probe assembly 1 18 of Figure 1 in accordance with at least one embodiment of the invention.
• the pump/probe assembly 1 18 comprises a lock-in amplifier 210, RF filter and amplifier 209, current amplifier 207, probe laser 218, probe detection optics 208, probe scan optics 206, coupling optics and objective 205, pump scan optics 204, pump detection optics 220, pump modulator 214, pump laser source 216, and signal generator 212.
• the pump/probe assembly 1 18 utilizes various wavelengths of laser light, various scanning patterns, and various laser modulations to produce a plurality of images of the integrated circuit under test 102.
• This hyper-dimensional imagery facilitates performance of a multimodal image analysis resulting in a detailed representation of the integrated circuit which can be used to distinguish circuit features with greater fidelity than any single image.
• the first and second lasers 216 and 218 have two different wavelengths, for example, 1064 and 1319 nm. Those of ordinary skill in the art will recognize that these frequencies are merely exemplary and are not limiting. Depending on design choice, neither, both or one of the lasers 216 and 218 may be amplitude, frequency or phase modulated. According to other embodiments, the lasers 216 and 218 may be mode-locked ultrafast lasers with pulse lengths ranging from 100 fs (femtoseconds) to 100 ps (picoseconds).
• the probe laser 218 has a wavelength of approximately 1319 nm and is not modulated, while the second pump laser 216 has a wavelength of 1064 nm and is amplitude modulated (e.g., pulsed) using modulator 214 and signal generator 212.
• the laser beams respectively pass through microscope optics 204 and 206 and transmit through common optics 205 including a dichroic beamsplitter and high variable numerical aperture air gap or solid immersion lens objective and focus on one or more of the active device layers within the IC 102, e.g., the layer containing the poly gates.
• Reflected laser light travels back through the microscope optics 204 and 206 which separate the pump and probe return signals to be refocused onto emission detectors using optics 208 and 220.
• the structure of the components used to receive the lasers may vary within scanning type and other factors.
• the output of the probe laser detector 208 is coupled to a current amplifier 207 and passed to a lock-in amplifier 210 that is synchronized to the signal generator 212, whose output is directed to an A D converter 200, which shares a readable memory with the controller and data processor 1 16.
• the pump laser detector signal is amplified and also directed to detection electronics in the controller and data processor 1 16.
• the device may be operated using digital input/output lines 215 during scanning.
• galvanometer 1 and galvanometer 2 used to scan the lasers 216 and 218 are operated from the controller and data processor 1 16. In this fashion, the very small response of the circuit to the pump laser is sensed and amplified and corresponding data is communicated to the database 130 through the ADNE 120.
• Charge flow imaging is realized by locking the probe laser to the pump repetition frequency.
• Charge flow imaging is a method used to enhance different features within the IC 102 in order to improve logic cell detection by imaging the feature's response to injected charge carriers.
• Charges are injected locally by the pump laser at a fixed frequency (typically 1 -500 MHz), and the probe laser is tuned to that same frequency. Small signals generated by the pump laser are sensed when the lock-in amplifier 210 is tuned to the same pump frequency. Images of the device produced at the pump laser frequency then reveal the charge flow throughout the IC which can be used to resolve additional features in an IC such as the polysilicon gates.
• phase imaging method is a further refinement of the charge flow method which further highlights the contrast between different components within the IC 102.
• Phase imaging is achieved by uniquely color-coding the phase of the lock-in signal and plotting the detected color-coded phase as a function of probe laser coordinate.
• charge flow imaging is achieved on picosecond time-scales to allow glimpsing the position of the charge carriers as they move away from the injection point created by the pump laser (e.g., pump laser 216 shown in Figure 2).
• the pump laser 218 and the probe laser 218 are mode locked and synchronized.
• the pump laser 216 and the probe lasers 218 are optionally derived from the same source laser.
• the ultrafast laser is split into a pump arm 302 and a probe arm 304, and the pump arm 302 and the probe arm 304 are independently modulated.
• the resulting pump/probe signal is measured again at a lock-in frequency that is given by the sum or difference of the two modulation frequencies, or one of its harmonics.
• the arrival of the optical signals on the pump and probe arms can be adjusted in order to observe the charge location in the device containing the IC 102 at various fixed points in time following the arrival of the pump.
• the unique material-specific temporal response to injected free carriers enhances material contrast within the IC by adjusting the relative delay between the pump arm 302 and the probe arm 304. In this way, the dynamic nature of charge flow through the device, as well as corresponding thermal transport on sub pico-second times scales can be observed.
• the enhanced material contrast directly improves the performance of registration and object recognition algorithms.
• the laser beams are scanned in accordance with a specific pattern across the surface of the integrated circuit under test 102.
• the scanning is performed by the microscope optics 204 and 206 using two, independently adjustable mirror pairs (galvanometers).
• the integrated circuit under test may be powered and also have test signals generated from within the data processor and controller 1 16 and supplied by digital input/output lines 215 (known as test vectors) applied to the integrated circuit input ports.
• test vectors digital input/output lines 215
• additional information may be gathered based upon whether or not the integrated circuit is powered during a laser scan, or has specific sets of test vectors being applied during laser scanning.
• Each state of the integrated circuit while being scanned may result in a separate image to be used in the multimodal analysis. Details of the operation of the pump probe assembly 1 18 during scanning of the integrated circuit under test 102 are described with reference to the figures below.
• a second method enabled by the embodiment in Figure 2 is referred to as "waveform suppression".
• the lock-in detector is bypassed and the amplified and filtered RF signals (209) are measured directly by electronics in the Data Processor and Controller 1 16.
• an active device 102 is stimulated by test vectors generated by the data processor and controller 1 16.
• Connections between logic cells are directly observed by selectively deactivating logic cells by fixing the focus of the pump laser 216 at the output of the logic cell. While holding the pump laser fixed at the logic cell output, the probe laser can identify those logic cells that are connected to the de-activated logic cells by measuring changes in the waveform. By iteratively pumping the output of all those previously suppressed (as detected by the probe laser) logic cells, one can determine the unique network of connections between active logic cell elements.
• FIG. 3 is a block diagram of an ultrafast laser embodiment of the pump/probe assembly 1 18 of Figure 1 , in accordance with exemplary embodiments of the present invention.
• Waveform suppression can be applied using the pulsed laser system 300.
• One form of waveform suppression is referred to as "waveform modulation”.
• waveform modulation first, the pulse repetition of two ultrafast lasers is synchronized with a synchronization unit 310. Alternatively, one may separate a portion of a single laser source to be used as the probe.
• both the pump and probe laser pulse trains are amplitude modulated by an RF source 328 at different frequencies. The relative arrival time of the two pulses is controlled using an optical delay line 320.
• the signal is measured using a frequency mixer 330 and lock-in amplifier 332 before the signal is sent to the data processor 1 16.
• the early arrival of one pulse is then used to affect the output of one logic cell of interest, and the temporal response can be measured elsewhere in the IC with the probe at a later time determined by the optical delay line 320.
• important parameters of the device are extracted such as the local time delays between two logic cells and local electrical impedance, which are in turn used to isolate timing errors or characterize how local variations in the manufacturing process affects device performance.
• FIG. 4 depicts a block diagram of the system 400 for performing super- resolved imaging in accordance with at least one embodiment of the invention.
• the system 400 comprises a probe arm 402 and a pump arm 404, where the structured probe arm laser is laser 218, an ultrafast laser and the structured pump arm laser is laser 216. Lasers 216 and 218 are synchronized via synchronization unit 310.
• a grating assembly 450 or similar wavefront distortion device e.g. holographic plate, wavefront distortion device, or phase plate
• wavefront distortion device e.g. holographic plate, wavefront distortion device, or phase plate
• the pump arm 404 is able to project a pattern of carriers onto the integrated circuit which can then be observed by the probe arm 402 of the microscope.
• This particular embodiment in Figure 4 enables a type of super- resolved imaging method (to be described below) whereby the several images created by varying patterns of injected charge carriers in the integrated circuit are used together to develop an image of the IC under test that has an improved resolution compared to any single image of the device.
• FIG. 5 depicts a block diagram of the controller and data processor 1 16 of Figure 1 in accordance with at least one embodiment of the invention.
• the controller and data processor 1 16 may be a general-purpose computer with memory 502 containing stored data and executable code that perform several functions comprising sensing and sending data to the pump/probe apparatus 1 18, communication with the autonomous device netlist extractor 120 or the database 130 over a network connection 530.
• the controller and data processor 1 16 comprises a central processing unit (CPU) 550, a memory 502 and support circuits 595.
• the memory 502 stores array formation 520, configuration files 540, activity detector 545, microscope controller 555 and a database client 565.
• the processor 1 16 further comprises devices 560.
• the devices 560 comprise an A/D converter 570, a D/A converter 580, a digital IO 590 and an FPGA 595.
• the database client 565 communicates with the database 130 via the support circuits 595 and the network interface 530. Signals are sent back and forth to the pump/probe apparatus over the devices 560.
• Galvanometer controls and laser scanning signals are handled by analog to digital (A/D) converter 570 and digital to analog (D/A) converter 580.
• Digital signals used to operate the IC under test 102 are handled by a digital I/O device 590.
• the microscope controller 555 coordinates and executes all experiments with the pump/probe apparatus by reading arrays from one or more configuration files 540 that are used to set the microscope stage coordinates (region of the IC to examine), galvanometer coordinates (scan field of view), desired microscope objective, test vector set, or other equipment settings such as the power supplied to the circuit or drawn by the circuit. Commands are facilitated through the use of one or more CPUs (central processing units) 555 and support circuits 595.
• RF signals may be digitized and transferred to the FPGA to carry out rapid signal analysis.
• the FPGA may be used to trigger the pump/probe assembly to acquire a signal when an RF signal of a certain characteristic is sensed by the signal-based triggering may be used by the FPGA to acquire
• data arrays 520 consisting of tuples of configuration parameters and measurements.
• data arrays are passed to the database 130 from the database client 565 over a network via the network interface 530, but to expedite data acquisition it is critical to acquire and transmit only critical data to the database. Such a case may occur for those data sources present only in a subset of the device 102.
• One example of that type of data source is the electronic waveform measured from the probe detector arm, wherein acquisition may require averaging of many hundreds or thousands of waveforms.
• control system and data processor 500 also contains an Activity Detection algorithm 545, present either in memory 502 or programmed onto an FPGA 595, which is able to both determine with fewer samples than a waveform whether there exists a waveform at all and where the optimal location to acquire waveforms is within the particular field of view.
• a Database Client 565 with the Auto-DNE subsystem 120, which is able to populate the configuration files 540 with candidate locations for acquiring waveforms based on the presence of detected components in the field of view, i.e. logic cells.
• the database 130 contains metadata for the various detected logic cells, including precise locations where waveforms will be present.
• the support circuits 595 may comprise one or more well-known circuits that facilitate and support the functionality of the CPU 550. Such circuits include, but are not limited to, clock circuits, input/output circuits, cache, buses, communications circuits, peripheral drivers and the like.
• FIG. 6 depicts the autonomous device netlist extractor subsystem in accordance with at least one embodiment of the invention.
• the Autonomous Device Netlist Extractor 600 comprises a CPU 602, memory 604, support circuits 695 and a network interface 660.
• Memory 604 may comprise well-known memory devices including random-access memory and read-only memory.
• the memory 604 stores executable code and data to enable the CPU 602 to produce a netlist for the IC under test 102 using the analyzer apparatus 104.
• the memory 604 comprises a Database Client 610, a hyper-dimensional logic cell recognition module 620, super- resolution reconstruction module 620, an image registration module 640, a test vector generator 655, an interconnect extractor 670, a device configuration manager 680, and a rapid electromagnetic simulator 690.
• Each of these controllers, analyzers, imagers, and generators may be implemented as individual software modules or may be a portion of a larger singular software module. In either instance, these modules or portions thereof are executed by the CPU 602, with the assistance of support circuits 695, to cause the Autonomous Device Extraction Unit 600 to perform various methods in accordance with various embodiments of the invention.
• the distributed computing cluster 140 is any well-known network of computing elements, each containing memory and any number of CPUs, GPUs, FPGAs, ASICs, or similar. They are programmed to work together to analyze larger volumes of data than can be stored on any computer. It is used for two of the main methods of this invention. First, the distributed computing cluster is used to correlate RF waveform signals collected at various locations in the IC. Correlations are then returned to the auto-DNE and used to identify connected logic cells and construct the device netlist. Secondly, the distributed computing cluster is used, in a novel method, to execute electromagnetic field simulation code that is used to predict how the logic cells will appear when acquired by the pump-probe assembly.
• the database 130 is any relational database that contains both logic cell libraries (including functional Verilog, 2D layer geometry, and process parameters) and data acquired by the pump-probe assembly 1 18 and processed by the controller 1 16, which are then used at a later time by the auto-DNE 120 to carry out any number of the main methods described herein and construct a netlist.
• logic cell libraries including functional Verilog, 2D layer geometry, and process parameters
• FIG. 7 depicts a flow diagram of a method 700 of performing automated integrated circuit analysis in accordance with at least one embodiment of the invention.
• the method 700 (representing one embodiment of the function of hyper- dimensional logic cell recognition module 620) begins at step 702 and proceeds to step 704 wherein the integrated circuit under test is prepared for analysis.
• Step 704 includes packaging the chip so that the back surface of the chip (the substrate) faces upwards, followed by polishing the exposed back surface of the silicon substrate to an optical quality finish.
• step 705 the ADNE algorithm writes configuration files to the probe assembly computer.
• These configuration files include a list of landing locations and experimental parameters such as microscope objective, laser source, measurement type and the like, which allow the pump probe assembly to begin collecting data.
• the pump probe assembly 1 18 then positions the sample under the appropriate microscope objective in step 708 and then proceeds to collect several different images of the device including both pump probe images (e.g. charge flow images, time-resolved charge flow, etc.) lands an objective on a location of interest.
• the method 700 then proceeds to step 710, wherein the apparatus 100 collects several multi-modal images of the same region of the device using either one or both of the pump-probe lasers.
• Multi-modal images are collected according to standard imaging methods used in failure analysis (FA) such as 1064 nm and 1319 nm reflectivity, laser-induced voltage alteration (LIVA), optical beam induced current (OBIC), thermally induced voltage alteration (TIVA), pump-probe images such as charge flow, time resolved charge flow, AC or DC reflectivity scans, AC or DC absorption scans, single point scans while varying test vectors, scans at a plurality of laser wavelengths, stress mapping, or the like.
• the images are uploaded to the database 130, where they are registered or super-resolved in step 717.
• Logic cells are detected in step 720 from one or more of the images collected at the landing site (using a third novel hyper-dimensional recognition approach).
• labels for each detected logic cell are entered into the database 130. After detections have been carried out, a list of probe locations is written into the pump probe assembly configuration files before the microscope moves to the next landing using the known input and output node locations in the logic cells.
• a test vector set is provided to the IC, which initially is a repeating random set of test vectors produced at the input pins of the chip.
• activity is measured in step 755 using an activity measurement method to be described below. If activity is detected to exist at step 760, we integrate longer and collect a waveform at step 765. If activity is not detected, the method 700 proceeds to step 762, where the method 700 waits for activity.
• the correlation between the immediately measured waveform is used by the interconnect extractor 670 shown in Figure 6 in step 770 to identify connected nodes via correlation with other waveforms in the device.
• Any discovered connection is then uploaded to the database 130 to indicate, for the detected logic cell in question, what node is connected to a given input and output port on every active logic cell. This procedure repeats until all entries in the configuration files corresponding to probe and stage coordinates have completed, as determined by step 785. If additional landing locations are in the queue then the objective is relocated at the coordinate. At that point, the method 700 repeats using a new set of test vectors that are generated from the netlist information generated by the initial approximation of the netlist. When all the ports on active logic cells have been assigned to a netlist node, the process terminates at step 795.
• the super-resolution reconstruction module 630 may be used in the method 700, the automated netlist extraction algorithm.
• the method utilizes the ultrafast embodiment of the pump probe assembly 1 18 where the pump laser is a near infrared laser of wavelength ranging from 1 .0-1 .1 microns.
• the pump probe apparatus is configured to create several well-defined sinusoidal patterns of injected charge carriers which are imaged less than 1 pico-second later by the arrival of a probe pulse.
• the charge flow patterns are created by locking to the sum or difference frequency of the pump and probe modulation frequencies.
• Several images are created by rotation and changing the phase of the pump laser.
• the pattern of charge carriers creates an illumination grating, which down-shifts high spatial frequencies into the optical acceptance bandwidth of the system.
• the algorithm then un-shifts each image using an estimate of the superimposed charge carrier pattern.
• a large bandwidth frequency domain representation of the scene is constructed through an estimation of the overlap.
• a higher resolution images is created by Fourier transforming the large bandwidth frequency domain image into the spatial domain.
• Figure 8 depicts a flow diagram for a method 800 for detecting logic cells in accordance with exemplary embodiments of the present invention.
• the method 800 is an implementation of the method step 720 from method 700 shown in Figure 7.
• the method 800 begins at step 805 and then proceeds to step 820, where several raw images are selected of the same region of the device 103 acquired with the various sensors in the pump-probe apparatus 100 shown in Figure 1 .
• step 825 the multiple images are aligned and rescaled so that each array coordinate in each image corresponds to the same location on the actual device.
• a 3D array is constructed in step 830, in which two of the three coordinates correspond to the x and y coordinates of the plan view of the chip on device 102 and the third is an index corresponding to each of the raw images in the database 130.
• 1 D descriptors For each object in the database 130, 1 D descriptors (see, for example, BRIEF, SWIFT, HOG) exist for each imaging modality.
• the 1 D descriptors are selected from the query object, which correspond to the imaging modalities selected from the raw images of the landing location stored in the database 130.
• the 3D array is iteratively scanned corresponding to the landing location imagery by selecting a sequence of regions of interest of the landing location with the same size as the query object, including all vertical and horizontal reflections of the query object.
• the method then proceeds to step 855, where a descriptor is constructed for each region of interest and image modality and compared to the query descriptor for each corresponding modality using any variety of methods, e.g. summing the NOR value for each bit. If the 1 D descriptor and the selected descriptor do not match at step 857, then the method proceeds to step 850. If the descriptors match at step 857, the method proceeds to step 860.
• step 860 logic cell metadata, for example, name, bounding box, or the like, is retrieved from database 130.
• step 865 the image patches are masked and the detections are uploaded to the database at step 870.
• one of the tables e.g. the detections table
• a library ID entry which uniquely relates a library element to a set of pixels in each raw data image. This process repeats for all desired query objects until a set of masks for the landing region is created.
• overlapping masks are eliminated using a voting scheme in step 880.
• the process ends at step 885 after all library objects have been identified in the landing location, and for every (x, y) coordinate where a library object has been identified, there exists an entry into a relational schema that can be queried to determine what object exists within that raw imagery of the landing location of interest.
• Figure 9 depicts a method 900 for extracting interconnects in accordance with exemplary embodiments of the present invention.
• the method 900 is an exemplary implementation of the steps performed by the super-resolution reconstruction module 670 shown in Figure 6.
• Method 900 is used to identify electrical connections between logic cells with the assistance of a distributed computing cluster that may be composed of a multitude of GPUs (graphical processing units), CPUs (central processing units), FPGAs (field programmable gate arrays), or some combination thereof.
• the waveform structure is essentially unchanged within each node.
• the method 900 begins at step 905 and proceeds to step 915, where a landing position is established, i.e. IC stage coordinate.
• the method 900 measures several clean waveforms from the device under test 102, created by averaging several noisy waveforms, corresponding to one or more test vector sets.
• the method transfers those waveforms to the distributed computing cluster in step 925.
• the distributed computing cluster computes a feature vector from the content of the waveform, and then in step 930 the correlation score is computed between each waveform and those unique waveforms with similar features stored in the database. If the correlation is above a given threshold, the new waveform is said to connect to the stored node ID and is assigned to that node ID, and the database waveform for the unique node is updated to reflect the newly joined waveform.
• the waveform is used to create a new node with new unique node ID.
• the node ID for each waveform and location in the field of view is associated with each active region in the landing location and uploaded to the database in step 945. The algorithm concludes in step 955.
• FIG. 10 depicts a flow diagram for a method 1000 for detecting activity in accordance with exemplary embodiments of the present invention.
• the method 1000 describes an exemplary embodiment of step 755 in method 700.
• the method 1000 is used to identify the presence of electronic waveforms within an IC without the need for longer averaging to measure the waveform.
• the algorithm begins at step 1005 while the device 102 is operated with test vectors.
• Several Laser Voltage Probed (LVP) signals i.e. noisy waveforms, are acquired using a standard AC coupled photodetector and RF amplifier assembly in step 1020.
• the activity detector algorithm computes an activity score A in step 1025.
• A is computed using the following equation:
• the score is computed by summing the dot product (correlation) of each individual with the waveform with the average and dividing by the sum of the difference of the self-correlation and the correlation with the mean for all waveforms. In this way, we can determine with only a few measurements whether there exists a waveform at all to be measured.
• the method 1000 then returns the activity score in step 1035 and ends at 1055.
• FIG. 1 1 depicts a flow diagram of a method 1 100 in accordance with exemplary embodiments of the present invention.
• the Rapid Electromagnetic Simulator 690 implements the method 1 100.
• the method 1 100 takes as input the GDS layout information contained in the database 130 and simulates how such a layout will appear in the microscope.
• the method has two main components: first a gallery of simulated features is created using only unique voxels contained in the GDS library. Gallery creation may happen while GDS files are simulated.
• the method begins at step 1 105 and proceeds to step 1 120, wherein the algorithm reads one or more GDS files from the database 130. The coordinate scaling and units of the GDS information are also read.
• Microscope configuration information is used to compute the size of the voxel, or confocal volume of the laser scanning microscope, and voxel spacing.
• GDS file is then partitioned into a set of non-overlapping voxels in step 1 135.
• a descriptor which may be a binary, 1 D array, is computed for each individual voxel.
• the voxel descriptors are then clustered and representatives from each unique voxel are held in memory.
• Unique voxel descriptors are compared to those found in the database in step 1 137 using any manner of feature vector comparison such as dot products, or NOR operations.
• the voxel is transferred into a 3D array of points containing optical dielectric parameters and then simulated using a finite difference time-domain (FDTD) or similar Maxwell's equation solver in step 1 155, where the initial beam is assumed to be a focused beam with parameters consistent with the voxel size.
• FDTD finite difference time-domain
• Maxwell's equation solver Maxwell's equation solver
• the method 1 100 simply downloads the simulation result in step 1 140 from the database and writes the result to that portion of the image simulation in step 1 160. This process may be repeated for every cell in the library and completes at step 1 170.
• the advantage of this procedure for simulating a system is that speed is increased due to the high degree of symmetry contained in GDS files, while accuracy is maintained with the accurate Maxwell's solvers, which are typically too slow to simulate large structures on their own. In this way, many large structures can be simulated quickly and accurately.

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• 2013
  • 2013-10-29 US US14/066,111 patent/US10180402B2/en not_active Expired - Fee Related
  • 2013-11-21 WO PCT/US2013/071231 patent/WO2014105304A2/en not_active Ceased
  • 2013-11-21 EP EP13868949.2A patent/EP2932283A4/en not_active Withdrawn
  • 2013-11-21 JP JP2015547965A patent/JP2016506623A/ja active Pending
  • 2013-11-21 SG SG11201504585QA patent/SG11201504585QA/en unknown

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