WO2014097580A1 - 電子基板及びそのコネクタ接続構造 - Google Patents
電子基板及びそのコネクタ接続構造 Download PDFInfo
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- WO2014097580A1 WO2014097580A1 PCT/JP2013/007286 JP2013007286W WO2014097580A1 WO 2014097580 A1 WO2014097580 A1 WO 2014097580A1 JP 2013007286 W JP2013007286 W JP 2013007286W WO 2014097580 A1 WO2014097580 A1 WO 2014097580A1
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- connection terminals
- connection terminal
- base material
- pair
- main surfaces
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/71—Coupling devices for rigid printing circuits or like structures
- H01R12/72—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
- H01R12/721—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures cooperating directly with the edge of the rigid printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
- H01R13/6461—Means for preventing cross-talk
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
- H01R13/6473—Impedance matching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/71—Coupling devices for rigid printing circuits or like structures
- H01R12/72—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
- H01R12/73—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
Definitions
- the present invention relates to an electronic board or the like, for example, an electronic board or the like having a plurality of connection terminals arranged at the end of a base material.
- An electronic substrate used in such a technique has a configuration as shown in FIGS. 13 and 14, for example.
- wirings 120 serving as signal lines are arranged on the flat substrate 110.
- the wiring 120 is connected to the connection terminal 130 on the end side of the substrate 110.
- the transmission signal is transmitted from the wiring 120 to the connection terminal 130.
- a signal in the reverse direction is transmitted from the connection terminal 130 to the wiring 120.
- connection terminal 130 located at the end of the electronic substrate 100a has a parasitic capacitance, and impedance mismatch occurs due to capacitive coupling, which causes a problem of crosstalk.
- the influence of crosstalk increases as the period of the digital signal decreases, and further increases as the parasitic capacitance of the connection terminal increases.
- connection terminal by configuring the connection terminal so that the wiring-side portion and the stub portion positioned in the opposite direction are electrically discontinuous, an extra portion of the connection terminal A technique for improving impedance mismatch by suppressing the reflection noise from the stub and reducing the parasitic capacitance between the stub and the GND layer is described.
- Patent Document 2 describes a technique for reducing crosstalk between terminals, although it is not a technique related to impedance mismatching due to capacitive coupling. That is, in the technique described in Patent Document 2, the connection terminals are formed in parallel in the kerf with the substrate end opened. And the dielectric material which is a base material is interposed as a convex step part between the connection terminals. Further, a connection terminal having a GND potential is provided on the stepped portion, and a through hole is provided immediately below the connection terminal having the GND potential. Thus, Patent Document 2 describes a technique for reducing the influence of an electromagnetic field between the connection terminals by a shielding effect and suppressing crosstalk.
- the substrate described in Patent Document 2 cannot reduce the parasitic capacitance between the signal terminal and the signal terminal or between the signal terminal and the connection terminal of the GND potential.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to provide an electronic substrate that can improve crosstalk by reducing parasitic capacitance between connection terminals.
- an electronic substrate includes a flat base material having a pair of main surfaces facing each other, an end side of the base material, and the pair of main surfaces of the base material. Between a plurality of connection terminals formed on at least one surface, a plurality of wirings connected to the plurality of connection terminals, and a connection terminal adjacent to each other among the plurality of connection terminals, A plurality of openings are provided along a direction in which the connection terminal extends over a region in which the connection terminal extends.
- the connector connection structure for an electronic board is a connector connection structure for an electronic board having a flat plate electronic board and a connector for holding an end of the electronic board, and a pair of main surfaces are mutually connected.
- a plurality of connection terminals formed on a flat substrate facing each other, arranged on at least one surface of the pair of main surfaces of the substrate, on the end side of the substrate;
- a plurality of wirings connected to the connection terminal and a connection terminal adjacent to each other among the plurality of connection terminals, and extending in a direction in which the connection terminal extends over a region where the connection terminal extends.
- a plurality of openings provided, and the connector includes connector-side connection terminals that contact the plurality of connection terminals when the electronic board is held.
- the parasitic capacitance of the connection terminal can be reduced, and as a result, crosstalk can be improved.
- FIG. 6B is a cross-sectional view taken along the line AA in FIG. 6A.
- FIG. 7B is a cross-sectional view taken along the line BB of FIG. 7A. It is a figure which shows the structure of the electronic substrate concerning the 4th Embodiment of this invention. It is a figure which shows the structure of the electronic substrate of related technology. It is a figure which shows the result of having analyzed the electric field distribution in a comparative example. It is a figure which shows the result of having analyzed the electric field distribution in Example 1. FIG. It is a figure which shows the result of having analyzed the scattering parameter of the crosstalk in Example 1 and 2 and a comparative example. It is a figure which shows the structure of the electronic substrate of related technology. It is a figure which shows the structure of the electronic substrate of related technology.
- First Embodiment> 1 and 2 show the configuration of the electronic substrate 100 according to the first embodiment of the present invention.
- 3 and 4 are diagrams showing a connector connection structure between the electronic substrate 100 and the connectors 200A and 200B according to the first embodiment of the present invention.
- the configuration of the electronic substrate 100 will be described with reference to FIG. 1, and then the configuration of the connector connection structure of the electronic substrate 100 will be described with reference to FIGS. 3 and 4.
- FIG. 1 is an enlarged view showing an end portion side where the connection terminal 130 of the electronic substrate 100 of FIG. 2 is provided.
- the electronic substrate 100 of this embodiment includes a flat substrate 110, wiring 120, connection terminals 130, and a plurality of openings 140 ⁇ / b> A.
- the pair of main surfaces 110a and 110b face each other.
- the base material 110 commonly used materials such as glass epoxy, polyimide, Teflon (registered trademark), and BT (Bismaleimide-Triazine) resin can be used.
- the base material 110 may be formed of a plurality of layers. For example, a GND layer or a power supply layer may be formed as an inner layer.
- connection terminals 130 are arranged on the end portion side of the base material 110 and arranged on at least one of the pair of main surfaces 110 a and 110 b of the base material 110. 1 and 2 exemplify an example in which the connection terminal 130 is formed on the main surface 110a.
- the connection terminal 130 for example, a signal connection terminal or a connection terminal having a GND potential can be used. Further, the connection terminal 130 can be formed by, for example, electrolytic gold plating or electroless gold plating.
- the wiring 120 is electrically connected to the connection terminal 130.
- a generally used conductive material such as copper can be used.
- the wiring 120 includes, for example, a signal wiring and a GND wiring.
- the plurality of openings 140 ⁇ / b> A are located between the connection terminals 130 adjacent to each other along a direction in which the connection terminals 130 extend over a region where the connection terminals 130 extend. Is formed.
- the plurality of openings 140A are through holes penetrating between the main surfaces 110a and 110b.
- the present invention is not limited to this, and the plurality of openings 140A may be grooves that do not penetrate between the main surfaces 110a and 110b. Further, it is only necessary that a plurality of openings 140A are formed.
- the plurality of openings 140 ⁇ / b> A may be formed over a region between the adjacent connection terminals 130 where the connection terminals 130 extend.
- the size, number, and shape of the plurality of openings 140A are preferably determined as appropriate in consideration of the balance between the region between the adjacent connection terminals 130 where the connection terminals 130 extend and the parasitic capacitance reduction effect. Examples of the method of forming the plurality of openings 140A include etching, drilling with a drill, and punching. ⁇ Description of connector connection structure> Next, the configuration of the connector connection structure of the electronic substrate 100 will be described with reference to FIGS. 3 and 4.
- the connector connection structure of the present embodiment includes an electronic substrate 100 and connectors 200A and 200B. Connectors 200A and 200B are mounted on circuit board 300. The configuration of the electronic substrate 100 is as described with reference to FIGS.
- FIG. 3 illustrates an example in which the connector 200 ⁇ / b> A holds the electronic board 100 so that the electronic board 100 is horizontal with respect to the circuit board 300.
- FIG. 4 illustrates an example in which the connector 200B holds the electronic board 100 so that the electronic board 100 is perpendicular to the circuit board 300.
- the connectors 200 ⁇ / b> A and 200 ⁇ / b> B are configured to include a housing 210 and connector-side connection terminals 220.
- the housing 210 is formed with an insertion port 211 into which an end of the electronic board having the connection terminal 130 of the electronic board 100 is inserted and removed.
- the insertion slot 211 is formed in accordance with the width in the longitudinal direction of the end portion of the electronic substrate 100.
- a plurality of connector-side connection terminals 220 are provided in the insertion port 211 of the housing 210 at intervals in the longitudinal direction of the insertion port 211. Further, the connector side connection terminal 220 is provided so as to come into contact with the plurality of connection terminals 130 of the electronic substrate 100 and hold the electronic substrate 100 with the electronic substrate 100 interposed therebetween when the electronic substrate 100 is inserted into the insertion slot 211. Further, the connector side connection terminal 220 penetrates the bottom portion of the housing 210 on the circuit board 300 side and is electrically connected to the circuit board 300 through the connector connection terminal 310. The connector side connection terminal 220 is connected to the connector connection terminal 310 of the circuit board 300 by, for example, soldering.
- the circuit board 300 is a flat board and has connector connection terminals 310.
- the circuit board 300 is electrically connected to the electronic board 100 via the connectors 200A and 200B.
- a printed board can be used as the circuit board 300.
- the connector connection terminal 310 is formed on the circuit board 300 and electrically connects the connector side connection terminal 220 and the circuit board 300.
- the electronic board 100 is inserted into the insertion slot 211 of the connector 200 mounted on the circuit board 300.
- the connector side connection terminal 220 contacts the plurality of connection terminals 130 of the electronic substrate 100 and holds the electronic substrate 100 with the electronic substrate 100 interposed therebetween.
- the electronic board 100 is electrically connected to the circuit board 300 via the connector 200A and the connector 200B.
- a transmission signal of the electronic board 100 passes through the connection terminal 130, the connector side connection terminal 220, and the connector connection terminal 310 and is transmitted to the circuit board 300.
- the transmission signal of the circuit board 300 is transmitted to the electronic board 100 through the connector connection terminal 310, the connector side connection terminal 220, and the connection terminal 130.
- the electronic substrate 100 includes the flat substrate 110, the wiring 120, the connection terminal 130, and the plurality of openings 140A.
- the base 110 on the flat plate has a pair of main surfaces 110a and 110b facing each other.
- the connection terminal 130 is formed on the end portion side of the base material 110 and arranged on at least one of the pair of main surfaces 110 a and 110 b of the base material 110.
- the wiring 120 is electrically connected to the connection terminal 130.
- the plurality of openings 140A are formed along the direction in which the connection terminals 130 extend between the connection terminals 130 adjacent to each other over a region where the connection terminals 130 extend.
- the plurality of openings 140 ⁇ / b> A are between the connection terminals 130 adjacent to each other and extend over the region where the connection terminals 130 extend. Is formed along the extending direction.
- L is the inductance of the connection terminal 130
- C is the parasitic capacitance value between the connection terminal 130 and the other connection terminal 130 adjacent thereto.
- the parasitic capacitance value C increases, the characteristic impedance Z0 of the connection terminal 130 decreases, causing crosstalk and degrading transmission characteristics.
- a plurality of openings 140A are formed in a region between the connection terminals 130 adjacent to each other and where the connection terminals 130 extend. For this reason, the relative dielectric constant of the region between the adjacent connection terminals 130 in the substrate 110 can be reduced in a pseudo manner.
- the parasitic capacitance value C between adjacent connection terminals 130 is proportional to the relative dielectric constant between the connection terminals 130. Therefore, the parasitic capacitance value C can be reduced by reducing the relative dielectric constant of the region between the connection terminals 130.
- connection terminals 130 it is possible to suppress a decrease in characteristic impedance by reducing the parasitic capacitance between adjacent connection terminals 130, and as a result, it is possible to improve crosstalk at the connection terminals 130.
- the plurality of openings 140A may be grooves that do not penetrate between the pair of main surfaces 110a and 110b of the base 110. In that case, since the plurality of openings 140A do not penetrate between the pair of main surfaces 110a and 110b of the base 110, the strength of the base 110 is not lowered more than necessary. Further, even if the plurality of openings 140A are grooves that do not penetrate between the pair of main surfaces 110a and 110b of the substrate 110, the relative dielectric constant between the adjacent connection terminals 130 can be reduced, and the adjacent connection terminals 130 can be reduced. As a result, the same effect as the electronic substrate 100 described above can be obtained.
- FIG. 5 is a diagram showing the electronic substrate 100A.
- constituent elements equivalent to those shown in FIGS. 1 to 4 are given the same reference numerals as those shown in FIGS.
- the electronic substrate 100 ⁇ / b> A includes a flat substrate 110, wiring 120, connection terminals 130, and a long rectangular opening 140 ⁇ / b> B.
- FIG. 1 and FIG. 5 in FIG. 1, a plurality of openings 140 ⁇ / b> A are provided in a region between the connection terminals 130 adjacent to each other and extending the connection terminals 130.
- a long rectangular opening 140 ⁇ / b> B is provided in a region between the connection terminals 130 adjacent to each other and extending the connection terminals 130. In this respect, they are different from each other.
- the description of the same configuration as that shown in FIGS. 1 and 2 is omitted.
- the elongated rectangular opening 140 ⁇ / b> B extends between the connection terminals 130 adjacent to each other among the plurality of connection terminals 130 and extends in the region where the connection terminals 130 extend. It is provided along the existing direction.
- the elongated rectangular opening 140B is a through hole formed through the pair of main surfaces 110a and 110b of the base 110 is shown.
- the elongated rectangular opening 140B may be a groove that does not penetrate between the pair of main surfaces 110a and 110b of the base 110.
- the long rectangular opening 140B is a groove that does not penetrate between the pair of main surfaces 110a and 110b of the base 110, the long rectangular opening 140B gradually opens toward the inner layer of the base 110, for example.
- Examples of the method for forming the elongated rectangular opening 140B include etching and drilling using a drill. Note that the method of forming the long rectangular opening 140B is not limited to etching and drilling by a drill, and may be any method that provides an opening in a long rectangular shape.
- the opening 140B can be formed using, for example, a V-shaped groove processing router.
- the electronic substrate 100A according to the second embodiment of the present invention has the long rectangular opening 140B.
- the long rectangular opening 140 ⁇ / b> B is formed between the connection terminals 130 adjacent to each other and extending over the region where the connection terminals 130 extend.
- the relative dielectric constant in the region between the terminals 130 can be reduced in a pseudo manner. Therefore, by reducing the relative dielectric constant of the region between the adjacent connection terminals 130, the parasitic capacitance between the adjacent connection terminals 130 is also reduced.
- FIG. 6A is a plan view of the electronic substrate 100B.
- 6B is a cross-sectional view taken along the line AA in FIG. 6A.
- FIG. 6A and FIG. 6B constituent elements equivalent to those shown in FIGS. 1 to 5 are given the same reference numerals as those shown in FIGS.
- the electronic substrate 100B includes a flat substrate 110, a wiring 120, a first connection terminal 130A, a second connection terminal 130B, a plurality of openings 140A, It is comprised.
- FIG. 1 and FIG. 2 are compared with FIG. 6A and FIG. 6B. 1 and 2, the connection terminals 130 are arranged on the end side of the base material 110 and arranged on at least one of the pair of main surfaces 110 a and 110 b of the base material 110.
- the first connection terminal 130A and the second connection terminal 130B are arranged on both surfaces of the pair of main surfaces 110a and 110b of the substrate 110 so as to face each other. Formed. In this respect, they are different from each other.
- description of components equivalent to those shown in FIGS. 1 to 5 is omitted.
- the first connection terminal 130A and the second connection terminal 130B are on the end portion side of the base material 110, and are both of the pair of main surfaces 110a and 110b of the base material 110. It is formed in an array on the surface.
- the first connection terminal 130 ⁇ / b> A is formed on one of the pair of main surfaces of the base material 110.
- 6A and 6B illustrate an example in which the first connection terminal 130A is formed on the main surface 110a.
- the second connection terminal 130 ⁇ / b> B is formed on the other of the pair of main surfaces of the base material 110.
- 6A and 6B illustrate an example in which the second connection terminal 130B is formed on the main surface 110b.
- the first connection terminal 130A and the second connection terminal 130B are formed so as to face each other.
- the first connection terminal 130A and the second connection terminal 130B include, for example, a signal connection terminal and a connection terminal having a GND potential.
- the first connection terminal 130A and the second connection terminal 130B can be formed by, for example, electrolytic gold plating or electroless gold plating.
- the plurality of openings 140A illustrate examples of grooves that do not penetrate between the pair of main surfaces 110a and 110b of the base 110.
- the plurality of openings 140 ⁇ / b> A may be through holes penetrating between the pair of main surfaces 110 a and 110 b of the substrate 110.
- connection terminals 220 of the connectors 200A and 200B described above are provided corresponding to the connection terminals 130A and 130B formed on both surfaces of the pair of main surfaces 110a and 110b of the base 110.
- the first connection terminal 130A and the second connection terminal 130B are on both surfaces of the pair of main surfaces 110a and 110b of the base 110. Are arranged so as to face each other.
- the electronic substrate 100 ⁇ / b> B can mount more electronic components.
- the electronic substrate 100B is provided with a plurality of openings 140A, the relative dielectric constant of the region between the first connection terminal 130A and the other adjacent first connection terminal 130A is simulated. Can be reduced.
- the parasitic capacitance between the first connection terminal 130A and the other adjacent first connection terminal 130A can be reduced.
- the relative dielectric constant of the region between the first connection terminal 130A and the second connection terminal 130B facing the first connection terminal 130A can be reduced in a pseudo manner.
- the parasitic capacitance generated between the first connection terminal 130A and the second connection terminal 130B facing the first connection terminal 130A can be reduced.
- a long rectangular opening 140B may be provided instead of the plurality of openings 140A.
- the first connection terminal The parasitic capacitance between 130A and the other adjacent first connection terminal 130A can be reduced.
- the elongated rectangular opening 140B is provided, so that the region between the first connection terminal 130A and the second connection terminal 130B that faces the first connection terminal 130A is provided. The relative dielectric constant can be reduced in a pseudo manner.
- FIGS. 7A and 7B are diagrams showing the configuration of the electronic substrate 100C in the fourth embodiment of the present invention.
- FIG. 7A is a plan view of an electronic substrate 100C having a plurality of openings 140A.
- FIG. 7B is a cross-sectional view taken along the line BB of FIG. 7A.
- FIG. 8 is a diagram illustrating a configuration of an electronic substrate 100D having a long rectangular opening 140B instead of the plurality of openings 140A of the electronic substrate 100C of FIGS. 7A and 7B.
- FIG. 7A, FIG. 7B, and FIG. 8 constituent elements that are equivalent to the constituent elements shown in FIGS. 1 to 6 are given the same reference numerals as those shown in FIGS.
- the electronic substrate 100C includes a base material 110, a wiring 120, a first connection terminal 130A, a second connection terminal 130B, and a plurality of openings 140A on a flat plate. Has been.
- FIG. 6A and FIG. 6B are compared with FIG. 7A and FIG. 7B.
- the first connection terminal 130A and the second connection terminal 130B are configured to be arranged so as to face each other.
- the first connection terminal 130A and the second connection terminal 130B are formed so as not to face each other. In this respect, they are different from each other.
- description of components equivalent to those shown in FIGS. 1 to 6 is omitted.
- the first connection terminal 130A and the second connection terminal 130B are formed so as not to face each other.
- 7A and 7B exemplify an example in which the first connection terminal 130A and the second connection terminal 130B are formed so as not to face each other by being shifted from each other by 1 ⁇ 2 pitch.
- the plurality of openings 140A are formed so that the first connection terminal 130A and the second connection terminal 130B do not face each other, so that they do not penetrate between the pair of main surfaces 110a and 110b of the base 110. It is configured.
- the first connection terminal 130A and the second connection terminal 130B are arranged so as not to face each other. Formed. Thereby, compared with other embodiment of this invention, more opening parts 140 can be provided. As a result, the dielectric constant of the region between the first connection terminal 130A and the other adjacent first connection terminal 130A and the region between the first connection terminal 130A and the second connection terminal 130B facing each other. The rate can be reduced more artificially. As a result, the parasitic capacitance generated in both regions can be reduced.
- Example 1 An example of the electronic substrate 100D in the fourth embodiment of the present invention will be described as Example 1.
- Example 2 An example of the electronic substrate 100C according to the fourth embodiment of the present invention will be described as Example 2.
- Example 3 An example of the electronic substrate 100b having the configuration shown in FIG. 9 will be described as a comparative example.
- FIG. 9 is a diagram showing a configuration of the electronic substrate 100b related to the present invention.
- FIG. 10 shows the result of analyzing the electric field distribution caused by the parasitic capacitance generated in the connection terminals 130A and 130B with the simulator for the electronic substrate 100b of the comparative example.
- FIG. 11 shows a result of analyzing the electric field distribution caused by the parasitic capacitance generated in the first and second connection terminals 130A and 130B by the simulator in the first embodiment.
- FIG. 12 shows the results of analyzing the crosstalk scattering parameters for Example 1, Example 2, and Comparative Example.
- Example 1 corresponds to electronic substrate 100D (see FIG. 8) according to the fourth embodiment of the present invention.
- substrate 110 a glass epoxy material (relative dielectric constant 3.8) having a thickness of 1 mm between the pair of main surfaces 110a and 110b was used.
- first and second connection terminals 130A and 130B a gold-plated copper alloy having a length in the short direction of 0.6 mm and a thickness of 43 ⁇ m was used. The distance between the connection terminal and the other connection terminal adjacent to the connection terminal was set to 0.2 mm.
- the long rectangular opening 140B was provided to have a length of 2.25 mm, a width of 0.15 mm, and a depth of 0.58 mm.
- Example 2 corresponds to electronic substrate 100C (see FIGS. 7A and 7B) according to the fourth embodiment of the present invention.
- the second embodiment is different from the first embodiment in that a plurality of openings 140A are provided instead of the elongated rectangular openings 140B of the first embodiment.
- the plurality of openings 140A were provided to have a diameter of 0.15 mm and a depth of 0.58 mm. Other conditions are the same as in the first embodiment.
- the comparative example is an electronic substrate 100b for comparison with Examples 1 and 2 in this example, and has a configuration as shown in FIG.
- the comparative example relates to the electronic substrate 100a (see FIGS. 13 and 14) of the related art of the present invention, and the connection terminals 130 and the wiring 120 formed on the pair of main surfaces of the electronic substrate 100a are opposed to each other.
- One main surface is formed in the same manner (see FIGS. 9 and 10).
- the connection terminals 130A and 130B of the electronic substrate 100b as a comparative example are formed so as not to face each other by being shifted by 1/2 pitch.
- the comparative example differs from the first embodiment in that the long rectangular opening 140B of the first embodiment is not provided. Other conditions are the same as in the first embodiment.
- [Evaluation of electric field distribution] Next, using FIG. 10 and FIG. 11, the spread of the electric field distribution caused by the parasitic capacitance in Example 1 and the comparative example is compared. The electric field distribution resulting from the parasitic capacitance of Example 1 shown in FIG. 11 is smaller than the electric field distribution of the comparative example shown in FIG. [Evaluation of scattering parameters of crosstalk] In addition, the results of the crosstalk scattering parameters of Examples 1 and 2 and the comparative example are compared using FIG. As shown in FIG.
- Example 1 and 2 which has an opening part has improved crosstalk.
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Abstract
Description
図1及び図2は、本発明の第1の実施の形態における電子基板100の構成を示している。図3及び図4は、本発明の第1の実施の形態における電子基板100とコネクタ200A、200Bとのコネクタ接続構造を示す図である。以下の説明では、まず、図1を用いて電子基板100の構成を説明し、その後に図3及び図4を用いて電子基板100のコネクタ接続構造の構成を説明する。
また、複数の開口部140Aは、複数形成されていれば良い。しかしながら、複数の開口部140Aを数多く形成することで、基材110のうちで隣接する接続端子130間の領域の比誘電率を疑似的に小さくすることができ、接続端子130における寄生容量をより低減することができる。
また、複数の開口部140Aは、隣接する接続端子130の間であって接続端子130が延在する領域に亘り形成されていれば良い。複数の開口部140Aの大きさや数や形状は、隣接する接続端子130間であって接続端子130が延在する領域と寄生容量の低減効果とのバランスを考慮して適宜決定することが好ましい。複数の開口部140Aを形成する方法には、例えばエッチング、ドリルによる掘削、パンチング加工がある。
<コネクタ接続構造の説明>
次に、図3及び図4を用いて、電子基板100のコネクタ接続構造の構成を説明する。
また、コネクタ側接続端子220は、ハウジング210の回路基板300側である底部を貫通して、コネクタ接続用端子310を通じて回路基板300と電気的に接続されている。コネクタ側接続端子220は例えば半田付けによって回路基板300のコネクタ接続用端子310と接続される。
電子基板100の伝送信号は接続端子130、コネクタ側接続端子220、コネクタ接続用端子310を通過し、回路基板300へと伝送される。また、回路基板300の伝送信号は、コネクタ接続用端子310、コネクタ側接続端子220、接続端子130を通じて電子基板100へと伝送される。
また、複数の開口部140Aは、基材110の一対の主面110a、110b間を貫通しない溝であっても、隣接する接続端子130間の比誘電率を小さくでき、隣接する接続端子130間の寄生容量を低減できるので、上述した電子基板100と同様の効果を奏する。
<第2の実施の形態>
図5を用いて、本発明の第2の実施の形態における電子基板100Aについて説明する。図5は、電子基板100Aを示す図である。なお、図5では、図1~4で示した各構成要素と同等の構成要素には、図1~4に示した符号と同等の符号を付している。
なお、ここでは、長矩形状の開口部140Bは、基材110の一対の主面110a、110b間を貫通して形成される貫通穴である例を示している。しかしながら、長矩形状の開口部140Bは、基材110の一対の主面110a、110b間を貫通しない溝であってもよい。
また、長矩形状の開口部140Bが、基材110の一対の主面110a、110b間を貫通しない溝の場合、長矩形状の開口部140Bは、例えば基材110の内層に向かって徐々に開口の幅を狭くしたV字状に形成される溝であってもよい。
長矩形状の開口部140Bを形成する方法には、例えばエッチング、ドリルによる掘削がある。なお、長矩形状の開口部140Bを形成する方法は、エッチング、ドリルによる掘削に限らず、長矩形状に開口部を設けられる方法であればよい。なお、長矩形の開口部140BがV字状の溝の場合、開口部140Bは例えばV字溝加工用ルータを用いて形成することができる。
そのため、隣接する接続端子130間の領域の比誘電率を小さくすることで、隣接する接続端子130間の寄生容量も小さくなる。従って、本実施形態によれば、隣接する接続端子130間の寄生容量を低減することで特性インピーダンス低下を抑制でき、その結果、接続端子130におけるクロストークを改善することができる。
<第3の実施の形態>
図6A及び図6Bを用いて、本発明の第3の実施の形態における電子基板100Bについて説明する。
これに対して、図6A及び図6Bでは、第1の接続端子130A及び第2の接続端子130Bは、基材110の一対の主面110a、110bの双方の面上に互いに向かい合うように配列して形成される。この点で両者は互いに相違する。以下の説明では、図1~図5で示した構成と同等の構成については、説明を省略する。
また、電子基板100Bには、複数の開口部140Aが設けられているため、第1の接続端子130Aと隣接するもう一方の第1の接続端子130Aとの間の領域の比誘電率を擬似的に低減することができる。その結果、第1の接続端子130Aと隣接するもう一方の第1の接続端子130Aとの間の寄生容量を小さくすることができる。
さらに、複数の開口部140Aが設けられていることによって、第1の接続端子130Aと対向する第2の接続端子130Bとの間の領域の比誘電率を擬似的に低減することができる。その結果、第1の接続端子130Aと対向する第2の接続端子130Bとの間に生じる寄生容量をも小さくすることができる。
さらに、上述した複数の開口部140Aの場合と同様に、長矩形状の開口部140Bが設けられていることによって、第1の接続端子130Aと対向する第2の接続端子130Bとの間の領域の比誘電率を擬似的に低減することができる。その結果、第1の接続端子130Aと対向する第2の接続端子130Bとの間に生じる寄生容量をも小さくすることができる。
<第4の実施の形態>
図7A、図7B及び図8を用いて、本発明の第4の実施の形態における電子基板100C、100Dについて説明する。
その結果、第1の接続端子130Aと隣接するもう一方の第1の接続端子130Aとの間の領域及び第1の接続端子130Aと対向する第2の接続端子130Bとの間の領域の比誘電率を擬似的により低減することができる。その結果、両領域に生じる寄生容量を小さくすることができる。
[実施例]
[実施例1]
実施例1は、上述の通り、本発明の第4の実施の形態における電子基板100D(図8参照)に対応している。基材110には、一対の主面110a、110b間の厚さが1mmのガラスエポキシ材(比誘電率3.8)を用いた。第1及び第2の接続端子130A、130Bには、短手方向の長さが0.6mm、厚み43μmの金メッキ銅合金を用いた。接続端子と隣接するもう一方の接続端子との距離は0.2mmとなるようにした。長矩形状の開口部140Bは、長手方向に2.25mm、短手方向に0.15mm、深さ0.58mmとなるように設けた。
[実施例2]
実施例2は、上述の通り、本発明の第4の実施の形態における電子基板100C(図7A、図7B参照)に対応している。実施例1と対比すると、実施例2は、実施例1の長矩形状の開口部140Bに代えて、複数の開口部140Aが設けられている点で実施例1と相違する。複数の開口部140Aは、直径0.15mmで深さが0.58mmになるように設けた。その他の条件については、実施例1と同様である。
[比較例]
比較例は、本実施例において実施例1及び2と対比するための電子基板100bであり、図9で示すような構成を有している。比較例は、本発明の関連技術の電子基板100a(図13、14参照)に関連しており、電子基板100aの一対の主面に形成されている接続端子130及び配線120が、対向するもう一方の主面にも同様に形成されている(図9、図10参照)。
また、図9及び図10に示すように、比較例である電子基板100bの接続端子130A、130Bは、互いに1/2ピッチずれることで、互いに向かい合わないように配列して形成されている。実施例1と対比すると、比較例は、実施例1が有する長矩形状の開口部140Bが設けられていない点で実施例1と相違する。その他の条件については、実施例1と同様である。
[電界分布の評価]
次に、図10と図11を用いて、実施例1と比較例の寄生容量に起因する電界分布の広がりを対比する。図11に示す実施例1の寄生容量に起因する電界分布は、図10に示す比較例の電界分布に比べて、電界分布の広がりが小さい。
[クロストークの散乱パラメータの評価]
また、図12を用いて、実施例1、2と比較例とのクロストークの散乱パラメータの結果を対比する。図12に示すように、比較例の場合、クロストークのピークは15.5GHz付近で-1.3dBである。一方、実施例1及び実施例2の場合、クロストークのピークは、実施例1において16.5GHz付近で-0.7dB、実施例2において16GHz付近で-1.0dBである。よって、開口部を有しない比較例と比べて、開口部を有する実施例1及び2はクロストークが改善されている。
[まとめ]
以上の測定結果によれば、開口部が設けられていることで、電子基板における接続端子間の寄生容量を低減し、結果、クロストークを改善することができた。
なお、この出願は、2012年12月18日に出願された日本出願特願2012-275669を基礎とする優先権を主張し、その開示の全てをここに取り込む。
100a 電子基板
100b 電子基板
100A 電子基板
100B 電子基板
100C 電子基板
100D 電子基板
110 基材
110a 一対の主面
110b 一対の主面
120 配線
130 接続端子
130A 第1の接続端子
130B 第2の接続端子
140A 複数の開口部
140B 長矩形状の開口部
200A コネクタ
200B コネクタ
210 ハウジング
220 コネクタ側接続端子
300 回路基板
310 コネクタ接続用端子
Claims (7)
- 一対の主面が互いに向かい合う平板状の基材と、
前記基材の端部側であって、前記基材の前記一対の主面の少なくとも一方の面上に配列して形成された複数の接続端子と、
前記複数の接続端子に接続された複数の配線と、
前記複数の接続端子のうちで互いに隣接する接続端子の間であって前記接続端子が延在する領域に亘り、前記接続端子が延在する方向に沿って、設けられた複数の開口部と、を備えた電子基板。 - 前記複数の開口部に代えて、前記複数の接続端子のうちで互いに隣接する接続端子の間であって前記接続端子が延在する領域に亘り、前記接続端子が延在する方向に沿って、設けられた長矩形状の開口部と、を備えた請求項1に記載の電子基板。
- 前記開口部は、前記一対の主面間を貫通する貫通穴である請求項1または2に記載の電子基板。
- 前記開口部は、前記一対の主面間を貫通しない溝である請求項1または2に記載の電子基板。
- 前記複数の接続端子は、前記基材の端部側であって、前記基材の前記一対の主面の双方の面上に配列して形成され、前記基材の前記一対の主面の一方に形成された複数の第1の接続端子と、前記基材の前記一対の主面の他方に形成された複数の第2の接続端子とからなり、
前記複数の第1の接続端子および第2の接続端子は、互いに向かい合うように配列して設けられた請求項3または4に記載の電子基板。 - 前記複数の接続端子は、前記基材の端部側であって、前記基材の前記一対の主面の双方の面上に配列して形成され、前記基材の前記一対の主面の一方に形成された複数の第1の接続端子と、前記基材の前記一対の主面の他方に形成された複数の第2の接続端子とからなり、
前記複数の第1の接続端子および第2の接続端子は、互いに向かい合わないように配列して設けられた請求項4に記載の電子基板。 - 平板状の電子基板と、前記電子基板の端部を保持するコネクタとを有する電子基板のコネクタ接続構造であって、
一対の主面が互いに向かい合う平板上の基材と、
前記基材の端部側であって、前記基材の前記一対の主面の少なくとも一方の面上に配列して形成された複数の接続端子と、
前記複数の接続端子に接続された複数の配線と、
前記複数の接続端子のうちで互いに隣接する接続端子の間であって前記接続端子が延在する領域に亘り、前記接続端子が延在する方向に沿って、設けられた複数の開口部と、を備え、
前記コネクタは、
前記電子基板を保持した際に、前記複数の接続端子に接触するコネクタ側接続端子を備えた電子基板のコネクタ接続構造。
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JP2014552915A JP5930069B2 (ja) | 2012-12-18 | 2013-12-11 | 電子基板及びそのコネクタ接続構造 |
US14/652,463 US9433094B2 (en) | 2012-12-18 | 2013-12-11 | Electronic substrate and structure for connector connection thereof |
CN201380066633.6A CN104871654B (zh) | 2012-12-18 | 2013-12-11 | 电子基板及其接头连接的结构 |
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