WO2014097369A1 - 窒化物半導体を用いたトランジスタおよびその製造方法 - Google Patents
窒化物半導体を用いたトランジスタおよびその製造方法 Download PDFInfo
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- WO2014097369A1 WO2014097369A1 PCT/JP2012/082660 JP2012082660W WO2014097369A1 WO 2014097369 A1 WO2014097369 A1 WO 2014097369A1 JP 2012082660 W JP2012082660 W JP 2012082660W WO 2014097369 A1 WO2014097369 A1 WO 2014097369A1
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- 150000004767 nitrides Chemical class 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 title description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims description 44
- 238000005530 etching Methods 0.000 claims description 14
- 230000010287 polarization Effects 0.000 claims description 13
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical group Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 12
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims 3
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- 239000010410 layer Substances 0.000 description 156
- 229910002601 GaN Inorganic materials 0.000 description 30
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 30
- 239000000758 substrate Substances 0.000 description 13
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- 238000010894 electron beam technology Methods 0.000 description 6
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- 229910052751 metal Inorganic materials 0.000 description 5
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- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
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- -1 AlGaN Chemical compound 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Definitions
- the present invention relates to a nitride semiconductor high electron mobility transistor (HEMT) typified by GaN (gallium nitride) and a method for manufacturing the transistor.
- HEMT nitride semiconductor high electron mobility transistor
- FIG. 1 of Non-Patent Document 1 shows a structural cross-sectional view of a GaN HEMT having an AlN spacer.
- AlN spacer layer AlN
- AlGaN barrier layer
- Si3N4 nitride film
- GaN HEMTs are used for high-power high-frequency amplifiers and power switch circuits.
- it is necessary to reduce the access resistance existing in series between the source electrode and the drain electrode.
- an AlN spacer is inserted between AlGaN (aluminum gallium nitride) and GaN. Since AlN has a polarization greater than that of AlGaN, the insertion of an AlN spacer increases the two-dimensional electron gas concentration and reduces the access resistance.
- FIG. 1 is a schematic cross-sectional view showing an example of the structure of a conventional high electron mobility transistor (GaN HEMT) using a nitride semiconductor.
- this conventional GaN HEMT has an AlN spacer inserted therein, and includes a substrate 1, a buffer layer 2, a channel layer 3, a spacer layer 4, a barrier layer 5, an insulating film layer 6, a source electrode 7, A drain electrode 8 and a gate electrode 9 are provided.
- This conventional structure has a structure in which the AlN spacer layer 4 is present on the entire surface including immediately below the gate electrode 9.
- the present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a highly reliable transistor using a nitride semiconductor and a method of manufacturing the same while suppressing an increase in access resistance.
- the present invention provides a channel layer in which electrons travel and one of indium, aluminum, and gallium provided above the channel layer for forming a two-dimensional electron gas in the channel layer.
- a transistor using a nitride semiconductor including a barrier layer containing one or more and nitrogen, and a gate electrode, a source electrode, and a drain electrode above the barrier layer, the transistor is inserted between the barrier layer and the channel layer And a spacer layer having a polarization greater than that of the barrier layer, wherein the spacer layer does not exist only near the gate electrode.
- the AlN spacer layer does not exist only in the vicinity immediately under the gate electrode, the gate electrode end electric field is reduced and the gate leakage current is reduced and the reliability is ensured as compared with the conventional transistor.
- the length of the portion where the AlN spacer layer does not exist is sufficiently smaller than the distance between the source electrode and the drain electrode, the access resistance reduction by the AlN spacer layer can be maintained at the same level as the conventional structure. The increase in access resistance can be suppressed.
- FIG. 3 is a schematic cross section which shows an example of the structure of the high electron mobility transistor (GaN HEMT) using the conventional nitride semiconductor.
- 3 is a schematic cross-sectional view showing an example of a structure of a high electron mobility transistor (GaN HEMT) using the nitride semiconductor according to Embodiment 1.
- FIG. 3 is a block diagram illustrating an example of a configuration of a sound processing unit according to Embodiment 1.
- FIG. It is a figure which shows the W / Lg dependence of the access resistance Ron and the reverse direction gate current -Igd of the structure by the conventional structure and this Embodiment 1.
- FIG. 6 is a schematic cross-sectional view showing an example of a structure of a high electron mobility transistor (GaN HEMT) using a nitride semiconductor according to Embodiment 2.
- FIG. 6 is a schematic cross-sectional view showing an example of a structure of a high electron mobility transistor (GaN HEMT) using a nitride semiconductor in Embodiment 3.
- FIG. 3 it is a figure which shows the manufacturing method which forms a gate electrode after the manufacturing method shown in FIG.
- FIG. FIG. 2 is a schematic cross-sectional view showing an example of the structure of a high electron mobility transistor (GaN HEMT) using a nitride semiconductor according to Embodiment 1 of the present invention.
- GaN HEMT high electron mobility transistor
- FIG. 1 the same code
- symbol is attached
- the first embodiment shown below differs from the conventional diagram (FIG. 1) in that there is a portion where the AlN spacer layer 4 does not exist.
- Lg10 indicates the length in the left-right direction of the gate electrode 9
- W11 indicates the length in the left-right direction of the portion where the spacer layer 4 does not exist
- Lsd12 indicates the length in the left-right direction between the source electrode 7 and the drain electrode 8.
- the GaN HEMT according to the first embodiment is used as a single amplifier, but can also be applied to a transistor constituting an MMIC (monolithic microwave integrated circuit).
- the substrate sapphire, SiC (silicon carbide), Si (silicon), a GaN substrate or the like is used.
- a semi-insulating SiC substrate having a good thermal conductivity is generally used, but a very general Si substrate as a semiconductor substrate is often used because of its low price.
- the buffer layer 2 is a layer inserted between the substrate 1 and the channel layer 3, and is intended to improve the crystallinity of the channel layer 3 and to confine electrons in the channel, so that AlN, AlGaN, GaN / InGaN, AlN Various structures such as / AlGaN and their superlattices are used.
- the channel layer 3 is a layer in which electrons (current) necessary for transistor operation travel.
- a typical channel layer 3 is GaN, but InGaN (indium gallium nitride), AlGaN, or a multilayer structure thereof can also be used.
- the spacer layer 4 is inserted between the channel layer 3 and the barrier layer 5, and in the conventional structure (FIG. 1), exists on the entire surface of the source electrode 7 and the drain electrode 8 (the entire surface including immediately below the gate electrode 9).
- the AlN spacer layer 4 does not exist only near the gate electrode 9. It is assumed that the midpoint of Lg10 and the midpoint of W11 coincide with each other in the horizontal direction.
- the spacer layer 4 is not limited to AlN, and may be any material such as InGaN or AlGaN that has a higher polarization than the barrier layer 5.
- the barrier layer 5 is provided above the channel layer 3 to form a two-dimensional electron gas in the channel layer 3, and one or more of In (indium), Al (aluminum), Ga (gallium) and N ( Nitrogen).
- the interface between the channel layer 3 and the AlN spacer layer 4 is formed by a heterojunction having a wider band gap than the channel layer 3. Any structure from the substrate 1 to the channel layer 3 can be applied to the present invention.
- the insulating film layer 6 on the barrier layer 5 serves as a film for suppressing the number of traps on the surface of the barrier layer 5.
- the insulating film layer 6 may be formed of an insulating film containing Si serving as a donor such as SiN (silicon nitride) or SiO (silicon oxide) as a material. If Si is contained, electrons can be supplied to the barrier layer 5 as a donor, and the number of traps on the surface of the barrier layer 5 can be reduced.
- the source electrode 7 and the drain electrode 8 are electrodes for taking out current (electrons) in the channel layer 3 out of the HEMT. For this reason, it forms so that resistance between an electrode and two-dimensional electron gas may be reduced as much as possible.
- FIG. 2 shows an example in which the source electrode 7 and the drain electrode 8 are formed so as to be in contact with the barrier layer 5, they may be formed so as to be in direct contact with a two-dimensional electron gas (2DEG). Further, an n + region may be formed under the source electrode 7 and the drain electrode 8.
- the gate electrode 9 is formed so as to include a metal in Schottky contact with the barrier layer 5, and the transistor operation is realized by controlling the 2DEG concentration under the gate electrode 9.
- the gate electrode 9 has a gate field plate structure (GFP structure) such that a part thereof protrudes onto the insulating film layer 6.
- GFP structure has a role of relaxing the electric field concentration on the surface of the barrier layer 5.
- the principle that the gate leakage current is reduced and the reliability is ensured as compared with the conventional structure, and the effect of reducing the access resistance is maintained at the same level as the conventional structure will be described.
- an AlN spacer layer 4 is inserted between the source electrode 7 and the drain electrode 8 over the entire surface. Since the polarization of the AlN spacer layer 4 is larger than that of the barrier layer 5, the concentration of the two-dimensional electron gas existing in the channel layer 3 can be increased by inserting the AlN spacer layer 4 than when only the barrier layer 5 is present. .
- the access resistance existing between the source electrode 7 and the drain electrode 8 can be reduced.
- the electric field concentrated especially on the gate electrode end increases.
- An increase in the electric field at the end of the gate electrode increases a tunnel current from the electrons toward the barrier layer 5 from the gate electrode 9, so that the reverse gate leakage current during the off operation increases.
- An increase in reverse gate leakage current can be a factor that degrades the reliability of GaN HEMTs.
- the AlN spacer layer 4 in the vicinity immediately under the gate electrode 9 that caused the increase in the electric field at the gate electrode end is eliminated, thereby The electric field can be reduced and the reverse gate leakage current can be reduced. Further, since the length W11 of the portion from which the AlN spacer layer 4 is deleted is sufficiently smaller than the length Lsd12 between the source electrode 7 and the drain electrode 8, the access resistance can be reduced even if the AlN spacer layer 4 is deleted. Is considered to be kept almost the same as the conventional structure.
- the principle described above was verified by device simulation.
- the GaN HEMT having the conventional structure shown in FIG. 1 and the structure according to the first embodiment of the present invention shown in FIG. 2, an electric field 0.5 nm below the surface of the barrier layer 5 when the gate voltage is ⁇ 5V and the drain voltage is 30V.
- the channel layer 3 was GaN
- the spacer layer 4 was AlN
- the barrier layer 5 was AlGaN (Al composition: 0.23).
- the thickness of the channel layer 3 was 1.2 ⁇ m
- the thickness of the spacer layer 4 was 1 nm
- the thickness of the barrier layer 5 was 20 nm.
- the ratio (W / Lg) of the length W11 of the portion from which the AlN spacer layer 4 is deleted in the structure of the first embodiment of the present invention to the gate length Lg10 is set to “2”.
- the polarization of the portion where the AlN spacer layer 4 is present is 5.27E-12 cm ⁇ 3 , which is the average value of the polarization of the AlGaN barrier layer 5 and the polarization of the AlN spacer layer 4, and the polarization of the portion where the AlN spacer layer 4 is not present is AlGaN
- the polarization of the barrier layer 5 was set to 8.85E-12 cm ⁇ 3 .
- FIG. 3 is a diagram showing the electric field at the gate electrode end with respect to the lateral distance (position from the lateral center) 0.5 nm below the surface of the barrier layer 5. As shown in FIG. 3, it can be seen that the electric field in the vicinity of the gate electrode can be reduced in the structure according to the first embodiment as compared with the conventional structure.
- the reverse current ⁇ Igd is greatly reduced until W / Lg is 2, but when W / Lg is greater than 2, (W It can be seen that the reverse current ⁇ Igd gradually saturates (when the current becomes twice Lg). Further, the access resistance Ron increases as W / Lg increases. This is because when the W / Lg increases, the length of the AlN spacer layer 4 with respect to Lsd12 decreases, so that the effect of increasing the two-dimensional electron gas by the AlN spacer is reduced.
- FIG. 5 is a view showing a manufacturing method up to forming the buffer layer 2, the channel layer 3, the spacer layer 4, the barrier layer 5, the insulating film layer 6, the source electrode 7 and the drain electrode 8 on the substrate 1. is there.
- FIG. 6 is a view showing a manufacturing method for forming the gate electrode 9 thereafter.
- a buffer layer 2, a channel layer 3, and a spacer layer 4 are formed on a substrate 1.
- MOCVD Metal-Organic-Chemical-Vapor-Deposition
- MBE Molecular-Beam Epitaxy
- the spacer layer 4 may be made of a material having polarization larger than that of the barrier layer 5 as well as AlN.
- the manufacturing method up to the formation of the spacer layer 4 on the channel layer 3 is the same as the conventional method.
- a pattern having an opening in the region where the AlN spacer layer 4 near the gate electrode 9 is removed by photolithography is formed with a resist 13. That is, the resist 13 is patterned on the spacer layer 4 except for a portion where the spacer layer 4 is removed. Then, using the patterned resist 13 as a mask, the AlN spacer layer 4 in a region immediately below the gate electrode 9 is removed by etching, and then the patterned resist 13 is removed.
- the barrier layer 5 is regrown and formed on the channel layer 3 and the AlN spacer layer 4.
- MOCVD can be used.
- an insulating film layer 6 is formed on the barrier layer 5 as shown in FIG.
- the material of the insulating film layer 6 is typically SiN or SiO, but other materials may be used as long as the insulating film contains Si.
- the source electrode 7 and the drain electrode 8 in order to form the source electrode 7 and the drain electrode 8, a portion of the insulating film corresponding to the position where the source electrode 7 and the drain electrode 8 are formed on a mask made of resist or SiO. Layer 6 is removed. Thereafter, the source electrode 7 and the drain electrode 8 can be formed by forming a metal such as Ti / Al / Ni / Au and Ti / Al and performing heat treatment. In this step, it is possible to add a heat treatment in which a dopant such as Si ions is implanted and electrically activated.
- a pattern having an opening in a region to be a gate electrode by photolithography is formed with a resist 13. That is, the resist 13 is re-patterned on the insulating film layer 6, the source electrode 7 and the drain electrode 8 except for the portion where the gate electrode 9 is formed. Then, as shown in FIG. 6B, using the re-patterned resist 13 as a mask, the insulating film layer 6 in the region to be the gate electrode 9 is removed by etching, and then the re-patterned resist 13 is removed. remove.
- a pattern having an opening larger than the region etched in FIG. 6B is formed so that the gate electrode 9 is also formed on the insulating film layer 6 by photolithography.
- a resist 13 is used. That is, the resist 13 having an opening larger than the region where the insulating film layer 6 is removed by etching is finally patterned.
- a gate electrode 9 is formed on the region where the insulating film layer 6 has been removed by etching and the insulating film layer 6, and the final patterned resist is removed.
- a metal having a Schottky characteristic is deposited (EB (electron beam) deposition or sputtering can be used), and the resist 13 is removed (lifted off), whereby a structure as shown in FIG. Can be formed.
- a protective film, wiring, via-hole wiring, capacitance, resistance, and the like are manufactured as necessary, but illustration and description are omitted here.
- the AlN spacer layer does not exist only in the immediate vicinity of the gate electrode, so that the gate electrode end electric field is reduced and the gate leakage current is reduced as compared with the conventional transistor. Reliability.
- the length of the portion where the AlN spacer layer does not exist is sufficiently smaller than the distance between the source electrode and the drain electrode, the access resistance reduction by the AlN spacer layer can be maintained at the same level as the conventional structure. The increase in access resistance can be suppressed.
- FIG. FIG. 7 is a schematic cross-sectional view showing an example of the structure of a high electron mobility transistor (GaN HEMT) using a nitride semiconductor according to Embodiment 2 of the present invention.
- GaN HEMT high electron mobility transistor
- FIG. 7 the same code
- the structure of the gate electrode 9 is different from that in the first embodiment, and the gate electrode 9 on the insulating film layer 6 has a two-stage structure.
- the effect of dispersing the electric field concentrated on the end of the gate electrode is increased. Therefore, a larger electric field can be reduced than in the first embodiment, the reverse gate leakage current is reduced, and the reliability is further improved.
- the buffer layer 2, the channel layer 3, the spacer layer 4, the barrier layer 5, the insulating film layer 6, the source electrode 7 and the drain electrode 8 are formed on the substrate 1.
- the manufacturing method up to this point is the same as the method described with reference to FIG. 6 in the first embodiment.
- a pattern having an opening in a region to be a gate electrode by photolithography is formed with the resist 13 as in the first embodiment.
- a two-layer structure is formed with an insulating film having a slow etching rate as a lower layer and an insulating film having a fast etching rate as an upper layer.
- a method for forming this two-layer structure there are various methods such as cat-CVD (Catalytic Chemical Vapor Deposition), plasma CVD, and sputtering.
- the insulating film layer 6 In order to make the insulating film layer 6 have a two-layer structure with different etching rates in this way, as shown in FIG. 6B, after the insulating film layer 6 in the region to be the gate electrode is etched, before the resist 13 is removed. Only the upper layer is wet etched. Of the two layers of the insulating film layer 6, the upper layer has a high etching rate, so that the side surface of the etched portion can be formed in two steps, and the insulating film layer 6 having the two-layer structure in the second embodiment can be formed.
- an opening larger than the region etched in FIG. 6B is formed so that the gate electrode 9 is also formed on the insulating film 6 by photolithography as shown in FIG. 6C.
- the held pattern is formed with the resist 13.
- a metal having Schottky characteristics is deposited (EB (electron beam) deposition or sputtering can be used), and the resist 13 is removed (lifted off), thereby forming a structure as shown in FIG. .
- a protective film, wiring, via-hole wiring, capacitance, resistance, and the like are manufactured as necessary, but illustration and description are omitted here.
- the gate electrode since the gate electrode has a two-stage structure, the edge is increased, and the effect of dispersing the electric field concentrated on the gate electrode end is increased.
- the electric field can be reduced more than that of the transistor in FIG. 1, the reverse gate leakage current is reduced, and the reliability is further improved.
- FIG. 8 is a schematic cross-sectional view showing an example of the structure of a high electron mobility transistor (GaN HEMT) using a nitride semiconductor according to Embodiment 3 of the present invention.
- GaN HEMT high electron mobility transistor
- FIG. 8 the same code
- the structure of the gate electrode 9 is different from that in the first embodiment, and the side surface of the gate electrode 9 on the insulating film layer 6 has an oblique structure.
- the electric field is averaged by making the gate electrode 9 slant, the electric field concentrated on the end of the gate electrode can be reduced. Therefore, a larger electric field can be reduced than in the first embodiment, the reverse gate leakage current is reduced, and the reliability is further improved.
- FIG. 9 is a diagram showing a manufacturing method for forming the gate electrode 9 after the manufacturing method shown in FIG. 5 in the third embodiment.
- a pattern having an opening in a region to be a gate electrode by photolithography is formed with a resist 13.
- the side surface of the etched portion is inclined according to the etching conditions at this time, the insulating film layer 6 in the region to be the gate electrode is removed by etching, and then the resist 13 is removed. .
- a pattern having an opening larger than the region etched in FIG. 9B is formed on the resist 13 so that the gate electrode 9 is also formed on the insulating film layer 6 by photolithography.
- a metal having Schottky characteristics is deposited (EB (electron beam) deposition or sputtering can be used), and the resist 13 is removed (lifted off), whereby a structure as shown in FIG. 8 can be formed.
- EB electron beam
- sputtering can be used
- a protective film, wiring, via-hole wiring, capacitance, resistance, and the like are manufactured as necessary, but illustration and description are omitted here.
- the electric field is averaged and the electric field concentrated on the end of the gate electrode can be reduced.
- the electric field can be reduced larger than that of the transistor, the reverse gate leakage current is reduced, and the reliability is further improved.
- the transistor using the nitride semiconductor of the present invention and the manufacturing method thereof can be applied to amplifiers and power switch circuits.
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Abstract
Description
増幅器やスイッチ回路の効率を上げるためには、ソース電極とドレイン電極の間に直列に存在するアクセス抵抗を低減する必要がある。このアクセス抵抗を低減させる手法のひとつとして、AlGaN(窒化アルミニウムガリウム)とGaNの間にAlNスペーサを挿入方法がとられてきた。AlNは分極がAlGaNより大きいため、AlNスペーサを入れることで2次元電子ガス濃度が増大し、アクセス抵抗を低減することができる。
実施の形態1.
図2は、この発明の実施の形態1における窒化物半導体を用いた高電子移動度トランジスタ(GaN HEMT)の構造の一例を示す模式断面図である。なお、従来図(図1)で説明したものと同様の構成には、同一の符号を付して重複した説明を省略する。以下に示す実施の形態1では、従来図(図1)と比べると、AlNスペーサ層4が存在しない部分がある点が異なる。
基板1には、サファイア、SiC(炭化ケイ素)、Si(ケイ素)、GaN基板などが用いられる。特に、熱伝導率の良好な半絶縁性SiC基板が一般的に利用されるが、半導体基板として非常に一般的なSi基板も価格が安いため、よく用いられている。
チャネル層3は、トランジスタ動作に必要な電子(電流)が走行する層である。典型的なチャネル層3はGaNであるが、InGaN(インジウム窒化ガリウム)、AlGaNやこれらの多層構造も使うことができる。
チャネル層3とAlNスペーサ層4が接触する界面は、チャネル層3よりバンドギャップが広いヘテロ接合で形成させる。基板1からチャネル層3に至る構造のいかなるものでも、この発明に適用できる。
図1に示すように従来構造はソース電極7とドレイン電極8の間にAlNスペーサ層4が全面に挿入されている。AlNスペーサ層4は分極がバリア層5に比べて大きいため、バリア層5しか存在しない場合よりAlNスペーサ層4を挿入することでチャネル層3に存在する2次元電子ガス濃度を増大させることができる。
図4は、従来構造とこの実施の形態1による構造の、アクセス抵抗Ronと逆方向ゲートリーク電流-IgdのW/Lg依存性を示す図である。従来構造においてはW=0であるので、図4における横軸W/Lg=0のときの値が、従来構造におけるアクセス抵抗Ronと-Vgd=100Vであるときの逆方向ゲートリーク電流-Igdを示している。
また、アクセス抵抗Ronは、W/Lgが増大すると増大する。これはW/Lgが増大するとLsd12に対するAlNスペーサ層4が存在する長さが減少するためAlNスペーサによる2次元電子ガス増大効果が薄れるためである。W/Lgが2のとき、すなわち、スペーサ層4が存在しない部分の左右方向の長さW11が、ゲート電極9の左右方向の長さLg10の2倍のときに、AlNスペーサ層4が削除されている部分がゲート電極9直下の近傍であるため、アクセス抵抗Ronの増大を抑えつつ、逆方向ゲートリーク電流-Igdを大幅に低減できると言える。
図5は、基板1の上に、バッファ層2、チャネル層3、スペーサ層4、バリア層5、絶縁膜層6、ソース電極7およびドレイン電極8を形成するところまでの製造方法を示す図である。また図6は、その後にゲート電極9を形成する製造方法を示す図である。
そして、パターニングされたレジスト13をマスクとして用いて、ゲート電極9の直下となる領域のAlNスペーサ層4をエッチングにより除去してから、パターニングされたレジスト13を取り除く。
さらに、図5(d)に示すように、バリア層5の上に絶縁膜層6を形成する。絶縁膜層6の材料はSiN、SiOが典型的であるがSiを含んだ絶縁膜であれば他の材料であっても良い。
そして、図6(b)に示すように、再パターニングされたレジスト13をマスクとして用いて、ゲート電極9となる領域の絶縁膜層6をエッチングにより除去してから、再パターニングされたレジスト13を取り除く。
図7は、この発明の実施の形態2における窒化物半導体を用いた高電子移動度トランジスタ(GaN HEMT)の構造の一例を示す模式断面図である。なお、従来図(図1)および実施の形態1で説明したものと同様の構成には、同一の符号を付して重複した説明を省略する。以下に示す実施の形態2では、実施の形態1と比べると、ゲート電極9の構造が異なっており、絶縁膜層6上のゲート電極9が2段構造になっている。
次に、図6(a)に示すように、写真製版でゲート電極となる領域に開口を持ったパターンをレジスト13で形成するのも実施の形態1と同じである。
そして、ショットキー特性を持つ金属を蒸着(EB(electron beam:電子ビーム)蒸着やスパッタ法が使用できる)し、レジスト13を除去(リフトオフ)することで、図7に示すような構造を形成できる。最後に、保護膜や配線、ビアホール配線、容量、抵抗等を必要に応じて作製するが、ここでは図示および説明を省略する。
図8は、この発明の実施の形態3における窒化物半導体を用いた高電子移動度トランジスタ(GaN HEMT)の構造の一例を示す模式断面図である。なお、従来図(図1)および実施の形態1,2で説明したものと同様の構成には、同一の符号を付して重複した説明を省略する。以下に示す実施の形態3では、実施の形態1と比べると、ゲート電極9の構造が異なっており、絶縁膜層6上のゲート電極9の側面が斜め構造になっている。
図9は、実施の形態3において、図5に示す製造方法の後に、ゲート電極9を形成する製造方法を示す図である。
そして、図9(b)に示すように、この時のエッチングの条件によってエッチング部分の側面を斜めにして、エッチングによってゲート電極となる領域の絶縁膜層6を除去してから、レジスト13を取り除く。
そして、ショットキー特性を持つ金属を蒸着(EB(electron beam:電子ビーム)蒸着やスパッタ法が使用できる)し、レジスト13を除去(リフトオフ)することで、図8に示すような構造を形成できる。最後に、保護膜や配線、ビアホール配線、容量、抵抗等を必要に応じて作製するが、ここでは図示および説明を省略する。
Claims (6)
- 電子が走行するチャネル層と、当該チャネル層に2次元電子ガスを形成するための前記チャネル層の上方に設けられたインジウム、アルミニウム、ガリウムのうちの1つ以上と窒素とを含むバリア層と、当該バリア層の上部にゲート電極、ソース電極およびドレイン電極を具備する、窒化物半導体を用いたトランジスタにおいて、
前記バリア層と前記チャネル層との間に挿入され、前記バリア層より分極が大きいスペーサ層をさらに備え、
当該スペーサ層は、前記ゲート電極の直下近傍のみ存在しない
ことを特徴とする窒化物半導体を用いたドランジスタ。 - 前記スペーサ層が窒化アルミニウムであることを特徴とする請求項1記載のトランジスタ。
- 前記スペーサ層が存在しない部分の左右方向の長さが、前記ゲート電極の左右方向の長さの2倍であることを特徴とする請求項1記載のトランジスタ。
- 前記ゲート電極が2段構造になっていることを特徴とする請求項1記載のトランジスタ。
- 前記ゲート電極の側面が斜めになっていることを特徴とする請求項1記載のトランジスタ。
- 電子が走行するチャネル層と、当該チャネル層に2次元電子ガスを形成するための前記チャネル層の上方に設けられたインジウム、アルミニウム、ガリウムのうちの1つ以上と窒素とを含むバリア層と、当該バリア層の上部にゲート電極、ソース電極およびドレイン電極を具備する、窒化物半導体を用いたトランジスタの製造方法であって、
前記チャネル層の上に、前記バリア層より分極が大きいスペーサ層を形成するステップと、
前記スペーサ層の上に、当該スペーサ層を除去する部分を除いてレジストをパターニングするステップと、
前記パターニングされたレジストをマスクとして用いて前記ゲート電極の直下となる領域の前記スペーサ層をエッチング除去するステップと、
前記パターニングされたレジストを除去するステップと、
前記チャネル層および前記スペーサ層の上部に前記バリア層を形成するステップと、
前記バリア層の上に絶縁膜層を形成するステップと、
前記ソース電極および前記ドレイン電極が形成される位置に対応する前記絶縁膜層を除去した後に、前記ソース電極および前記ドレイン電極を形成するステップと、
前記絶縁膜層、前記ソース電極および前記ドレイン電極の上に、前記ゲート電極を形成する部分を除いてレジストを再パターニングするステップと、
前記再パターニングされたレジストをマスクとして用いて前記ゲート電極となる領域の前記絶縁膜層をエッチング除去するステップと、
前記再パターニングされたレジストを除去するステップと、
前記絶縁膜層をエッチング除去した領域より大きい開口を持ったレジストを最終パターニングするステップと、
前記絶縁膜層をエッチング除去した領域および前記絶縁膜層の上に前記ゲート電極を形成するステップと、
前記最終パターニングされたレジストを除去するステップと
を備えることを特徴とするトランジスタの製造方法。
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- 2012-12-17 EP EP12890237.6A patent/EP2933827B1/en active Active
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Publication number | Publication date |
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EP2933827B1 (en) | 2021-09-15 |
JPWO2014097369A1 (ja) | 2017-01-12 |
JP5744346B2 (ja) | 2015-07-08 |
EP2933827A1 (en) | 2015-10-21 |
US20150249150A1 (en) | 2015-09-03 |
US9570599B2 (en) | 2017-02-14 |
EP2933827A4 (en) | 2016-10-26 |
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