JP2016531420A - 窒化ガリウムデバイス及び集積回路において自己整合分離を製作する方法 - Google Patents
窒化ガリウムデバイス及び集積回路において自己整合分離を製作する方法 Download PDFInfo
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- 238000002955 isolation Methods 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 47
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title description 30
- 229910002601 GaN Inorganic materials 0.000 title description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims abstract description 71
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 229910002704 AlGaN Inorganic materials 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 16
- 238000000926 separation method Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Junction Field-Effect Transistors (AREA)
Abstract
Description
Claims (16)
- 少なくとも2つのトランジスタデバイスを有する集積回路を形成する方法であって、当該方法は、
基板の上に緩衝層を形成するステップと、
前記緩衝層の上にGaN層を形成するステップと、
前記GaN層の上にバリア層を形成するステップと、
前記バリア層の上に誘電層を形成するステップと、
前記誘電層に前記少なくとも2つのトランジスタデバイスのそれぞれのための少なくとも1つのデバイスコンタクト開口を、前記誘電層の、前記少なくとも2つのトランジスタデバイスの間に分離コンタクト開口を形成するステップと、
前記誘電層、前記デバイスコンタクト開口及び前記分離コンタクト開口の上に金属層を形成するステップと、
各前記デバイスコンタクト開口の上にフォトレジスト膜を形成するステップと、
前記分離コンタクト開口の上に金属マスクの窓を形成するために前記金属層をエッチングするステップと、
前記誘電層内の前記分離コンタクト開口によって露出された前記バリア層及び前記GaN層の一部をエッチングするステップと、
を含む方法。 - 前記金属層をエッチングするステップは、Cl2プラズマ、BCl3プラズマ及びArプラズマのうちの少なくとも1つを含むプラズマを用いた金属エッチングを含む、請求項1に記載の方法。
- 前記少なくとも2つのトランジスタデバイスのそれぞれのための前記デバイスコンタクト開口はそれぞれのゲートコンタクトを定義する、請求項1に記載の方法。
- 前記デバイスコンタクト開口は、前記少なくとも2つのトランジスタデバイスのそれぞれのためのドレインオーミックコンタクト及びソースオーミックコンタクトをそれぞれ定義する一対のデバイスコンタクト開口を含む、請求項1に記載の方法。
- 前記GaN層はドープされておらず、0.5〜10μmの厚さを含む、請求項1に記載の方法。
- 前記バリア層はドープされておらず、50オングストローム〜300オングストロームの厚さを含む、請求項1に記載の方法。
- 前記バリア層はAlGaNを含み、該AlGaNのAl組成比が10%〜35%である、請求項6に記載の方法。
- トランジスタデバイスを形成する方法であって、当該方法は、
基板の上に緩衝層を形成するステップと、
前記緩衝層の上にGaN層を形成するステップと、
前記GaN層の上にバリア層を形成するステップと、
前記バリア層の上に誘電層を形成するステップと、
前記誘電層に少なくとも1つのデバイスコンタクト開口と、分離コンタクト開口とを形成するステップと、
前記誘電層、前記少なくとも1つのデバイスコンタクト開口及び前記分離コンタクト開口の上に金属層を形成するステップと、
前記少なくとも1つのデバイスコンタクト開口の上にフォトレジスト膜を形成するステップと、
前記分離コンタクト開口の上に金属マスクの窓を形成するために前記金属層をエッチングするステップと、
前記誘電層内の前記分離コンタクト開口によって露出された前記バリア層及び前記GaN層の一部をエッチングするステップと、
を含む方法。 - 前記分離コンタクト開口は前記金属マスクの窓よりも幅広である、請求項1又は8に記載の方法。
- 前記金属マスクの窓は前記分離コンタクト開口よりも幅広である、請求項1又は8に記載の方法。
- 前記誘電層に少なくとも1つのデバイスコンタクト開口と、分離コンタクト開口とを形成するステップは、前記バリア層を露出するために前記誘電層をエッチングすることを含む、請求項8に記載の方法。
- 前記フォトレジスト膜を剥離するステップをさらに含む、請求項1又は8に記載の方法。
- 前記少なくとも1つのデバイスコンタクト開口は、前記トランジスタデバイスのためのゲートコンタクトを定義する、請求項8に記載の方法。
- 前記少なくとも1つのデバイスコンタクト開口は、前記トランジスタデバイスのためのドレインオーミックコンタクト及びソースオーミックコンタクトをそれぞれ定義する一対のデバイスコンタクト開口を含む、請求項8に記載の方法。
- 前記フォトレジストは、前記金属層のエッチングのためのエッチストップとして機能する、請求項4又は14に記載の方法。
- 前記金属層をエッチングするステップは、各デバイスのドレインオーミックコンタクトとソースオーミックコンタクトとの間にそれぞれの金属空間を定義することを含む、請求項15に記載の方法。
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US61/843,804 | 2013-07-08 | ||
PCT/US2014/045246 WO2015006131A1 (en) | 2013-07-08 | 2014-07-02 | Method to fabricate self-aligned isolation in gallium nitride devices and integrated circuits |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01179458A (ja) * | 1988-01-07 | 1989-07-17 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2007048863A (ja) * | 2005-08-09 | 2007-02-22 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2011082217A (ja) * | 2009-10-02 | 2011-04-21 | Fujitsu Ltd | 化合物半導体装置及びその製造方法 |
JP2013012735A (ja) * | 2011-06-20 | 2013-01-17 | Imec | Hemt装置を製造するcmosコンパチブルな方法とそのhemt装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100320364B1 (ko) * | 1993-03-23 | 2002-04-22 | 가와사키 마이크로 엘렉트로닉스 가부시키가이샤 | 금속배선및그의형성방법 |
US7238560B2 (en) | 2004-07-23 | 2007-07-03 | Cree, Inc. | Methods of fabricating nitride-based transistors with a cap layer and a recessed gate |
US20060226442A1 (en) * | 2005-04-07 | 2006-10-12 | An-Ping Zhang | GaN-based high electron mobility transistor and method for making the same |
US7972915B2 (en) * | 2005-11-29 | 2011-07-05 | The Hong Kong University Of Science And Technology | Monolithic integration of enhancement- and depletion-mode AlGaN/GaN HFETs |
US7932539B2 (en) * | 2005-11-29 | 2011-04-26 | The Hong Kong University Of Science And Technology | Enhancement-mode III-N devices, circuits, and methods |
US7592211B2 (en) * | 2006-01-17 | 2009-09-22 | Cree, Inc. | Methods of fabricating transistors including supported gate electrodes |
CN100468718C (zh) * | 2006-04-30 | 2009-03-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其制造方法 |
US20100117188A1 (en) | 2007-03-05 | 2010-05-13 | General Electric Company | Method for producing trench isolation in silicon carbide and gallium nitride and articles made thereby |
US7898004B2 (en) * | 2008-12-10 | 2011-03-01 | Transphorm Inc. | Semiconductor heterostructure diodes |
US8436398B2 (en) * | 2009-04-08 | 2013-05-07 | Efficient Power Conversion Corporation | Back diffusion suppression structures |
US8168486B2 (en) | 2009-06-24 | 2012-05-01 | Intersil Americas Inc. | Methods for manufacturing enhancement-mode HEMTs with self-aligned field plate |
KR101248005B1 (ko) * | 2009-11-17 | 2013-03-27 | 엘지디스플레이 주식회사 | 어레이 기판 및 그의 제조방법 |
EP2793255B8 (en) * | 2013-04-16 | 2018-01-17 | IMEC vzw | Manufacturing method of a semiconductor device comprising a schottky diode and a high electron mobility transistor |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01179458A (ja) * | 1988-01-07 | 1989-07-17 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2007048863A (ja) * | 2005-08-09 | 2007-02-22 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2011082217A (ja) * | 2009-10-02 | 2011-04-21 | Fujitsu Ltd | 化合物半導体装置及びその製造方法 |
JP2013012735A (ja) * | 2011-06-20 | 2013-01-17 | Imec | Hemt装置を製造するcmosコンパチブルな方法とそのhemt装置 |
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JP6351718B2 (ja) | 2018-07-04 |
DE112014003175B4 (de) | 2020-12-03 |
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US9214528B2 (en) | 2015-12-15 |
WO2015006131A1 (en) | 2015-01-15 |
KR102193085B1 (ko) | 2020-12-21 |
KR20160030074A (ko) | 2016-03-16 |
TW201519364A (zh) | 2015-05-16 |
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