Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C16/40—Oxides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C16/40—Oxides
  • C23C16/401—Oxides containing silicon
  • C23C16/402—Silicon dioxide
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/01—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes on temporary substrates, e.g. substrates subsequently removed by etching
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/56—After-treatment
• • C—CHEMISTRY; METALLURGY
  • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
  • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
  • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
  • C25D5/48—After-treatment of electroplated surfaces
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer

Definitions

• the present invention relates to a method for applying a temporary boundary layer to a carrier wafer for temporary bonding to a product wafer by fusion bonding or anodic bonding according to claim 1.
• Object of the present invention is therefore to provide a method for applying a
• the invention is based on the idea, on the one hand to the
• fusion bonding or material suitable for anodic bonding to apply the temporary bonding layer and to act as a temporary bonding layer by modifying the temporary bonding layer during or after application such that a fusion bond or anodic bond is formed with a product wafer with corresponding, especially radical release agents is releasable again.
• the aforementioned measure is the use of carriers at much higher temperatures possible than before, so that a treatment of the
• the present invention is based on a
• Temporärbondtik in particular one, preferably exclusively, consisting of Si0 2 layer on a carrier wafer, in particular a Si wafer to deposit.
• the deposition process according to the invention is in particular PVD and / or CVD processes and / or sol gel processes and / or electrochemical deposition and / or wet chemical
• the temporary boundary layer is replaced by a
• Carrier substrate allows.
• the modification by surface treatment in particular by structuring and / or changing the microstructure of
• the surface treatment preferably takes place in such a way that a formation of the temporary boundary layer parallel to the carrier wafer takes place.
• the temporary boundary layer with, in particular chemically, preferably selectively on the
• Temporary BOND layer by exposure to a gas during the CVD process to trap gases in the pores. The properties of the trapped gas can then be used to dissolve the compound. Porosity, in conjunction with the disclosed channels, may also facilitate and assist the access of the release agent, especially if it is an open porosity. Therefore is also one
• gases all types of mono-, di- or polyatomic gases are used as gases according to the invention, but with preference to helium, argon, neon, hydrogen, oxygen, nitrogen, carbon dioxide, Ohlenmonoxid, water vapor, HCL, sulfuric acid, hydrofluoric acid.
• Nitric acid phosphoric acid, all organic acids.
• a glass carrier wafer and a silicon temporary body or silicon wafer carrier and a glass temporary moiety wafer are used.
• the anodic bonding is preferably carried out in a temperature range between 0 ° C and 800 ° C, with preference between 100 ° C and 700 ° C, more preferably between 200 ° C and 600 ° C, most preferably between 300 ° C and 500
• the absolute value of the voltage between anode and cathode is in the anodic bonding process in particular in the range between 0V and 1000V, preferably between 100V and 900V, more preferably between 200V and 800V, most preferably between 300V and 700V, most preferably between 400V and 600V.
• inventive method steps are provided in particular:
• the bond force is between 0 N and 100,000 N, preferably between 0 N and 10,000 N, more preferably between 0 N and 1000 N, most preferably between 0 N and 100 N.
• a temporary boundary layer of Si0 2 and a carrier wafer of silicon bonding takes place even at room temperature without force.
• Connection between the Si surface of the carrier wafer and the S 1 O 2 surface of the temporary boundary layer can be achieved by a corresponding
• Conceivable for the surface modification would be plasma treatment, wetting with DI water (DI deionized) or dry cleaning.
• FIGS. 2 a to 2 f show a second embodiment according to the invention with six method steps and
• Figure 3 shows a third embodiment of the invention
• a carrier wafer 1 is first coated with a temporary coloring layer 2.
• Temporary coloring layer 2 is preferably Si0 2 .
• the Coating can be done by any known coating method, but preferably by PVD, CVD or electrochemical
• the thickness of the temporary boundary layer 2 depends on
• the thickness of the Temporärbond Mrs 2 is between 1 nm and 1 mm, mi t preference between 10 nm and 100 ⁇ , with greater preference between 100 nm and 10 ⁇ , with the greatest preference between 1 ⁇ and 5 ⁇ , Die
• Temporary BOND 2 is patterned by methods known to those skilled in the art.
• a structured temporary boundary layer 2 with channels 3 is shown by way of example.
• These channels 3 for example, by known mask techniques, lithography, masking and subsequent etching with acids and / or alkalis and / or by appropriately suitable
• Temporärbond Faculty 2 by means of shadow masks during the deposition process.
• the shadow masks thereby mask areas where the material should not be deposited during the deposition process.
• the use of shadow masks saves a subsequent masking and etching of the temporary surface layer 2 applied over the entire area.
• the etching is carried out in particular with hydrofluoric acid (hydrogen fluoride, HF) in the liquid and / or vapor state.
• hydrofluoric acid hydrogen fluoride, HF
• vapor phase is the access through the channels 3 and / or through the existing pores particularly fast.
• acids which can be used according to the invention are sulfuric acid, hydrochloric acid, nitric acid, phosphoric acid, all organic acids.
• a known M ischung of several chemicals such as aqua regia, piranha (H2S O 4 H 2 0 2 ), a mixture of hydrofluoric acid and nitric acid.
• Basic substances for example KOH, TMAH (tetramethylammonium hydroxide) and / or EDP, also serve as etching media
• the etch rate of Si0 2 when attacked by a 44% KOH solution at about 85 is about 14 Angstroms / min.
• the etching rate of Si0 when attacked by a 25% TMAH solution at about 80 ° C is about 2 Angstroms / min.
• the etching rate of Si0 2 when attacked by an EDP solution at about 1 1 5 ° C is about 2 Angstrom / min.
• the solution used has a concentration greater than 20%, more preferably greater than 40%, more preferably greater than 60%, most preferably greater than 80%, most preferably greater than 99%.
• the etch temperature used in the present invention is greater than 25 ° C, preferably greater than 50 ° C, more preferably greater than 100 ° C, most preferably greater than 200 ° C, most preferably greater than 400 ° C.
• the surface 4o of a product wafer 4 can now be bonded to the surface 2o d Temporärbond Anlagen 2. Unlike bonding with t Adhesive, where polymers are regularly used, bonds here between the high temperature temporary temporary layer 2, preferably Si0 2 ⁇ , and the surface 4o of the product wafer 4. Those skilled in the art will be familiar with fusion bonding technologies and anodic bonding technologies. The fusion bond or the anodic bond is so strong that the back 4u can be processed.
• the fusion bond ideally takes place at room temperature without the action of force, ie in particular exclusively by simply contacting the
• the anodic bond is usually associated with a
• the product wafer 4 can again be released from the temporary boundary layer 2 by penetrating a chemical 6 through the channels 3 and dissolving the temporary boundary layer 2 or at least the interface between the surface 4o of the product wafer 4 and the surface 2o of the temporary boundary layer 2 weakens (Fig. I d to lf).
• the channels 3 serve mainly the better access of the chemical to the Temporärbond Mrs 2. The chemical dissolves the
• Temporärbond Faculty 2 allows the separation of the product wafer 4 from the carrier wafer. 1
• the carrier wafer 1 can be used again. If there are residues of the temporary boundary layer 2 on the carrier wafer 1, the carrier wafer 1 can be cleaned according to the invention.
• FIG. 2a-c is by a
• Coating process preferably a CVD coating process, the Temporärbond Mrs 2 'applied to the carrier wafer 1. If a CVD coating process is used, the deposited layer already has a correspondingly high porosity. If other coating processes are used, the invention requires a corresponding porosity known processes are generated. In this porosity different gases can be introduced or are already in the
• Coating process included By means of a fusion bonding process, the product wafer 4 is welded to the temporary boundary layer 2 '.
• the product wafer 3 can be processed accordingly on its rear side.
• Tk critical temperature
• This volume expansion leads to an at least predominant breaking of the temporary boundary layer 2 'and / or to a weakening of the interface between the surface 2o' of the temporary boundary layer 2 'and the surface 4o of the product substrate 4 and to the possibility of removing the product wafer 4 from the carrier wafer 1, more precisely of temporary layer 2 ⁇ to remove.
• Outgassing does not necessarily lead to complete delamination of the interface. It is sufficient according to the invention if the outgassing process leads to a weakening of the interface (temporary boundary layer 2 ') and by a later, in particular mechanical, separation process the two wafers 1, 4
• the critical temperature Tk can very well also lie in the temperature interval in which the product wafer 4 is processed, so that the outgassing takes place in particular during the processing of the product wafer 4.
• the bonding of the product substrate 4 to a carrier wafer 1 takes place by means of an anodic bonding method.
• the carrier substrate 1 is a glass substrate 1 and the temporary boundary layer 2, 2 ', 2 "consists at least predominantly,
• the carrier substrate 1 is a silicon substrate 1 and the temporary coloring layer 2, 2 ', 2 "consists at least predominantly, preferably completely, of glass
• the temporary boundary layer 2, 2', 2" can be pretreated the same as the SiO 2 layer the other invention

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• Chemical & Material Sciences (AREA)
• Engineering & Computer Science (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Materials Engineering (AREA)
• Metallurgy (AREA)
• Organic Chemistry (AREA)
• General Chemical & Material Sciences (AREA)
• Mechanical Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Inorganic Chemistry (AREA)
• Electrochemistry (AREA)
• Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
• Weting (AREA)
• Peptides Or Proteins (AREA)

Priority Applications (6)

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Publications (1)

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Citations (2)

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• 2012
  • 2012-12-21 DE DE102012112989.4A patent/DE102012112989A1/de not_active Ceased
• 2013
  • 2013-12-16 KR KR1020147027831A patent/KR20150097381A/ko not_active Withdrawn
  • 2013-12-16 WO PCT/EP2013/076629 patent/WO2014095668A1/de not_active Ceased
  • 2013-12-16 JP JP2015548392A patent/JP2016503961A/ja active Pending
  • 2013-12-16 US US14/388,107 patent/US20150047784A1/en not_active Abandoned
  • 2013-12-16 SG SG2014013056A patent/SG2014013056A/en unknown
  • 2013-12-16 AT ATA9019/2013A patent/AT516064B1/de active
  • 2013-12-16 CN CN201380018729.5A patent/CN104380457A/zh active Pending

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