WO2014091929A1 - SiC基板の製造方法 - Google Patents
SiC基板の製造方法 Download PDFInfo
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- WO2014091929A1 WO2014091929A1 PCT/JP2013/081897 JP2013081897W WO2014091929A1 WO 2014091929 A1 WO2014091929 A1 WO 2014091929A1 JP 2013081897 W JP2013081897 W JP 2013081897W WO 2014091929 A1 WO2014091929 A1 WO 2014091929A1
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- sic substrate
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- oxide film
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Definitions
- the present invention relates to a method for manufacturing a SiC substrate, and more particularly, to a method for manufacturing a SiC substrate, which includes a step of polishing and planarizing a surface of a SiC substrate or a SiC substrate having an epitaxial layer laminated on the surface side.
- Silicon carbide has characteristics such as a dielectric breakdown electric field that is an order of magnitude larger than silicon (Si), a band gap that is three times larger, and a thermal conductivity that is about three times higher. Applications to devices, high-frequency devices, high-temperature operating devices, etc. are expected. For this reason, in recent years, SiC substrates have been used for semiconductor device substrates.
- the SiC substrate described above is manufactured from, for example, an SiC bulk single crystal ingot produced by a sublimation method or the like, and is usually disk-shaped using a wire saw or the like after grinding the outer periphery of the ingot into a cylindrical shape. Obtained by slicing, chamfering the outer peripheral portion and finishing to a predetermined diameter. Furthermore, the surface of the disk-shaped SiC substrate is subjected to a grinding process by a mechanical grinding method to adjust the unevenness and parallelism, and then a mechanochemical polishing such as a CMP (Chemical Mechanical Polishing) method is performed. By applying to the surface, one or both sides are finished to a mirror surface. Such grinding and polishing of the SiC substrate is performed for the purpose of flattening the surface of the SiC substrate in addition to the removal of waviness and processing distortion generated by slicing.
- CMP Chemical Mechanical Polishing
- the above-described CMP method is a polishing method having both a chemical action and a mechanical action, it is possible to stably obtain a flat surface without damaging the SiC substrate. For this reason, the CMP method flattens the undulations on the surface of the SiC substrate or the unevenness caused by the wiring on the wafer in which the epitaxial layer is laminated on the surface of the SiC substrate in the manufacturing process of the SiC semiconductor device or the like. Widely adopted as a method.
- a wafer in which an SiC substrate is used is usually an SiC that becomes an active region of an SiC semiconductor device by chemical vapor deposition (CVD) on the SiC substrate obtained by the above procedure. It is manufactured by growing an epitaxial film.
- CVD chemical vapor deposition
- a SiC substrate sliced from a SiC single crystal ingot is used in a state in which unevenness and undulation are generated on the surface, the surface of the epitaxial layer formed on the surface of the SiC substrate is also uneven. Occurs.
- the surface of the SiC substrate is polished in advance by the CMP method, and also after the growth of the SiC epitaxial film, by the mechanical grinding method as described above.
- a process for flattening the substrate surface that is, the wafer surface is performed.
- an epitaxial layer is grown on the surface of the SiC substrate with waviness and processing strain remaining thereon, and a semiconductor element such as a transistor or a diode is formed on the epitaxial layer to manufacture a semiconductor device.
- a semiconductor element such as a transistor or a diode
- the planarization process of the surface of the SiC substrate as described above is a very important process.
- a mechanical polishing method such as lapping for removing the waviness and processing distortion on the surface of the SiC substrate. Polishing using a diamond having a diameter and grinding using a high-grinding stone of # 10000 or higher are effective. Further, as finishing processing of the SiC substrate surface before growing the SiC epitaxial film and finishing processing of the wafer after forming the SiC epitaxial film, the surface roughness Ra ⁇ 0.1 ⁇ m, so that polishing by the CMP method is performed. Processing is generally performed.
- SiC substrate 100 whose surface is ground by a mechanical grinding method is attached to a rotatable SiC substrate support 201 provided in CMP polishing machine 200. Then, the SiC substrate 100 is pressed against the polishing pad 202a attached to the surface of the rotating surface plate 202, and while supplying the slurry 204 from the slurry nozzle 203 to the interface between the polishing pad 202a and the SiC substrate 100, the SiC By rotating substrate support 201, polishing surface (surface) 100a of SiC substrate 100 is polished.
- a scratch flaw 300 occurs at the initial stage of polishing the SiC substrate 100 using the polishing process by the CMP method. This is because, in the initial stage of the CMP polishing process, the surface of the SiC substrate is scratched on the substrate surface by the operation of pressing the polishing surface 100a of the SiC substrate against the polishing pad 202a and the operation of rotating the SiC substrate 100 attached to the SiC substrate support 201. This is because the scratch 300 is likely to occur.
- the average particle size of the colloidal silica used as the slurry is generally about 0.2 to 0.5 ⁇ m, and the removal amount and the remaining scratches by the CMP polishing process. From the relationship with the scratch, the depth of the scratch scratch 300 is estimated to be approximately 0.5 ⁇ m or less.
- the scratch flaw 300 occurs in the CMP polishing process, as shown in FIG. 7, the scratch flaw 300 remains on the polishing surface 100a even after the SiC substrate 100 is removed from the SiC substrate support 201. Thus, there is a problem that the yield decreases.
- the improvement of the surface roughness which is the original purpose when polishing the SiC substrate 100 by the CMP method, can be achieved in a polishing time of about several tens of minutes.
- the polishing process by the CMP method when the scratches 300 as described above are generated, the scratches generated at the initial stage of the processing are removed even though the surface roughness has been improved. This requires additional processing.
- the polishing process by the CMP method has a lower processing rate than other methods, so when performing the additional processing as described above, a processing time for removing the scratches 300 is added in units of several hours. As a result, there arises a problem that the process time is prolonged.
- the substrate thickness adjustment before polishing on the rotary table is performed by using an SiC substrate.
- a technique for aligning the thickness of each SiC substrate without causing mechanical damage such as scratches on the substrate surface has been proposed.
- Patent Document 1 According to the technique described in Patent Document 1, by adopting the above method, the thickness of a plurality of substrates can be made uniform without causing mechanical damage to the substrate, so that polishing on each surface of a plurality of SiC substrates is performed. The effect that the variation in the amount can be suppressed is obtained.
- Patent Document 1 is a method for making a polishing amount of a plurality of SiC substrates constant by applying a liquid material to the surface opposite to the polishing surface of the SiC substrate and adjusting the substrate thickness.
- a liquid material to the surface opposite to the polishing surface of the SiC substrate and adjusting the substrate thickness.
- Patent Document 2 is a method for suppressing the occurrence of waviness when an SiC substrate is adsorbed and fixed.
- the technique on the polishing surface of the SiC substrate at the initial stage of CMP polishing processing is used. It is impossible to prevent the generation of scratches and the lengthening of the process time.
- the method of Patent Document 2 has a serious problem that damage such as scratches occurs on the surface of the substrate after performing double-sided processing of the SiC substrate.
- the present invention has been made in view of the above problems, and can prevent the occurrence of scratches on the surface of the SiC substrate and can planarize the SiC substrate without increasing the process time.
- An object of the present invention is to provide a method for manufacturing a SiC substrate that is excellent in productivity and yield.
- the inventors of the present invention when polishing the surface of the SiC substrate by the CMP method as described above, prevent the generation of scratches in the initial stage, and further, a process associated with additional processing for removing the scratches. In order to prevent lengthening of time, intensive studies were repeated. As a result, particularly immediately after the start of the CMP polishing process, scratch damage or the like is likely to occur on the surface of the substrate (wafer) due to the interaction between the operation of pressing the SiC substrate against the polishing pad and the operation of starting the rotation. I found a phenomenon.
- the surface of the SiC substrate pressed against the polishing pad at the start of the CMP polishing process is preliminarily applied. Therefore, it was considered effective to form an oxide film that functions as a protective film during polishing.
- the oxide film is pressed against the polishing pad in the initial stage of the CMP polishing process.
- the oxide film itself is removed by CMP polishing.
- the surface of the SiC substrate is exposed.
- the pressure and the rotational speed at which the SiC substrate is pressed against the polishing pad are already stable. It has been found that no additional process for removing scratches is required.
- the amount of polishing (polishing allowance) on the surface of the SiC substrate after the oxide film is removed becomes very small. The present inventors have found that the scratching due to processing does not occur and that the surface of the SiC substrate can be planarized with high productivity and yield, and the present invention has been completed.
- An SiC substrate manufacturing method including a step of flattening by polishing a surface of an SiC substrate, the oxide film forming step of forming an oxide film so as to cover the surface of the SiC substrate, and the SiC A planarization step of removing the oxide film by polishing the substrate from the oxide film side by a CMP (Chemical Mechanical Polishing) method and planarizing the surface of the SiC substrate by polishing the surface of the SiC substrate.
- a method of manufacturing a SiC substrate comprising: (2) The method for manufacturing an SiC substrate according to (1), wherein the oxide film forming step forms the oxide film with a thickness of 0.5 ⁇ m or more.
- the oxide film forming step is characterized in that a film formation rate when forming the oxide film on the surface of the SiC substrate is 0.15 ( ⁇ m / hr) or more (1) or The manufacturing method of the SiC substrate as described in (2).
- the planarization step is characterized in that when the oxide film and the SiC substrate are polished by a CMP method, a processing rate of the oxide film is larger than a processing rate of the SiC substrate.
- the manufacturing method of the SiC substrate as described in any one of (3).
- a processing rate ratio of the oxide film to the SiC substrate is 10 or more, and a processing rate of the SiC substrate is The method for producing an SiC substrate according to any one of (1) to (4), wherein the SiC substrate is 0.1 ( ⁇ m / hr) or more.
- the “SiC substrate” in the present invention includes both the SiC substrate itself or an SiC substrate (SiC epitaxial wafer) in which an epitaxial layer is laminated on at least one surface. That is, in the present invention, “the surface of the SiC substrate is flattened by polishing the surface” means that the surface of the SiC substrate is polished, or an SiC substrate (SiC epitaxial layer) on which an epitaxial layer is laminated. Any of the cases where the surface (epitaxial layer surface) of the wafer is polished is included.
- the SiC substrate manufacturing method of the present invention after forming an oxide film so as to cover the surface of the SiC substrate, the oxide film is removed by polishing the SiC substrate from the oxide film side by CMP.
- a method of flattening the surface of the SiC substrate by polishing the surface is employed.
- no scratches are generated on the surface of the SiC substrate in the initial stage of the CMP polishing process, and as a result, it is not necessary to add a process for removing the scratches associated with the generation of scratches.
- the SiC substrate can be flattened while greatly reducing the above. Therefore, it is possible to manufacture a SiC substrate having excellent surface characteristics with high productivity and yield.
- FIGS. 1 to 5 a preferred example of a method of manufacturing an SiC substrate to which the present invention is applied will be described in detail with reference to FIGS. 1 to 5 as appropriate.
- the drawings used in the following description may show the features that are enlarged for the sake of convenience in order to make the features easier to understand, and the dimensional ratios of the respective components may be different from the actual ones.
- the materials, dimensions, and the like exemplified in the following description are examples, and the present invention is not limited to them, and can be appropriately changed and implemented without changing the gist thereof.
- the SiC substrate which is an object to be polished, is a semiconductor substrate used for various semiconductor devices.
- Such an SiC substrate is formed by, for example, grinding an outer periphery of an SiC bulk single crystal ingot produced by a sublimation method or the like into a cylindrical shape, and then slicing it into a disk shape using a wire saw or the like. Can be manufactured by chamfering and finishing to a predetermined diameter.
- any polytype can be used, and 4H—SiC which is mainly used as a SiC bulk single crystal for producing a practical SiC device is used. Can be used.
- the surface of the SiC substrate that has been made into a disk shape by slicing is finally mirror-polished, but first, the surface is polished using a conventionally known mechanical polishing method to roughly roughen the unevenness of the polished surface. While removing, parallelism can be adjusted.
- the surface of the SiC substrate whose surface has been polished using a mechanical polishing method is mechanochemically polished by a CMP (Chemical Mechanical Polishing) method, so that the surface of the SiC substrate is mirror-finished. It becomes. At this time, only one surface of the SiC substrate may be polished to be a mirror surface, or may be a mirror surface with both surfaces polished.
- the SiC substrate has a mirror surface in which the surface of the substrate is flattened while the waviness and processing distortion generated when the above ingot is sliced are removed by polishing the surface.
- Such a SiC substrate whose surface is polished to a mirror surface becomes very excellent in flatness, and a wafer in which various epitaxial layers are formed on the SiC substrate has excellent crystal characteristics of each layer.
- the SiC substrate 1 is usually used as a SiC epitaxial wafer, on which an epitaxial layer that becomes an active region of a SiC device is formed by chemical vapor deposition (CVD) or the like.
- the “SiC substrate” in the present invention includes both the SiC substrate itself or an SiC substrate (SiC epitaxial wafer) in which an epitaxial layer is laminated on at least one surface. Therefore, in the polishing of the SiC substrate described in the present embodiment, the surface of the SiC substrate itself is polished, or the surface of the SiC substrate (SiC epitaxial wafer) on which the epitaxial layer is laminated, that is, the epitaxial layer surface is used. Both cases of polishing are included.
- the surface of the epitaxial layer generated during epitaxial growth is removed by removing irregularities such as minute steps, and further planarized, thereby forming an electronic device. It is possible to improve the quality of the interface with the oxide film to be formed and to obtain a high-quality device. In particular, when the epitaxial growth layer is thick, steps and the like are likely to occur on the surface, so it is more effective to employ the CMP polishing conditions in the manufacturing method according to the present invention.
- the surface polishing by the mechanical polishing method may be omitted when the surface of the epitaxial layer is polished by the CMP method. it can.
- the polishing apparatus 2 of the present embodiment is configured so that the SiC substrate support 21 to which the SiC substrate 1 is attached and the SiC substrate 1 are pressed against the surface 1a of the SiC substrate 1 while rotating.
- a polishing pad 22 a that is affixed to the surface of the rotating surface plate 22 and a slurry nozzle 23 that supplies the slurry 4 to the interface between the SiC substrate 1 and the polishing pad 22.
- the SiC substrate support portion 21 has a cylindrical shape, and the SiC substrate 1 is attached to the tip surface 21a made of a ceramic plate by a suction chuck mechanism (not shown). Further, the SiC substrate support portion 21 is configured to be rotatable in a predetermined direction (see an arrow A in FIG. 1) by a motor or the like (not shown) with the longitudinal axis direction as the center. Further, the SiC substrate support portion 21 can be moved up and down in FIGS. 1 and 2 by driving means (not shown), and the SiC substrate 1 attached to the tip surface 21a by suction is attached to the SiC substrate support portion. As 21 moves downward, it is configured to be pressed against the polishing pad 22.
- the method of attaching the SiC substrate 1 to the tip surface 21a of the SiC substrate support 21 is not limited to the above-described suction chuck mechanism, and for example, a method using tape or wax may be employed. Further, the number of SiC substrates 1 attached to the front end surface 21a may be one, or a plurality of SiC substrates 1 may be attached side by side.
- the polishing pad 22a is affixed to the surface of the rotating surface plate 22, and polishes the surface 1a of the SiC substrate 1.
- the polishing pad 22a for example, a nonwoven fabric or a suede material that has been conventionally used in this field can be used.
- the polishing pad 22a is also configured to be rotatable by a motor (not shown) or the like, similar to the SiC substrate support portion 21 described above.
- the polishing pad 22a itself rotates, and the surface of the SiC substrate 1 is polished and planarized by pressing the SiC substrate 1 attached to the SiC substrate support portion 21 against the polishing pad 22a while rotating. To do.
- a non-woven fabric such as SUBA400 manufactured by Nitta Haas can be used without any limitation.
- the slurry nozzle 23 supplies the slurry (abrasive) 4 to the interface between the SiC substrate 1 and the polishing pad 22a.
- the slurry passed from the slurry tank (not shown) to the slurry nozzle 23 by a pump means or the like, It is discharged from the front end port 23a.
- the slurry 4 is supplied from the tip port 23 a of the slurry nozzle 23 to the interface between the oxide film 10 formed on the surface 1 a of the SiC substrate 1 and the polishing pad 22 a.
- the polishing apparatus 2 having the above-described configuration will be described in detail later, but the polishing surface 10a of the oxide film 10 formed on the surface 1a of the SiC substrate 1 rotates with respect to the polishing pad 22a.
- the oxide film 10 is first polished from the polishing surface 10a side. When the oxide film 10 is almost removed by polishing, the surface 1a of the underlying SiC substrate 1 is exposed. In the present invention, the surface 1a of the SiC substrate 1 is polished following the polishing of the oxide film 10. As a result, the SiC substrate 1 can be planarized without causing scratches or the like on the surface 1a.
- the manufacturing method of the SiC substrate 1 according to the present invention is a method of planarizing the surface 1a of the SiC substrate 1 by polishing.
- a case where the surface 1a of the SiC substrate 1 on which no epitaxial layer is laminated is polished by using the polishing apparatus 2 having the above configuration will be described as an example.
- the manufacturing method according to the present invention includes an oxide film forming step of forming an oxide film 10 so as to cover the surface 1a of the SiC substrate 1, and polishing the SiC substrate 1 from the oxide film 10 side by a CMP method. And a planarizing step of planarizing the surface 1a by removing the oxide film 10 and polishing the surface 1a of the SiC substrate 1.
- a method including a rough polishing step of polishing the surface 1a of the SiC substrate 1 by a mechanical polishing method before the oxide film forming step can be adopted. The case where this rough polishing step is included will be described as an example.
- a method for growing a SiC bulk single crystal, an ingot grinding method, a slicing method, and the like are not particularly limited, and a conventionally known method can be employed.
- the surface of the SiC substrate before grinding and polishing has a thickness variation, undulation, and unevenness of about several tens of ⁇ m.
- the surface 1a of the SiC substrate 1 is polished by a mechanical polishing method.
- a mechanical polishing method such as lapping
- a polishing process for removing irregularities such as relatively large undulations and processing distortions on the surface 1a of the SiC substrate 1 is performed.
- the SiC substrate is held on the carrier plate by using a conventionally known lapping device, and the slurry is supplied and the surface plate is rotated while the carrier plate is moved in a planetary motion, so that one or both surfaces of the SiC substrate are attached.
- a method of lapping at the same time can be employed.
- the SiC substrate When polishing both surfaces of the SiC substrate, first, the SiC substrate is accommodated and held in a circular hole formed in the carrier plate. Next, the SiC substrate held on the carrier plate is sandwiched between upper and lower surface plates, and two sheets are supplied while a slurry containing an abrasive is supplied between the surface plate and the SiC substrate while a load is applied. The surface plates of the SiC substrate are alternately rotated in opposition to scrape the front and back of the SiC substrate. As a result, the surface of the SiC substrate is gradually polished, and the undulating convex portions remaining on the surface are removed in advance. As the processing abrasive at this time, for example, diamond abrasive is used.
- the surface opposite to the surface to be polished of the SiC substrate is bonded to the carrier plate with an adhesive or the like, and the carrier plate and the surface plate to which the SiC substrate is bonded are attached.
- the polishing is performed in the same manner as described above.
- the surface of the SiC substrate polished in such a rough polishing process is in a state in which irregularities such as large waviness and processing strain are removed.
- the processing pressure when mechanical polishing is performed by lapping that is, the load applied when polishing the SiC substrate is preferably in the range of 10 to 100 g / cm 2 .
- This processing pressure corresponds to the polishing rate, but by setting the range to the above, it is possible to achieve a polishing rate that can remove irregularities such as waviness and processing strain on the surface of the SiC substrate in a short time.
- the processing pressure applied to the SiC substrate exceeds the above range, a force is easily applied locally to the SiC substrate having a large thickness variation and waviness after slicing, and a crack or a crack occurs in the SiC substrate. there is a possibility.
- the diameter of the abrasive grain used in this case is 10 ⁇ m or less.
- a method of performing rough polishing by lapping as described above is given as an example.
- precise polishing using a polish is performed, and thereafter
- a method of performing ultra-precise polishing of the surface 1a of the SiC substrate 1 by performing an oxide film forming step and a flattening step, which will be described later may be employed.
- the rough polishing process as described above may be performed a plurality of times.
- oxide film 10 is formed so as to cover surface 1a of SiC substrate 1 from which relatively large waviness, processing strain, and the like have been removed in the rough polishing step of the above procedure.
- an oxide film 10 as shown in FIG. 1 is formed by depositing an oxide so as to cover surface 1a of SiC substrate 1 using a conventionally known film forming method. Thereby, the fine irregularities remaining on the surface 1 a of the SiC substrate 1 are also covered with the oxide film 10 while being covered.
- the oxide film 10 functions as a protective film in a flattening process described later, and is a film that is completely removed.
- the material of the oxide film 10 is not particularly limited, but it is preferable that the material be appropriately adopted in consideration of the processing rate of slurry (abrasive) used in the CMP polishing process in the flattening step described later.
- slurry abrasive
- colloidal silica it is preferable to use a silicon oxide film (SiO 2 film) that can obtain a processing rate 10 times or more that of SiC as the oxide film 10.
- oxide film materials other than SiO 2 can be employed in consideration of the film formation rate described below and the processing rate conditions by CMP polishing.
- the film forming rate when forming the oxide film 10 on the surface 1a of the SiC substrate 1 is preferably 0.15 ( ⁇ m / hr) or more from the viewpoint of shortening the processing (film forming) time. If the deposition rate of the oxide film is below the above, productivity may be reduced.
- the oxide film forming step it is preferable to form the oxide film 10 with a thickness of 0.5 ⁇ m or more.
- the polishing is started by pressing the SiC substrate 1 against the polishing pad 22 while rotating it.
- the scratch 30 (see FIG. 1) is generated in the oxide film 10
- the oxide film 10 is formed in the initial stage of polishing in which the polishing operation is not stable (rotation of the SiC substrate 1 shown in FIG. 1, rotation of the polishing pad 22, and the slurry 4 between the SiC substrate 1 and the polishing pad 22).
- the scratch 30 that is likely to be generated at a stage where supply or the like is not stable functions as a protective film that suppresses generation on the surface 1a of the SiC substrate 1.
- the method for forming the oxide film 10 is not particularly limited. However, when the oxide film 10 is formed by forming the above-mentioned SiO 2 , for example, it is preferable to use the P-CVD method. . This is because the P-CVD method can obtain a high film formation rate of about 5 ( ⁇ m / hr) depending on the film formation conditions, and is generally used in the device manufacturing process after the formation of the epitaxial layer. This is because the method is advantageous in that the manufacturing apparatus can be used as it is in the manufacturing process of the semiconductor device.
- the film formation rate in the RF sputtering method is about 0.2 ( ⁇ m / hr), which is a lower film formation rate than the P-CVD method. From the viewpoint of processing (film formation) time, it is considered that it can withstand practical use.
- the film thickness is saturated at 0.1 ⁇ m, and therefore it is too thin as an oxide film used in the present invention. There is a risk of scratching. Moreover, when forming a thermal oxide film, since the film formation rate is as low as 0.1 ( ⁇ m / hr) or less, the effect of shortening the processing time cannot be expected, which is not preferable.
- the polishing rate of the silicon nitride film is a fraction of the polishing rate of SiO 2 , which is not preferable from the viewpoint of productivity. Further, if the silicon nitride film is formed thick, cracks are likely to occur, and therefore, the variation in the polishing rate of the silicon nitride film on the surface 1a of the SiC substrate 1 increases, which is not preferable.
- the unevenness and the parallelism are adjusted in the rough polishing step, and the SiC substrate 1 on which the oxide film 10 is formed on the surface 1a is superposed from the oxide film 10 side by the CMP method.
- precise polishing mirror polishing
- the oxide film 10 is polished and removed, and the surface 1a of the SiC substrate 1 is polished to flatten the surface 1a.
- a suction chuck mechanism (not shown) or an attaching method using tape or wax is applied to the tip surface 21 a of the SiC substrate support 21 provided in the polishing apparatus 2.
- the SiC substrate 1 having the oxide film 10 laminated on the surface 1a is adsorbed and fixed in the direction facing the polishing pad 22 with the oxide film 10 side exposed.
- the polishing pad 22a is rotated at a predetermined rotational speed, and the slurry (polishing liquid) 4 is supplied from the slurry nozzle 23 onto the polishing pad 22a. Then, the SiC substrate support portion 21 to which the SiC substrate 1 is attached is moved downward, the polishing surface 10a of the oxide film 10 and the polishing pad 22a are brought into contact with each other, and the SiC substrate support portion 21 is rotated at a predetermined rotational speed. Then, polishing of the oxide film 10 is started.
- the thickness is set to 0.5 ⁇ m or more in the initial stage of the polishing process by the operation of pressing the SiC substrate 1 (oxide film 10) against the rotating polishing pad 22a or the operation of starting the rotation of the SiC substrate support 21.
- scratches 30 due to the abrasive contained in the slurry 4 for example, colloidal silica having an average secondary particle size of 0.2 to 0.5 ⁇ m are generated. Such scratches 30 are likely to occur immediately after the start of CMP polishing, and are less likely to newly occur after polishing progresses and CMP polishing is stabilized.
- the polishing is stable (rotation of the polishing cloth, rotation of the SiC substrate, supply of the slurry 4 between the SiC substrate and the polishing cloth, etc.
- the SiC substrate 1 is polished in a state where it is difficult for scratches to occur due to friction reduction due to the phenomenon.
- scratch scratch 30 occurs only in oxide film 10 formed on surface 1 a of SiC substrate 1, and scratch scratch 30 does not reach SiC substrate 1. Therefore, it is possible to suppress the generation of scratches on the surface 1a of the SiC substrate 1. Further, since the oxide film 10 itself is removed in the planarization step, there is no problem even if the scratch flaw 30 occurs in the oxide film 10.
- the polishing of the surface 1 a of the SiC substrate 1 exposed by removing the oxide film 10 is continued.
- the pressure and the rotational speed at which the SiC substrate 1 is pressed against the polishing pad 22a are already in a stable state, no scratches are generated on the SiC substrate.
- survived on the surface 1a of the SiC substrate 1 are planarized, and it grind
- the SiC substrate 1 can be polished under CMP conditions slower than the processing rate of the oxide film 10 made of a silicon oxide film as the processing rate (polishing rate) of the SiC substrate 1.
- the surface 1a of the SiC substrate 1 can be processed into a good smooth surface. Since the surface 1a of the SiC substrate 1 has relatively large irregularities such as waviness and processing strain removed in the rough polishing step and fine irregularities remain, the processing rate of the SiC substrate 1 with respect to the oxide film 10 can be reduced. Even when a slurry having a low ratio (a polishing liquid in which the SiC substrate 1 is hard to be polished) is used, the surface 1a of the SiC substrate 1 can be planarized and mirror-polished in a relatively short time. Further, when the surface of the epitaxial layer is polished by CMP, the size of the unevenness before polishing is small, and planarization is performed with a small amount of processing, so that the above CMP conditions are particularly preferable.
- a slurry having a low ratio a polishing liquid in which the SiC substrate 1 is hard to be polished
- the number of rotations of the polishing pad 22 is 30 to 70 rpm, and the rotation of the SiC substrate support 21 is performed.
- the polishing conditions can be a number of 30 to 70 rpm and a processing pressure (polishing load) of 100 to 1000 g / cm 2 .
- the slurry (abrasive material) 4 used in the planarization step is not particularly limited, but when the oxide film 10 and the surface 1a of the SiC substrate 1 are polished by the CMP method, the processing rate ratio of the oxide film 10 to the SiC substrate 1 is high. It is preferable that it is 10 or more. Furthermore, in addition to the above processing rate ratio, the processing rate of SiC substrate 1 is more preferably 0.1 ( ⁇ m / hr) or more. In the present embodiment, “the processing rate ratio of oxide film 10 to SiC substrate 1 is 10 or more” means that the processing (polishing) rate of oxide film 10 is 10 times or more the processing rate of SiC substrate 1. Say there is. “The processing rate ratio of the SiC substrate 1 to the oxide film 10 is high” means that the processing rate of the oxide film 10 is larger than the processing rate of the SiC substrate 1.
- the time required for polishing and removing the oxide film 10 can be shortened, so that the productivity of the SiC substrate 1 can be improved.
- the polishing amount (polishing allowance) of the SiC substrate 1 can be reduced. Since it is possible to reduce as much as possible, it is possible to obtain a flat surface 1a without generation of scratches without increasing the process time. Further, when the surface of the epitaxial layer is polished, a flat surface of the epitaxial layer can be obtained without generating scratches.
- a secondary particle having an average particle diameter of 0.2 to 0.5 ⁇ m formed by agglomerating the abrasive contained in the slurry 4 can be used.
- the oxide film 10 having a thickness of 0.5 ⁇ m or more is formed in the oxide film forming step, and then the slurry 4 in which the average particle diameter of the secondary particles of the abrasive is in the above range is formed.
- the oxide film 10 for polishing it occurs at the initial stage of the polishing process caused by the abrasive (the stage at which the rotating polishing pad 22a and the polishing surface 10a of the oxide film 10 come into contact with each other to start polishing).
- the easy scratch 30 can be prevented from reaching the surface 1 a of the SiC substrate 1.
- the specific slurry 4 for example, by mixing colloidal silica having an average secondary particle diameter of 0.2 to 0.5 ⁇ m, KOH, H 2 O 2 , pure water, etc., PH is increased.
- a mixed liquid made alkaline for example, PH is 11 or less
- the composition of KOH and H 2 O 2 may be adjusted.
- the processing rate of SiC substrate 1 is 0.1 ( ⁇ m / hr) or higher, so that the surface of SiC substrate 1 is 1a can be polished in a short time, and productivity is improved.
- the polishing operation is stopped when the surface 1a of the SiC substrate 1 is planarized and mirror-polished. Specifically, the SiC substrate support portion 21 is moved upward to be separated from the polishing pad 22a. Next, the SiC substrate support 21 and the surface 1 a of the SiC substrate 1 are cleaned using pure water while rotating the SiC substrate support 21.
- SiC substrate 1 having surface 1a flattened and mirror-polished can be manufactured.
- a semiconductor device can be formed by growing various epitaxial layers on the planarized surface 1a of the SiC substrate 1 using a conventionally known CVD method or the like.
- the surface of the device on which such an epitaxial layer or the like is formed can be polished by the same method as described above.
- the depth of scratches generated on the surface of the SiC substrate in the CMP polishing process is approximately 0.5 ⁇ m or less. Therefore, if the oxide film 10 is formed with a film thickness of 0.5 ⁇ m or more in the oxide film forming process prior to the planarization process using CMP polishing, scratch scratches 30 generated in the initial stage of the polishing process are caused by SiC. Since it does not reach the surface 1a of the substrate 1, it is possible to suppress the occurrence of scratches on the SiC substrate 1 itself. Further, in the conventional CMP polishing process, post-processing that is essential for removing scratches on the substrate surface can be omitted, so that the process time of about 15 minutes required for this post-processing can be shortened. is there.
- the film forming time for forming the oxide film 10 with a film thickness of 0.5 ⁇ m or more in the oxide film forming process, and the planarization process The total processing time for polishing and removing the oxide film 10 needs to be approximately 4 hours or less.
- the polishing conditions for polishing and removing the oxide film 10 in the planarization step are not the optimum conditions for polishing the oxide film, but are set to the same conditions as the polishing process of the SiC substrate 1 in terms of continuity of the process. Therefore, the polishing time of the oxide film 10 depends on the polishing conditions of the SiC substrate 1.
- the slurry 4 needs to be capable of processing both the oxide film 10 and the SiC substrate 1 and have a high processing rate of the oxide film 10.
- a processing rate (SiO 2 processing rate) 10 times or more that of SiC can be obtained by using a material containing colloidal silica or alumina as an abrasive.
- the SiO 2 processing rate is changed to about 100 of the SiC processing rate without substantially changing the SiC processing rate. Since it can be increased up to about twice, the processing time of the oxide film 10 is shortened.
- SiC substrate 3 inch, 4H-SiC-4 ° off substrate; one set of four (2) CMP polishing conditions Processing time: 15 minutes, 30 minutes, 1 hour, 3 hours, 5 hours; CMP slurry: colloidal silica + KOH + H 2 O 2 (pH: 9) C. CMP polishing load: 300 gf / cm 2 D. Plate rotation speed: 60rpm (3) Measurement conditions AFM measurement: Measured before and after CMP polishing. Confocal microscope: Counts only after polishing (cannot be evaluated prior to polishing due to surface roughness)
- the processing rate by CMP is extremely small, it is difficult to directly determine the processing rate from the change in the thickness of the SiC substrate, but when calculated from the change in the weight of the substrate, it is approximately 0.1 ( ⁇ m / hr). It can be seen that the polishing rate is about 0.5 ( ⁇ m) to completely remove the scratches. Also from this fact, scratching reaches the surface of the SiC substrate by setting the thickness of the oxide film 10 formed in the oxide film forming process to 0.5 ( ⁇ m) or more before performing the planarization process. It can be effectively suppressed, which is more preferable.
- oxide film 10 is formed so as to cover surface 1a of the SiC substrate 1, and thereafter oxide film 10 functions as a protective film when polishing surface 1a of SiC substrate 1 by CMP. .
- the scratch flaw 30 is generated on the SiC substrate 1. It can suppress reaching to the surface 1a. Accordingly, no scratches are generated on the surface 1a of the SiC substrate 1, and as a result, no additional process for removing the scratches associated with the generation of the scratches is required, so that the process time is greatly reduced.
- the planarization process of the SiC substrate can be performed. Therefore, it is possible to manufacture the SiC substrate 1 excellent in surface characteristics with high productivity and yield.
- oxide film 10 can be removed in a short time. Since flattening and mirror polishing can be performed in a state where the amount of polishing of the SiC substrate 1 is as small as possible, a flat surface 1a free from scratches can be obtained without increasing the process time. Further, when the surface of the epitaxial layer is polished, a flat surface of the epitaxial layer can be obtained without generating scratches.
- Example 1 In Example 1, first, lapping polishing was performed on the surface of a SiC substrate (3 inch, 4H—SiC-4 ° off substrate) using a diamond slurry having an average particle size of secondary particles of 0.25 ⁇ m. After that, an SiO 2 film is formed on the surface with a thickness of 0.5 ( ⁇ m), 1.0 ( ⁇ m), and 2.0 ( ⁇ m) by the P-CVD method.
- P-CVD plasma-organic acid
- CMP polishing is performed on each substrate using a slurry in which KOH and H 2 O 2 are added to colloidal silica having an average secondary particle size of 0.3 ( ⁇ m) and the pH is adjusted to 10. Performed for 0.5 hr.
- the conditions for CMP polishing were as follows. (1) Polishing load: 500 (gf / cm 2 ) (2) Surface plate rotation speed: 60 rpm (3) SiC substrate processing rate: 0.1 ( ⁇ m / hr) ⁇ Density: Based on weight conversion from 3.2 (g / cc). ⁇
- Comparative Examples 1-1-1 to 1-4, 1-2-1 to 4, 1-3-1 to 4, SiC substrates without a SiO 2 film after lapping polishing using a diamond slurry Each of the four sheets was subjected to CMP polishing under the same processing conditions as in the above-described example of the present invention. The processing times at this time were 0.5 hr, 3 and 5 hr, respectively. Further, as Reference Examples 1-4-1 to 4, after forming a SiO 2 film with a film thickness of 0.3 ( ⁇ m) on the surface of the SiC substrate under the same P-CVD conditions as in the above-described example of the present invention, CMP polishing was performed for 0.5 hr.
- the entire surface of the SiC substrate is inspected for scratches (counting the number) using a confocal microscope, and the surface roughness Ra (nm) is measured by AFM measurement. Measurement (field of view: 5 ⁇ m square (square: four directions)) was performed. Further, the difference between the weight of the SiC substrate after lapping polishing using diamond slurry and the weight of the SiC substrate after CMP polishing was calculated, and the removal amount (removed thickness) of the SiC substrate by CMP polishing was calculated. . Table 1 below shows a list of manufacturing conditions and evaluation results of the inventive examples and comparative examples in Example 1.
- Comparative Examples 1-1-1 to 1-2-3 in which the CMP polishing process was performed without forming the SiO 2 film on the surface of the SiC substrate, scratches were detected. could not be polished to an ideal mirror surface.
- Comparative Example 1-2-4 although no scratch was found, the amount of removal of the SiC substrate was large and the productivity was not high due to the long CMP polishing time.
- Comparative Examples 1-3-1 to 4 are conventional processing methods, and although scratch-free has been achieved, additional polishing processing is performed to remove scratches generated in the initial stage of CMP polishing processing. Thus, it can be seen that the CMP polishing time is as long as 5 hours, and the productivity is very poor.
- the thickness of the SiO 2 film formed on the surface of the SiC substrate is 0.3 ( ⁇ m), which is thinner than the above-described example of the present invention.
- Example 2 In Example 2, the surface of a SiC substrate (3 inch, 4H—SiC-4 ° off substrate) was lapped using a diamond slurry having an average secondary particle size of 0.25 ⁇ m, An SiO 2 film having a film thickness of 0.5 ( ⁇ m) is formed on the substrate surface by P-CVD under the same conditions as in Inventive Example 1-1-1 to Inventive Example 1 of Example 1, and the Inventive Example 2-1-1 to 4.
- an SiO 2 film of 0.5 ( ⁇ m) is formed on the surface of the SiC substrate under the same conditions as in the invention example 2-1-1 except that an RF sputtering method is used instead of the P-CVD method.
- the film thicknesses were determined as Invention Examples 2-2-1 to 4-1.
- the RF sputtering conditions for forming the SiO 2 film were the following conditions. (1) Ar gas pressure; 0.8 (Pa) (2) RF power: 100 (W) (3) Target; ⁇ 180mm (SiO 2 ) (4) Deposition rate: 0.2 ( ⁇ m / hr)
- each substrate was prepared using a slurry prepared by adding KOH and H 2 O 2 to colloidal silica having an average secondary particle size of 0.3 ( ⁇ m) and adjusting the pH to 10.
- the CMP polishing process was performed for 0.5 hr.
- the conditions for CMP polishing were as follows. (1) Polishing load: 500 (gf / cm 2 ) (2) Surface plate rotation speed: 60 rpm (3) SiC substrate processing rate: 0.1 ( ⁇ m / hr) ⁇ Density: Based on weight conversion from 3.2 (g / cc). ⁇
- the entire surface of the SiC substrate is inspected for scratches (counting the number) using a confocal microscope, and the surface roughness Ra (nm) is measured by AFM measurement. Measurement (field of view: 5 ⁇ m (square: four directions)) was performed. Further, the difference between the weight of the SiC substrate after lapping polishing using diamond slurry and the weight of the SiC substrate after CMP polishing was calculated, and the removal amount (removed thickness) of the SiC substrate by CMP polishing was calculated. . Table 2 below shows a list of manufacturing conditions and evaluation results of the inventive examples and the reference examples in Example 2.
- the deposition rate of the SiO 2 film is 0.15 ( ⁇ m). It can be seen that the above is more preferable.
- Example 3 In Example 3, after lapping the surface of a SiC substrate (3 inch, 4H—SiC-4 ° off substrate) with a diamond slurry having an average particle size of secondary particles of 0.25 ⁇ m, An SiO 2 film having a thickness of 0.5 ( ⁇ m) is formed on the surface of the substrate by P-CVD under the same conditions as in Invention Examples 1-1 to 4 in Example 1, and Example 3- Examples 1-1 to 4 and Invention Examples 3-2-1 to 4 were used.
- a SiO 2 film was formed on the surface of the substrate by a P-CVD method to 0.5 ( ⁇ m). ), And Reference Examples 3-1-1 to 4 were used. And as a thriller, except that the pH adjuster and H 2 O 2 were added to colloidal silica having an average particle size of secondary particles of 0.3 ( ⁇ m) and the pH was adjusted to 2: Under the same conditions as in the example of the present invention, CMP polishing of the surface of the SiC substrate was performed for 0.5 hr. At this time, the processing rate of the SiC substrate was 0.15 ( ⁇ m / hr) in terms of weight from density: 3.2 (g / cc). The processing rate of the SiO 2 film was 1.2 ( ⁇ m / hr).
- the entire surface of the SiC substrate is inspected for scratches (counting the number) using a confocal microscope, and the surface roughness Ra (nm) is measured by AFM measurement. Measurement (field of view: 5 ⁇ m square (square: four directions)) was performed. Further, the difference between the weight of the SiC substrate after lapping polishing using diamond slurry and the weight of the SiC substrate after CMP polishing was calculated, and the removal amount (removed thickness) of the SiC substrate by CMP polishing was calculated. . Table 3 below shows a list of production conditions and evaluation results for the inventive examples and reference examples in Example 3.
- Example 3 From the results of Example 3, in order to make the surface of the SiC substrate flat and ideal mirror surface, and to shorten the processing time and increase the productivity, in addition to the high processing rate of the SiC substrate, the SiO 2 film It can be seen that a higher processing rate is more preferable.
- the method for producing an SiC substrate according to the present invention can produce an SiC substrate having excellent surface characteristics with good productivity and yield, and is therefore suitable for producing an SiC substrate used for a power device, a high-frequency device, a high-temperature operation device, or the like. .
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Abstract
Description
本出願は、2012年12月12日に日本に出願された特願2012-271578号に基づき、優先権を主張し、その内容をここに援用する。
図6に示すように、スライス後、表面が機械的研削法で研削されたSiC基板100は、CMP研磨機200に備えられる回転可能なSiC基板支持部201に取り付けられる。そして、SiC基板100を、回転定盤202の表面に貼り付けられた研磨パッド202aに押し当てるとともに、研磨パッド202aとSiC基板100との界面に、スラリー204をスラリーノズル203から供給しながら、SiC基板支持部201を回転させることにより、SiC基板100の研磨面(表面)100aを研磨する。
さらに、CMP研磨加工において、酸化膜に対する選択性の高いスラリーを用いた場合には、酸化膜が除去された後の、SiC基板の表面の研磨量(研磨代)は微量となるので、CMP研磨加工によるスクラッチ傷が発生することが無く、高い生産性及び歩留まりでSiC基板表面の平坦化処理が可能となることを見出し、本発明を完成させた。
(1) SiC基板の表面を研磨することによって平坦化する工程を有するSiC基板の製造方法であって、前記SiC基板の表面を覆うように酸化膜を成膜する酸化膜形成工程と、前記SiC基板に対して、CMP(Chemical Mechanical Polishing)法によって前記酸化膜側から研磨を施すことで該酸化膜を除去するとともに、前記SiC基板の表面を研磨することで該表面を平坦化する平坦化工程と、を少なくとも具備することを特徴とするSiC基板の製造方法。
(2) 前記酸化膜形成工程は、前記酸化膜を0.5μm以上の膜厚で成膜すること、を特徴とする(1)に記載のSiC基板の製造方法。
(3) 前記酸化膜形成工程は、前記SiC基板の表面に前記酸化膜を成膜する際の成膜レートが0.15(μm/hr)以上であること、を特徴とする(1)または(2)に記載のSiC基板の製造方法。
(4) 前記平坦化工程は、CMP法によって前記酸化膜及び前記SiC基板を研磨する際、前記酸化膜の加工レートが、前記SiC基板の加工レートよりも大きいことを特徴とする(1)~(3)の何れか一項に記載のSiC基板の製造方法。
(5) 前記平坦化工程は、CMP法によって前記酸化膜及び前記SiC基板を研磨する際、前記SiC基板に対する前記酸化膜の加工レート比が10以上であり、且つ、前記SiC基板の加工レートが0.1(μm/hr)以上であること、を特徴とする(1)~(4)の何れか一項に記載のSiC基板の製造方法。
(6) 前記SiC基板が、さらに、少なくとも一方の面にエピタキシャル層が積層されたSiC基板であることを特徴とする(1)~(5)の何れか一項に記載のSiC基板の製造方法。
(7) 前記酸化膜形成工程の前に、さらに、SiC基板の表面を機械式研磨法によって研磨する粗研磨工程を含むことを特徴とする(1)~(5)の何れか一項に記載のSiC基板の製造方法。
なお、以下の説明で用いる図面は、特徴をわかりやすくするために便宜上特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率などは実際とは異なっていることがある。
また、以下の説明において例示される材料、寸法等は一例であって、本発明はそれらに限定されるものではなく、その要旨を変更しない範囲で適宜変更して実施することが可能である。
本発明に係る製造方法における、被研磨物であるSiC基板は、各種の半導体デバイスに用いられる半導体基板である。このようなSiC基板は、例えば、昇華法等によって作製したSiCバルク単結晶のインゴットの外周を研削して円柱状に加工した後、ワイヤーソー等を用いて円板状にスライス加工し、外周部を面取りして所定の直径に仕上げることで製造できる。この際のSiCバルク単結晶としては、何れのポリタイプのものであっても用いることができ、実用的なSiCデバイスを作製するためのSiCバルク単結晶として主に採用されている4H-SiCを用いることができる。
以下に、本実施形態で説明するSiC基板の製造方法で用いる、CMP研磨加工を行うための研磨装置の一例について説明する。
図1、2に示すように、本実施形態の研磨装置2は、SiC基板1が取り付けられるSiC基板支持部21と、SiC基板1が回転しながら押し当てられることでSiC基板1の表面1aを研磨する、回転定盤22の表面に貼り付けられた研磨パッド22aと、SiC基板1と研磨パッド22との界面にスラリー4を供給するスラリーノズル23と、から概略構成されている。
本発明に係るSiC基板1の製造方法は、SiC基板1の表面1aを研磨することによって平坦化する方法である。また、本発明では、少なくとも一方の表面に図示略のエピタキシャル層が積層されたSiC基板の表面を研磨することによって平坦化することも可能である。以下の説明においては、上記構成の研磨装置2を用いて、エピタキシャル層が積層されていないSiC基板1の表面1aを研磨する場合を例に挙げて説明する。
本実施形態においては、まず、被研磨物であるSiC基板を得るにあたり、SiCバルク単結晶のインゴットを準備し、このインゴットの外周を研削して、円柱状のインゴットに加工する。その後、ワイヤーソー等により、インゴットを円板状にスライス加工し、さらに、その外周部を面取りすることで、所定の直径を有するSiC基板1に仕上げる。
なお、通常、研削、研磨を施す前のSiC基板の表面には、数10μm程度の厚みのばらつきやうねり、凹凸が生じた状態となっている。
粗研磨工程においては、SiC基板1の表面1aを、機械式研磨法によって研磨する。
具体的には、詳細な図示を省略するが、例えば、ラップ研磨等の機械式研磨法により、SiC基板1の表面1aにおける、比較的大きなうねりや加工歪等の凹凸を除去する研磨処理を行う。この際、従来公知のラップ研磨装置を用いて、キャリアプレートにSiC基板を保持させ、スラリーを供給するとともに、キャリアプレートを遊星運動させながら定盤を回転させることにより、SiC基板の片面あるいは両面を同時にラップ研磨する方法を採用することができる。
次いで、キャリアプレートに保持されたSiC基板を、上下に配置された定盤で挟み込み、荷重をかけた状態で、定盤とSiC基板との間に研磨剤を含むスラリーを供給しながら、2枚の定盤を交互に対向して回転させ、SiC基板の表裏を削り取る。これにより、SiC基板の表面が次第に研磨され、表面に残留したうねりの凸部が先行して除去される。この際の加工砥粒としては、例えば、ダイヤモンド砥粒等を用いる。また、SiC基板の片面のみを研磨する場合には、SiC基板の研磨する表面とは反対側の面をキャリアプレートに接着材等で貼り付け、SiC基板を貼り付けたキャリアプレートと定盤とを対向させて、上記同様の研磨を行う。
このような粗研磨工程で研磨されたSiC基板の表面は、大きなうねりや加工歪等の凹凸が除去された状態となる。
また、この際に用いる砥粒の粒径は、直径が10μm以下であることが好ましい。
あるいは、上記のラップ研磨において、二次粒子の平均粒径が0.25μm(250nm)程度の、ポリッシュにおいても用いられる細やかなダイヤモンドスラリーを用い、精密な研磨を行うことも可能である。
また、上述のような粗研磨工程を、複数回で行っても良い。
次に、酸化膜形成工程においては、上記手順の粗研磨工程において、比較的大きなうねりや加工歪等が除去されたSiC基板1の表面1aを覆うように酸化膜10を形成する。
具体的には、従来公知の成膜方法を用いて、SiC基板1の表面1aを覆うように酸化物を堆積させることにより、図1中に示すような酸化膜10を形成する。これにより、SiC基板1の表面1aに残存した微細な凹凸も、酸化膜10によって埋め込まれながら覆われた状態となる。
この酸化膜10は、後述する平坦化工程において保護膜として機能し、完全に除去される膜である。
このように、酸化膜10の膜厚を0.5μm以上とすることにより、後述の平坦化工程において、SiC基板1を回転させながら研磨パッド22に押し当てることで研磨が開始される初期段階で、スクラッチ30(図1参照)が酸化膜10内に生じる一方、このスクラッチ30がSiC基板1に到達するのを抑制できる効果が確実に得られる。即ち、酸化膜10は、研磨動作が安定していない研磨の初期段階(図1に示すSiC基板1の回転、研磨パッド22の回転、SiC基板1と研磨パッド22との間へのスラリー4の供給等が安定していない段階)に発生しやすいスクラッチ30が、SiC基板1の表面1aに発生するのを抑制する保護膜として機能する。
また、シリコン窒化膜は、厚く成膜すると割れが発生しやすくなることから、SiC基板1の表面1a上におけるシリコン窒化膜の研磨レートのばらつきが大きくなるため、好ましくない。
次に、平坦化工程においては、上記粗研磨工程において凹凸及び平行度が整えられ、さらに表面1a上に酸化膜10が形成されたSiC基板1に対して、CMP法によって酸化膜10側から超精密研磨(鏡面研磨)を施すことで、酸化膜10を研磨して除去するとともに、SiC基板1の表面1aを研磨することにより、この表面1aを平坦化する。
この際のSiC基板1の加工レート(研磨速度)としては、シリコン酸化膜からなる酸化膜10の加工レートよりも遅いCMP条件として、SiC基板1を研磨することができる。これにより、SiC基板1の表面1aの微細な凹凸を選択的に研磨することが可能となるので、SiC基板1の表面1aを、良好な平滑面に加工することができる。SiC基板1の表面1aは、上記の粗研磨工程において比較的大きなうねりや加工歪等の凹凸が除去され、微細な凹凸等が残存している程度なので、酸化膜10に対するSiC基板1の加工レート比が低いスラリー(SiC基板1が研磨されにくい研磨液)を用いた場合でも、比較的短時間で、SiC基板1の表面1a平坦化、鏡面研磨することが可能となる。また、エピタキシャル層の表面をCMP研磨する場合には、研磨前の凹凸の大きさが小さく、少ない加工量で平坦化を行うため、上記のようなCMP条件が特に好ましい。
なお、本実施形態において、「SiC基板1に対する酸化膜10の加工レート比が10以上である」とは、酸化膜10の加工(研磨)レートが、SiC基板1の加工レートの10倍以上であることを言う。また、「酸化膜10に対するSiC基板1の加工レート比が高い」とは、酸化膜10の加工レートが、SiC基板1の加工レートよりも大きいことを言う。
上述のように、まず、酸化膜形成工程において膜厚が0.5μm以上とされた酸化膜10を形成し、その後、研磨剤の二次粒子の平均粒子径が上記範囲とされたスラリー4を用いて酸化膜10を研磨することにより、研磨剤に起因する研磨加工の初期段階(回転する研磨パッド22aと酸化膜10の研磨面10aとが接触して研磨が開始される段階)に発生しやすいスクラッチ30が、SiC基板1の表面1aに到達するのを抑制できる。
なお、酸化膜10に対するSiC基板1の加工レート比を高くするためには、KOHとH2O2との配合を調整するとよい。
次いで、SiC基板支持部21を回転させながら、純水を用いて、SiC基板支持部21、SiC基板1の表面1aを洗浄する。
以上の工程により、表面1aが平坦化、鏡面研磨されたSiC基板1を製造することができる。
本実験においては、平均粒径:0.25μmのダイヤモンドスラリーを用いて、ラップ研磨により粗研磨工程を施したSiC基板に対して、以下に示す条件でCMP研磨加工を行った。そして、CMP研磨加工後のSiC基板の表面粗さRa(nm)を、AFM(原子間力顕微鏡法)により、5μm□(スクエア:四方))視野で測定するとともに、SiC基板表面に生じたスクラッチ傷の本数を、コンフォーカル式顕微鏡観察によってカウントした。そして、CMP加工時間(hr)と表面粗さRa(nm)との関係を図4のグラフに示すとともに、CMP加工時間とスクラッチ傷の本数との関係を図5のグラフに示した。
なお、図4、5のグラフ中に示したCMP加工時間に関し、スクラッチ傷が加工初期段階で発生することを考慮して、連続運転により実験を行った。
(2)CMP研磨加工条件
A.加工時間:15分、30分、1時間、3時間、5時間;各1組
B.CMPスラリー:コロイダルシリカ+KOH+H2O2(pH:9)
C.CMP研磨荷重:300gf/cm2
D.定盤回転数:60rpm
(3)測定条件
A.AFM測定:CMP研磨加工の前後に測定
B.コンフォーカル式顕微鏡:研磨加工後のみカウント(研磨加工前は表面荒れによるノイズのため評価不可)
また、図5のグラフに示すように、CMP研磨加工の時間が経過するとともにスクラッチ傷の本数が減少して行き、5hrでスクラッチ傷がほぼ消滅していることがわかる。
本発明のSiC基板の製造方法によれば、SiC基板1の表面1aを覆うように酸化膜10を成膜した後、SiC基板1に対してCMP法によって酸化膜10側から研磨を施すことで酸化膜10を除去するとともに、さらに、SiC基板1の表面1aを研磨することでこの表面1aを平坦化する方法を採用している。このように、まず、SiC基板1の表面1aを覆うように酸化膜10を形成することにより、その後、CMP法によってSiC基板1の表面1aを研磨する際、酸化膜10が保護膜として機能する。これにより、互いに回転する研磨パッド22aと酸化膜10とが接触するCMP研磨加工の初期段階において、酸化膜10にスクラッチ傷30が発生した場合であっても、このスクラッチ傷30がSiC基板1の表面1aにまで到達するのを抑制できる。従って、SiC基板1の表面1aにスクラッチ傷が発生することがなく、ひいては、スクラッチ傷の発生に伴う、このスクラッチ傷を除去するための工程の追加が不要となるので、工程時間を大幅に短縮しながらSiC基板の平坦化処理を行うことができる。従って、表面特性に優れたSiC基板1を、生産性及び歩留まり良く製造することが可能となる。
本実施例においては、酸化膜の膜厚とCMP研磨加工時間との、研磨後のスクラッチ傷の数の関係の調査(実施例1)、各種の酸化物成膜方法におけるCMP研磨加工時間と研磨後のスクラッチ傷との関係(実施例2)、CMPスラリーとCMP研磨加工量(除去量)との関係(実施例3)の各々を調査した。
実施例1においては、まず、SiC基板(3インチ、4H-SiC-4°off基板)の表面に、二次粒子の平均粒径が0.25μmのダイヤモンドスラリーを用いてラップ式研磨を施した後、その表面に、P-CVD法により、SiO2膜を、0.5(μm)、1.0(μm)、2.0(μm)の各膜厚で形成し、これらの各4枚を、本発明例1-1-1~4、1-2-1~4、 1-3-1~4とした。
SiO2膜を形成する際のP-CVDの条件は、以下の各条件とした。
(1)チャンバ内圧力;100(Pa)
(2)チャンバ内温度;400℃
(3)流通ガス;SiH4:N2O=20:300(sccm)
(4)RFパワー;100(W)
(5)成膜レート;6(μm/hr)
CMP研磨加工の条件は、以下の各条件とした。
(1)研磨荷重;500(gf/cm2)
(2)定盤回転数;60rpm
(3)SiC基板加工レート;0.1(μm/hr){密度:3.2(g/cc)からの重量換算による。}
また、参考例1-4-1~4として、SiC基板の表面に、SiO2膜を0.3(μm)の膜厚で、上記本発明例と同様のP-CVD条件で形成した後、CMP研磨加工を0.5hr行った。
また、ダイヤモンドスラリーを用いたラップ式研磨後のSiC基板の重量と、CMP研磨処理後のSiC基板の重量との差を求め、CMP研磨処理によるSiC基板の除去量(除去厚さ)を算出した。
実施例1における本発明例及び比較例の各々の製造条件並びに評価結果の一覧を下記表1に示す。
また、比較例1-2-4では、スクラッチ傷の発生は確認されなかったものの、CMP研磨加工時間が長いことから、SiC基板の除去量が多く、生産性も高くない。
また、比較例1-3-1~4は、従来の加工方法であり、スクラッチフリーは達成しているものの、CMP研磨加工の初期段階で発生したスクラッチ傷を除去するための追加研磨加工を行っていることから、CMP研磨加工時間が5時間と長く、生産性が非常に劣っていることがわかる。
一方、本発明例においては、SiO2膜の成膜時間とCMP研磨加工時間とを合わせても、合計で1時間以内であり、仮に、SiO2膜の成膜前後の作業に多少の時間を要したとしても、従来の方法に較べて大幅な工程時間の短縮が可能になることが明らかである。
実施例2においては、SiC基板(3インチ、4H-SiC-4°off基板)の表面に、二次粒子の平均粒径が0.25μmのダイヤモンドスラリーを用いてラップ式研磨を施した後、実施例1の本発明例1-1-1~4と同様の条件で、基板表面に、P-CVD法により、SiO2膜を0.5(μm)の膜厚で形成し、本発明例2-1-1~4とした。
SiO2膜を形成する際のRFスパッタリング条件は、以下の各条件とした。
(1)Arガス圧力;0.8(Pa)
(2)RFパワー;100(W)
(3)ターゲット;φ180mm(SiO2)
(4)成膜レート;0.2(μm/hr)
CMP研磨加工の条件は、以下の各条件とした。
(1)研磨荷重;500(gf/cm2)
(2)定盤回転数;60rpm
(3)SiC基板加工レート;0.1(μm/hr){密度:3.2(g/cc)からの重量換算による。}
また、ダイヤモンドスラリーを用いたラップ式研磨後のSiC基板の重量と、CMP研磨処理後のSiC基板の重量との差を求め、CMP研磨処理によるSiC基板の除去量(除去厚さ)を算出した。
実施例2における本発明例及び参考例の各々の製造条件並びに評価結果の一覧を下記表2に示す。
実施例3においては、SiC基板(3インチ、4H-SiC-4°off基板)の表面に、二次粒子の平均粒径が0.25μmのダイヤモンドスラリーを用いてラップ式研磨を施した後、実施例1の本発明例1-1~4と同様の条件で、基板表面に、P-CVD法により、SiO2膜を0.5(μm)の膜厚で形成し、本発明例3-1-1~4、本発明例3-2-1~4とした。
CMP研磨加工の条件は、以下の各条件とした。
(1)研磨荷重;500(gf/cm2)
(2)定盤回転数;60rpm
(3)SiC基板加工レート;{密度:3.2(g/cc)からの重量換算による。}
pH:10の場合;0.1(μm/hr)
pH:12の場合、0.13(μm/hr)
(4)SiO2膜の加工レート;10(μm/hr){pH:10、pH:12とも。}
そして、スリラーとして、二次粒子の平均粒径が0.3(μm)のコロイダルシリカにpH調整剤及びH2O2を添加し、pH:2に調整したものを用いた点以外は、上記本発明例と同様の条件で、SiC基板の表面のCMP研磨加工を0.5hrで行った。
この際、SiC基板の加工レートは、密度:3.2(g/cc)からの重量換算により、0.15(μm/hr)であった。
また、SiO2膜の加工レートは、1.2(μm/hr)であった。
また、ダイヤモンドスラリーを用いたラップ式研磨後のSiC基板の重量と、CMP研磨処理後のSiC基板の重量との差を求め、CMP研磨処理によるSiC基板の除去量(除去厚さ)を算出した。
実施例3における本発明例及び参考例の各々の製造条件並びに評価結果の一覧を下記表3に示す。
1a…表面、
10…酸化膜、
10a…研磨面、
30…スクラッチ傷、
2…製造装置、
21…SiC基板支持部、
21a…先端面、
22…回転定盤、
22a…研磨パッド、
23…スラリーノズル、
23a…先端口、
4…スラリー
Claims (7)
- SiC基板の表面を研磨することによって平坦化する工程を有するSiC基板の製造方法であって、
前記SiC基板の表面を覆うように酸化膜を成膜する酸化膜形成工程と、
前記SiC基板に対して、CMP(Chemical Mechanical Polishing)法によって前記酸化膜側から研磨を施すことで該酸化膜を除去するとともに、前記SiC基板の表面を研磨することで該表面を平坦化する平坦化工程と、
を少なくとも具備することを特徴とするSiC基板の製造方法。 - 前記酸化膜形成工程は、前記酸化膜を0.5μm以上の膜厚で成膜すること、を特徴とする請求項1に記載のSiC基板の製造方法。
- 前記酸化膜形成工程は、前記SiC基板の表面に前記酸化膜を成膜する際の成膜レートが0.15(μm/hr)以上であること、を特徴とする請求項1に記載のSiC基板の製造方法。
- 前記平坦化工程は、CMP法によって前記酸化膜及び前記SiC基板を研磨する際、前記酸化膜の加工レートが、前記SiC基板の加工レートよりも大きいことを特徴とする請求項1に記載のSiC基板の製造方法。
- 前記平坦化工程は、CMP法によって前記酸化膜及び前記SiC基板を研磨する際、前記SiC基板に対する前記酸化膜の加工レート比が10以上であり、且つ、前記SiC基板の加工レートが0.1(μm/hr)以上であること、を特徴とする請求項4に記載のSiC基板の製造方法。
- 前記SiC基板が、さらに、少なくとも一方の面にエピタキシャル層が積層されたSiC基板であることを特徴とする請求項1に記載のSiC基板の製造方法。
- 前記酸化膜形成工程の前に、さらに、SiC基板の表面を機械式研磨法によって研磨する粗研磨工程を含むことを特徴とする請求項1に記載のSiC基板の製造方法。
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JP2014116553A (ja) | 2014-06-26 |
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US9502230B2 (en) | 2016-11-22 |
US20150303050A1 (en) | 2015-10-22 |
JP6106419B2 (ja) | 2017-03-29 |
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TWI562219B (en) | 2016-12-11 |
KR20150080547A (ko) | 2015-07-09 |
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