TW200908120A - Manufacturing method of semiconductor device - Google Patents

Abstract

To provide a planarization method which suppresses defects on a surface of a polished film and can control a thickness of the polished film, and to provide a manufacturing method of a semiconductor device using such the planarization method.An interlayer insulating film 3 is formed on a semiconductor substrate 1 formed with a semiconductor element 2. When this takes place, a projected part 4 having a higher position than a periphery and a non-projected part 5 having a lower position than the projected part 4 exist on a surface of the formed interlayer insulating film 3. For such the interlayer insulating film 3, first, a first polishing processing is conducted by use of abrasive grains having non-Prestonian characteristics to planarize the projected part 4. Thereafter, a second polishing processing in which a polishing pressure is set to 1.5 times or more is executed on the surface of the interlayer insulating film 3.; Thus, the number of defects remaining on the surface of the interlayer insulating film 3 after polishing can be suppressed, and further a control of a film thickness of the interlayer insulating film 3 which is desired to remain is facilitated.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and more particularly to a planarization method for planarizing a surface after film formation. [Prior Art]

With the high integration of the semiconductor integrated circuit device, it is important to form a fine pattern with high precision during the manufacturing process, and to flatten the surface of the substrate uniformly. As such a flattening technique, a CMP (Chemical Mechanical Grinding) method in which a polishing liquid (slurry) is pressed against a polishing pad and rubbed on a substrate is widely used. When flattening by the CMP method is required, when a particularly high flatness is required, for example, when an element separation region is formed by STI (Shallow Trench Isolating) method, it will be utilized. When the remaining portion of the buried insulating film in the trench formed by this method is polished and removed, as described in the following patent document, cerium oxide (J is referred to as "cerium oxide") is widely used as a slurry of abrasive grains. material. This is based on the following, by using cerium oxide as the abrasive particles and a suitable organic compound as an additive, and the conventionally used ones are: using oxidized stone (cerium dioxide) as the abrasive grain In the case of the slurry, a higher grinding speed of the oxygen cut film can be obtained, and a higher grinding speed corresponding to the tantalum nitride film used as the polishing stop film can be selected: the grinding pressure is lower than a specific value. In the case of a grinding speed of two or two = non-Prestonian characteristics, because the umbilical recognition U is exposed to the grinding stop 之 130439.doc 200908120 stage, can inhibit excessively grinding the separation zone of the element of the oxidized stone . As a result, it is possible to achieve a polishing with a small pattern dependency and high flatness. Further, 'in recent years', as shown in the following Patent Document 2, provides a non-prestoning rate at a polishing rate of about 20 to 50 nm per minute when the polishing pressure (pressing pressure at the time of polishing) is lower than a fixed value. CP - a strong abrasive material. When the surface of the film to be polished having the shape of the convex portion is polished by using such a polishing material, the polishing is performed at a polishing speed of about 100 to 1000 nm per knife hour in the presence of the convex portion, and the convex portion is flattened. At the stage where the surface of the polishing film is substantially flat, the polishing rate is rapidly lowered to 5 〇 nm & right and below, and the polishing is hardly performed as compared with the polishing rate which is usually applied. That is, by using such non-Preston (n〇n_Prest〇nian) abrasive particles (abrasive material), such as interlayer insulation having a convex portion formed after formation of a semiconductor element or metal wiring In the case of a film or the like, when the material does not exist in the polishing film different from the film to be polished, the polishing speed is automatically dropped sharply during the flattening of the convex portion (almost no, automatic shutdown). The interlayer insulating film can also realize a polishing process with high flatness. [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. Hei. No. 2, No. Hei. No. 2, No. 2, pp. When a polishing grain having a strong characteristic is used, and a flattening process (polishing process) is performed on a film to be polished having a convex portion, the film to be polished 130439 is obtained by flattening the convex portion. .doc 200908120 When the surface is roughly flattened, the automatic grinding becomes almost impossible. Therefore, there is a problem that even if a defect such as a scratch generated on the surface of the film to be polished exists, the defect does not be removed but remains directly, so that the defect density of the surface of the film to be polished after the planarization treatment becomes very large. . Further, the following problem occurs. The polishing rate after the flattening of the convex portion is very slow, so that it is difficult to control the amount of polishing in the CMP treatment for each treatment batch based on the film formation amount in the stage before the CMP treatment which is measured in advance. The present invention has been made in view of the above problems, and an object thereof is to provide a method for suppressing the surface of a film to be polished by using a material having a non-Prestonian property as a polishing particle. The method of planarizing the surface of the film to be polished and controlling the thickness of the film to be polished, and providing a method of manufacturing a semiconductor device using the planarization method. A first feature of the method for fabricating a semiconductor device of the present invention for achieving the above object includes a film forming step of forming a film to be polished composed of an insulating film or a conductive film on a semiconductor substrate, and a planarization step. After the film forming step is completed, the film forming surface of the film to be polished is planarized; the planarizing step includes: a first polishing process using a non-Prestonian property. The grain is subjected to a polishing treatment on the surface of the film to be polished; and a second polishing process is performed after the first polishing process is completed, and the film is subjected to a polishing pressure of 1.5 times or more as compared with the first polishing process. The surface of the polishing film is subjected to a polishing treatment. The first polishing treatment is completed at a stage where the film formation surface of the film to be polished is changed to a first surface state, and the first surface state is at least perpendicular to a direction of the semiconductor substrate surface. The height or depth is 100 nm or more. 130439.doc 200908120 The protrusion or recess does not exist. According to the above feature of the method of manufacturing a semiconductor device of the present invention, the first polishing process having a relatively small polishing pressure flattens the convex portion or the concave portion existing on the surface of the film to be polished, and the polishing pressure is relatively large. In the second polishing treatment, after the second polishing treatment, the region where the surface of the polishing crucible is defective is polished, whereby the number of defects on the surface after the polishing can be reduced. Thereby, the film-formed film to be polished is not excessively polished, and the surface of the film to be polished can be planarized, and the number of defects existing in the film to be polished after polishing can be greatly reduced as compared with the prior art. Further, since the second polishing treatment performed after the first polishing treatment has a larger polishing pressure than the first polishing treatment, the surface of the surface to be polished in the second surface state can be polished at a monitorable speed. Thereby, it is possible to control so that the second polishing treatment is performed at a time point when the predetermined film thickness is polished, and the Q beam, and the film thickness of the film to be polished which needs to be left can be easily adjusted. Further, in addition to the above-described second feature, the manufacturing method of the semiconductor device of the present invention is characterized in that, in the second polishing process, the polishing rate of the film formation surface in the first surface state is just after the start. The grinding speed is less than 1 / 4. According to the second aspect of the method for manufacturing a semiconductor device of the present invention, the convex portion or the concave portion is planarized by the first polishing treatment, and the polishing speed is greatly reduced when the surface of the polished film is in the i-th surface state. Therefore, the end timing of the first polishing process can be easily identified. Further, the polishing rate corresponding to the surface of the film to be polished in the first surface state is 130,130.doc 200908120 k', so that the film to be polished is not excessively polished after the flattening treatment for the convex portion or the concave portion is completed. Further, in addition to the first or second feature described above, the third method of manufacturing the semiconductor device of the present invention is characterized in that the second polishing process is performed on the film formation surface in the first surface state by 2 Å per minute. The polishing is carried out under grinding conditions of 〇nm or more. According to the third feature of the method of manufacturing a semiconductor device of the present invention, the number of defects remaining after polishing can be reduced as compared with the first polishing process, and the surface is present on the surface of the film to be polished after the second polishing process is included. The film formation area of the defect is ground. Further, since the surface of the surface to be polished of the surface of the second surface can be polished at a monitorable polishing rate, the control of the thickness of the polishing film can be facilitated. Thereby, it is possible to control only the film formation region of the defect generated after the first polishing process by the plurality of packets 3, and then the second polishing process is completed without excessively polishing, thereby suppressing the remaining after polishing. The number of defects in the film being polished. Further, in addition to any one of the above-described rth to third features, the fourth aspect of the present invention is characterized in that the second polishing process is performed on a film formation surface in the first surface state. It is carried out under grinding conditions of 5 μm or less per minute. According to the fourth feature of the method of manufacturing a semiconductor device of the present invention, the polishing rate corresponding to the surface of the film to be polished in the first surface state is extremely slow. Therefore, after the planarization of the convex portion or the concave portion is completed, there is no excess. The ground film is ground. Thereby, it is possible to shift to the second polishing treatment without excessive polishing by the second polishing treatment. In addition to any one of the first to fourth features of the present invention, the second polishing method is configured to apply a film thickness to the film to be polished. Finished after grinding above nm. According to the fifth feature of the method for fabricating a semiconductor device of the present invention, the number of defects remaining in the polishing pad remaining after the second polishing process can be suppressed within a range that does not affect the subsequent manufacturing steps. Moreover, the manufacturing method of the semiconductor device of the present invention is not limited to the above first to the first

In addition to any of the features, the sixth feature is that the film to be polished is a ruthenium oxide film formed by an HDP (Hlgh-Density Piasma) method. According to the sixth aspect of the method of manufacturing a semiconductor device of the present invention, in the polishing process, the polishing unevenness of the film to be polished in the first surface state can be made very slow, thereby suppressing excessive polishing of the film to be polished. . According to the configuration of the present invention, the number of defects existing on the surface of the film to be polished after planarization can be reduced, and the residual film thickness of the film to be polished after planarization can be easily controlled. [Embodiment] Hereinafter, an embodiment of the semiconductor device of the present invention (hereinafter, appropriately referred to as "the method of the present invention") will be described with reference to the drawings of the following drawings to Fig. 3. The f 1 system schematically shows that the schematic cross-sections of the respective steps of the method of the present invention are shown in Fig. 1 (4) to (4) for each step. Further, Fig. 2 is a flow chart showing the manufacturing steps of the method of the present invention, and the respective steps in the following tables are not the steps of the flowchart shown in Fig. 2. Further, the schematic cross-sectional structural diagram shown in Fig. 1 is only schematically illustrated, and the scale of the actual structure is not necessarily the same as the scale of the figure. First, as shown in FIG. 1(a), a semiconductor element or a metal wiring layer is formed on the semiconductor substrate w (hereinafter, simply described as "semiconductor element 2"), and an interlayer insulating film 3 is deposited on the upper surface thereof (step is called. The interlayer insulating film 3' is made by using the mgh-Density Plasma method at a film forming temperature of 200 to 70 〇m and a pressure of about 1 to 1 〇Pa to a film thickness of 100 to 2000. The thickness of the interlayer insulating spacer 3 is at least larger than the height of the semiconductor element 2. The stacking of the interlayer insulating medium 3 by the step is as shown in the figure (4). The surface of the upper portion of the region in which the semiconductor element 2 is formed and the upper portion of the region in which the semiconductor element 2 is formed are fixed and uneven on the surface. Hereinafter, the uneven portions are referred to as "protrusion 4" and "non-convex". Further, the term "concave-convex portion as used herein refers to a region in which the interlayer film 2 of the interlayer insulating film is different in the direction of the nm or more in the direction perpendicular to the substrate surface of the semiconductor substrate". That is, 'the uppermost surface of the above convex portion 4 The height position is higher than the height position of the uppermost surface of the adjacent non-protrusion portion 5 by 100 nm or more. Next, as shown in Fig. 1 (b) and (4), the substrate surface is used by the CMp method to include cerium oxide as the abrasive grain. The polishing process of the abrasive (hereinafter referred to as "the i-th polishing process") (step #2), thereby flattening the convex portion 4 formed on the upper surface of the interlayer insulating crucible 3. Further, Fig. i(8) FIG. 1(4) shows a cross-sectional view at the end of the polishing station 130439.doc 200908120. As shown in Fig. 1 (4), at the time point when the polishing process is finished, the interlayer insulating film 3 The surface of the 矣& and the 啄膘^ is in a state in which the convex portion 4 does not exist (hereinafter, it is appropriately referred to as "the first surface state"). The 丨 丨 丨 丨 四 四 四 四 四 四 四 四In the case where the oxidized material is a polishing material of the abrasive grains, the high polishing rate is maintained in the first surface state (4) (4) of the convex portion 4, and the polishing rate is automatically lowered to cause automatic shutdown. Grinding is performed.

As a more specific polishing condition in the step #1, for example, the abrasive material CES-333-2.0 containing the oxidized (four) abrasive grains manufactured by Asahi Co., Ltd. is dropped every minute for about 200 d, so that the pressing pressure at the time of grinding ( Hereinafter, simply referred to as "grinding pressure") is about 3 psi (the mark per square inch, about 2 i kpa), so that the rotation speed of the substrate (head) is about 12 〇, and the rotation speed of the polishing cloth (10) (four) is about 13 〇 rpm, (four) line grinding at the king. In the case of the conventional system, when the thickness of the semiconductor element 2 is about i 8 〇 nm and the p_Si 〇 film having a film thickness of about H) 00 nm is formed as the interlayer insulating 臈 3, the above-mentioned polishing conditions are performed. In the case of the rubbing treatment, the measurement of the change in the height position of the convex portion 4 and the non-convex portion 5 from the upper surface of the semiconductor substrate is performed by using the spectroscopic ellipsometry or the spectroscopic interference reflectance method. The optical film thickness measurement method of the interlayer insulating film 3 is performed on the surface difference measurement method of the surface of the interlayer insulating film 3 by atomic force microscopy, and the semiconductor substrate (wafer) having a diameter of about 200 mm is shown. The average of the measured values of the nine different points in the plane. Furthermore, the difference bar of each point indicates the upper limit of the measured value of the nine points in the upper surface 130439.doc •12- 200908120 The unevenness of the king's limit. Here, in actuality, in the stage of the second polishing treatment for 10 seconds or more, the surface state of the interlayer insulating film 3 is in the first surface state, and the convex portion 4 is not present, and in the following description, & It is convenient to explain how the height positions of the convex portion 4 and the non-convex portion 5 existing before the start of the second polishing process are changed by the execution of the first polishing process, and the convex region formed before the start is described as "convex" In the portion 4", a region in which the non-protrusion portion 5 is formed before the start of the i-th polishing portion = 记载 is referred to as "non-convex portion 5". In Fig. 3, the dots drawn in the black square shape indicate the height position of the convex portion 4, and are solid lines]! Indicates the state of change. On the other hand, the dot table drawn by the circle of the hollow is not the height position of the convex portion 5 and the variable = state indicated by the broken line 12. In addition, the arrow shown in the up and down direction of each drawing position indicates that the plurality of samples are in the same condition under the same conditions. The sample is in the first grinding process: L, the arrow of the solid line The height of the convex portion 4 is not indicated: the dotted arrow indicates the unevenness of the height position of the non-protrusion portion 5. 2: At the beginning of the Γ grinding process (grinding time. sec), the same position of the convex portion 4 and the height member 2 of the non-protrusion portion 5 are thick, and the difference is substantially equal to the thickness of the semiconductor element noon, and FIG. 3 The chart shows approximately 18 〇 (10). Secondly, by performing the first, the grinding process is performed for about 1 () seconds, and the convex portion 4 is applied more than the non-protrusion portion 5 as compared with the surface of the non-protrusion portion 5: After the surface positions become substantially equal, even if the surface position of the area of the in/out 4f non-convex portion 5 is almost polished, two lines are processed. In other words, it is considered that the polishing is not indicated by the condition of the condition, and it can be said that the flattening of the portion of the convex portion 130439.doc 200908120 is completed (that is, the state of FIG. 1(c)), and the surface of the interlayer insulating film 3 becomes The first surface state described above. Further, the polishing rate of the surface of the interlayer insulating film 3 in the first surface state (after the polishing time elapses after the leap second) is approximately 23 nrn per minute, and approximately 1 〇 second after the start of the first polishing treatment. 4 is compared to a grinding speed of about 8 〇 nm, which is a very slow grinding speed. As described above, the first polishing treatment uses cerium oxide abrasive grains as the abrasive material, and has a non-prestoning characteristic when the polishing pressure is lower than a fixed value. Moreover, by utilizing such a property, it is characterized in that it is not excessively ground even after the flattening is completed. Therefore, in order to utilize this feature, it is preferable that the polishing rate in the case where the convex portion 4 is present is extremely large as compared with the polishing speed after the flattening of the convex portion * is completed, whereby the third step is performed under such conditions. In the polishing treatment, the interlayer insulating film 3 is not excessively polished to planarize the surface. That is, the first grinding process has a feature that the grinding speed is faster than the grinding pressure above a certain threshold, and the grinding speed is very slow below the grinding pressure of the threshold. Therefore, in order to fully utilize the feature The grinding condition must be adjusted so that the polishing pressure on the film forming surface where the convex portion 4 is present is higher than the above-mentioned threshold value, and conversely, the polishing pressure on the film forming surface in which the second surface state of the convex portion 4 is not present is lower than the above Threshold. Specifically, it is preferable that the polishing rate corresponding to the surface of the interlayer insulating film 3 in the first surface state after the planarization process is 50 nm or less per minute, and the convex portion 4 before the planarization treatment exists. In the case of the condition, the surface of the interlayer film 130439.doc • 14 - 200908120 is polished at a polishing rate of 4 times or more. However, the polishing rate corresponding to the interlayer insulating film 3 after the flattening treatment of the convex portion 4 is changed according to the material used as the abrasive grains, and also depends on the film type of the interlayer insulating film 3 to be polished. And change. For example, in the case of a P_TE〇s film formed by a plasma-assisted chemical vapor deposition (PE-CVD) method, the polishing rate after the planarization treatment is about 31 nm per minute. And the polishing rate of 23 nm per knife ring represented by the P-SiO film formed by the above HDP method is still 'but is a very slow polishing speed of less than $〇nm per minute, so it can be said that This material is used as the interlayer insulating film 3, and flattening of the convex portion 4 can be achieved without excessive polishing. On the other hand, in the bpsg film doped with b and p formed by the thermal CVD method, since the polishing rate after the planarization treatment is 450 nm or more per minute, it is not suitable as the first polishing treatment. Grind the object. When the polishing speed in the case where the convex portion 4 is present in the first polishing process is such that the polishing speed after the flattening of the convex portion 4 is completed is very slow, for example, as usual The flattening can be completed by continuously monitoring the substrate (head) rotation torque or the platen rotation torque over time. When the end of the flattening is confirmed as described above, the flattening of the convex portion 4 can be performed without excessive polishing by terminating the second polishing process. However, since the polishing rate of the second polishing treatment after the completion of the planarization is very slow, as shown in FIG. 1(c), the surface of the interlayer insulating film 3 after the completion of the first polishing treatment is generated during polishing (4). Traces and other defects remain unchanged 130439.doc 200908120

Here, the interlayer insulating film 3 is subjected to a polishing treatment (hereinafter referred to as "second polishing treatment", step #3), in which the polishing pressure is 15 times or more as compared with the first polishing treatment in the step #2. By the second polishing treatment, the upper surface of the interlayer insulating film 3 is polished to remove the defects 6 remaining on the upper surface. In the second polishing treatment, it is not necessary to change the polishing material and the polishing cloth from the second polishing treatment, and the first polishing treatment may be continued continuously.

get on. For example, the interlayer insulating film 3 having a film thickness of about 00 nm is removed by grinding with a polishing pressure of about 6 psi (about 41 kPa) for about 40 seconds. Table 1 below shows a table showing the number of defects existing on the surface of the interlayer insulating film 3 after polishing corresponding to the amount of polishing removal of the interlayer insulating film 3 in the second polishing treatment. [Table 1]

The amount of polishing in the second polishing treatment "nm! 0 (only the number of defects in the first grinding disc (number / crystal 11, > 100 nm)

Π3 (only the second polishing treatment) 53 Further, the number of defects shown in the above Table 1 indicates the size of the defect by performing appropriate cleaning (the rectangular shape is cut out from the planar shape when the defect region is observed from the upper surface) The average of the long side and the short side is about (10) (10) or more, and the diameter is about 2 (8), which is represented by the number 1 of the semiconductor substrate (wafer). Hereinafter, the defect in the range counted as the number of defects is described as "defect 6". The sample S1 is a measure of the number of defects when only the first polishing process is performed and the second polishing process 130439.doc 200908120 is not performed. Further, in the sample (four), the number of defects in the case where the polishing treatment of the second polishing treatment is changed after the first polishing treatment is performed under the phase = condition is measured. In addition, the sample S5 is not subjected to the first polishing treatment, and only the number of defects in the case where the polishing process is increased to increase the polishing force and the flattening process of the convex portion 4 is performed is measured. Further, the polishing amounts of the second polishing treatments of the respective samples S2 to S5 were as follows, the sample was called 28 nm', the sample S3 was 57 nm, and the sample was 85 biliary, and the sample was (10) (1) (10).

In the case of the sample S1, there are more than 3 very large defects 6 on the surface of the interlayer insulating film 3 after the second polishing treatment. Therefore, when only the first polishing process is performed, the CMp step is terminated, and if it is a step, the metal film is deposited for wiring, for example, due to a large number of defects 6 remaining on the upper surface of the interlayer insulating film 3. When the metal material in the defect 6 is formed, the defect which is not normally etched in the etching step for forming the wiring pattern is generated, or the pattern which is generated in the upper portion of the photolithography (four) film defect 6 disappears or the residual pattern remains. As a result, various obstacles such as wiring or through holes that cannot form a desired shape may occur. On the other hand, after the ith polishing process is performed as a result of the sample S2, the interlayer insulating film 3 having a film thickness of 28 nm is removed by the second polishing process, whereby the number of defects per wafer is reduced to about 3 Å. Hey. Accordingly, it is considered that although the number of defects generated by the first polishing process is extremely large, the number of defects located at a position on the upper surface of the interlayer insulating film 3 after the end of the upper polishing process is 3 〇, is half, The interlayer insulating film 3 is removed by the second polishing treatment, whereby the defect 6 is effectively removed. Further, it can be said that the defect 6 generated by the i-th grinding process is of course changed according to the state of the grinding device of I30439.doc -17-200908120, but is smaller than the size of the general abrasive grain. Defects, and it is difficult to suppress the defect itself by only the usual device management method. Further, according to the result of the sample S4, if the amount of removal of the interlayer insulating film 3 is increased to about 85 nm by the second polishing treatment, the number of defects per wafer can be reduced to about 100 or less. As in the case of the sample S5, it is possible to suppress the number of defects to be almost the same as in the case where the CMP step is performed only by the second polishing treatment. Further, when only the second polishing treatment is performed as in the case of the sample 85, the number of defects can be reduced as much as the above-described Table 1, but the convex portion 4 is not formed by the polishing pressure as compared with the second polishing treatment. After the existence of the third surface state, 'a large amount of grinding is performed, and as a result, the grinding process may be excessively performed. In other words, as in the method of the present invention, the film formation surface is in the first surface state while the film thickness is minimized while the film thickness is minimized, and the second polishing process is performed by the second polishing process. The grinding process is performed to minimize the amount of defects required, thereby achieving the number of defects remaining after the grinding reduction process and suppressing the thickness of the polishing film. In the above, it is preferable that the polishing amount of the interlayer insulating film 3 is about 30 nm or more by the second polishing treatment, and more preferably 8 Å or more. Further, since the second polishing treatment is larger than the polishing of the first polishing treatment, the polishing rate is faster than the polishing treatment for the interlayer insulating film 3 having the first surface state. Therefore, the second polishing treatment can be performed by monitoring the film thickness _ surface of the interlayer insulating film 3 by an optical method such as a general surface, and 130439.doc • 18· 200908120 can easily control the interlayer insulating film 3 to be left. The thickness of the layer is such that the interlayer insulating film 3 can be left to have a desired film thickness to terminate the CMP step. Therefore, unevenness in the formation steps of the interlayer insulating film 3 or unevenness in the polishing speed of the CMP apparatus can be suppressed. After the completion of the second polishing treatment in the step #3, the wiring step and the interlayer insulating film deposition step are specifically described. Thereby, the number of defects remaining on the surface of the interlayer insulating film can be reduced, and the film thickness of the interlayer insulating film 3 to be left can be easily controlled. As described above, according to the method of the present invention, the first polishing treatment for flattening the convex portion existing on the surface of the film to be polished and the second polishing for reducing the number of defects on the damaged surface are performed under different polishing conditions. By this, the film to be polished is not excessively polished, and the surface of the film to be polished can be planarized, and the amount of defects remaining on the surface after polishing can be greatly reduced as compared with the prior art. Further, since the second polishing treatment performed later has a larger polishing pressure than the first polishing treatment, the surface of the surface to be polished in the first surface state can be polished at a monitorable speed. Thereby, it is possible to control so that the second polishing treatment is completed at the time point when the predetermined film thickness is polished, and the film thickness of the film to be polished which can be left can be easily adjusted. In the above-described embodiment, the case where the interlayer insulating film is planarized is described as an example. However, the film to be polished is not limited to the insulating film, and J J is a conductive film. In addition, in Fig. 1, the expressions "protrusion", "non-&, primordial, earth" are expressed, and the concave-convex region formed on the film-forming surface is referred to as a medium 7 and the right height is higher. The area is the reference 130439.doc -19- 200908120, and it can also be described as "concave portion" and "non-recessed portion 4_. ^". "Frightening corpse is the above-mentioned "i-th surface state" in a plane state in which the convex portion 4 does not exist. Refers to the planar state in which the concave portion does not exist. If the general term is used, it is based on the fact that the film surface does not have a surface state in the direction of the substrate surface perpendicular to the semiconductor board 1 or The depth position changes by more than 1〇〇. Nm [Simple diagram description] Ο

FIG. 2 is a schematic cross-sectional structural view showing the steps of the method for fabricating the semiconductor device of the present invention. FIG. 2 is a flow chart showing the sequence of steps of the method for fabricating the semiconductor device of the present invention. Graph of polishing time characteristics of the first polishing treatment. [Description of main component symbols] 1 Semiconductor substrate 2 Semiconductor component 3 Interlayer insulating film 4 Projection portion 5 Non-convex portion 130439.doc -20-

Claims (1)

200908120 X. Patent application scope: 1. A method for manufacturing a semiconductor device, comprising: a film forming step of forming a film to be polished comprising an insulating germanium or a conductive film on a semiconductor substrate; and a planarizing step, After the film forming step is completed, the surface of the film to be polished is flattened; the planarization step includes: the first polishing process is performed using a non-prestoning characteristic The abrasive grains are subjected to a polishing treatment on the surface of the film to be polished; and the second polishing treatment is performed after the first polishing treatment is completed, and the polishing ink force is 1.5 times or more higher than the first polishing treatment. And polishing the surface of the film to be polished; the first polishing process is completed at a stage of changing a film formation surface of the film to be polished to a first surface state, wherein the first surface state is at least perpendicular to the semiconductor A protrusion or a recess having a height or depth of 100 nm or more in the direction of the substrate surface does not exist. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the first polishing treatment, the polishing rate of the film formation surface in the surface state of the first surface is 1/4 or less of the polishing rate immediately after the start. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the second polishing treatment is performed on a polishing condition in which the film formation surface in the surface state of the second surface is subjected to grinding at 130439.doc 200908120 per minute by 200 nm or more. Go on. 4. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the i-th polishing treatment is performed under polishing conditions in which the film formation surface in the first surface state is polished to 50 nm or less per minute. 5. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the second polishing treatment is performed after the film is polished to a thickness of 3 〇 nm or more. 6. The method of manufacturing a semiconductor device according to claim 2, wherein the film to be polished is a ruthenium oxide film formed by the HDP method. 130439.doc