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  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/15—Charge-coupled device [CCD] image sensors
  • H10F39/158—Charge-coupled device [CCD] image sensors having arrangements for blooming suppression
• • H—ELECTRICITY
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  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
  • H10F39/014—Manufacture or treatment of image sensors covered by group H10F39/12 of CMOS image sensors
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  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
  • H10F39/182—Colour image sensors
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  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
  • H10F39/186—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors having arrangements for blooming suppression
  • H10F39/1865—Overflow drain structures
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  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
  • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
  • H10F39/8033—Photosensitive area
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
  • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
  • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
  • H10F39/807—Pixel isolation structures

Definitions

• Embodiments of the present invention are generally related to pixel technology for CMOS imaging sensors and, more particularly, to a CMOS multi- pinned (MP) pixel.
• MP multi- pinned
• FIG. 1 depicts a schematic view of a conventional NMOS 5TPPD pixel 100.
• the 5TPPD pixel 100 includes a pinned-photo diode (PPD) 102 as a photosensitive element for photo generating and collecting electrical charge.
• the PPD 102 is flanked by transfer gate- 1 (TG1 ) 104 and transfer gate-2 (TG2) 106.
• a sense node 108 is located proximate the TG1 104 and converts charge to a voltage.
• the sense node 108 is coupled to three 'read' MOSFETs 120, 122, 124. These MOSFETS are known as the reset, source follower and row select transistors, respectively. Collectively, they are responsible for reading a video voltage level on the sense node 108.
• the PPD 102 comprises a diode 126 (n-doped for a NMOS 5TPPD pixel) formed within p-epitaxial silicon 128.
• the p-epi silicon 128 resides above a highly doped p-substrate 130.
• the p- epi silicon 128 and substrate 130 are assumed to be at ground potential (i.e., zero volts) or an external negative bias potential.
• a p-doped pinning layer 132 is formed directly above and aligned with the diode 126.
• the pinning layer 132 assumes the same potential as the substrate, whereas the doping of the diode 126 sets a potential for the PPD 102.
• a p-well 134 surrounds the PPD 102, the transfer gates 104 and 106, and the sense node 108.
• the read MOSFETS 120, 122 and 124 as well as additional support circuitry are formed in the p-well 134.
• charge on the sense node 108 is first removed by the reset MOSFET 120 coupled to the V REF potential 136.
• TG2 106 is "off' (i.e., decoupling the V REF potential 136 from the diode 126) and the TG1 104 is "off (i.e., decoupling the sense node 108 from the PPD 102).
• the gate TG2 1 06 is not present.
• photons interact with the PPD 1 02, electrons are generated and collected in the diode 1 26 over the time period of exposure. After exposure, TG 1 1 04 is turned “on” to transfer signal charge from the diode 1 26 to the sense node 1 08.
• the electrons present on the sense node 1 08 are converted to a voltage (by the capacitance related to the sense node 1 08). This resultant voltage is buffered by the source follower MOSFET 1 22 and output as a pixel value when the pixel row is selected by MOSFET 1 24. Once the pixel value is present at the column video output, the PPD 1 02 and sense node 1 08 are reset and the imaging process repeats.
• NMOS 5TPPD pixel For a PMOS 5TPPD pixel, the n and p doping is reversed (p becomes n, and n becomes p), the p-well becomes an n-well and the voltages V RE F, V D D are set to 0 volts and the substrate is biased at 3.3 volts. In a PMOS 5TPPD pixel, the carriers are holes rather than electrons.
• thermally generated dark current is very low for the PPD 1 02
• a significant amount of dark charge originates from the transfer gates 1 04 and 1 06 (typically 2-3 orders of magnitude higher than the PPD generated dark current).
• the level of dark current can obscure the signal level measured.
• charge trapping and recombination effects that are very common to transfer gates 1 04 and 1 06 can reduce the measured signal level.
• CTE charge transfer efficiency
• CMOS multi-pinned pixel and a method of manufacturing a CMOS multi- pinned pixel substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
• Figure 1 is a cross-sectional view of a background art 5T (i.e., a 5 transistor) n-type CMOS pinned-photo diode pixel;
• 5T i.e., a 5 transistor
• Figure 2 is a cross-sectional view of an NMOS multi-pinned (MP) pixel according to an embodiment of the present invention
• Figure 3 is a representation of potential conditions when signal charge collects in the PPD for the NMOS MP pixel of Figure 2;
• FIG. 4 is a representation of transfer gate (TG) potential in a NMOS MP pixel as a function of distance into the epitaxial silicon when signal charge collects in the PPD region. During this time, holes 'invert' the channel under TG1 and TG2 at the epitaxial silicon to oxide interface;
• TG transfer gate
• Figure 5 shows potential conditions when charge is transferred for the NMOS CMOS MP pixel of Figure 2;
• FIG. 6 is a representation of transfer gate (TG) potential in a NMOS MP pixel as a function of distance into the epitaxial silicon when signal charge transfers from the PPD region. During this time holes under the TG1 diffuse back to the p- substrate;
• TG transfer gate
• Figure 7 is a representation of potential conditions when signal charge collects in the PPD for the PMOS MP pixel of Figure 18;
• Figure 8 is a representation of transfer gate (TG) potential in a PMOS MP pixel as a function of distance into the epitaxial silicon when signal charge collects in the PPD region. During this time electrons 'invert' the channel under TG1 and TG2 at the epitaxial silicon to oxide surface;
• TG transfer gate
• Figure 9 shows potential conditions when charge is transferred for the PMOS MP pixel of Figure 18;
• Figure 10 is a representation of transfer gate (TG) potential in a PMOS MP pixel as a function of distance into the epitaxial silicon when signal charge transfers from the PPD region. During this time electrons under the TG1 diffuse back to the n- substrate;
• TG transfer gate
• Figure 1 1 is a cross-sectional view of NMOS CMOS MP pixel showing two implants often used in CMOS pixels (referred to as the TG barrier and shield implants);
• Figure 12 illustrates a potential plot for a NMOS MP pixel with a TG barrier implant shown in Figure 1 1 when signal charge collects in the PPD region;
• Figure 13 illustrates a potential plot for a NMOS MP pixel with a TG barrier implant shown in Figure 1 1 operating in charge transfer mode
• Figure 14 is a cross-sectional view of a large, high-speed NMOS MP pixel where the MP implant only covers half of the PPD region nearest TG1 and sense node regions;
• Figure 15 illustrates a potential plot for a large high speed NMOS MP pixel of Figure 14 operating in charge collection mode
• Figure 16 illustrates a potential plot for a large high speed NMOS MP pixel of Figure 14 operating in charge transfer mode
• Figure 17 depicts a top plan view of a CMOS MP pixel in accordance with one embodiment of the invention.
• Figure 18 is a cross-sectional view of a PMOS multi-pinned (MP) pixel according to an embodiment of the present invention.
• Embodiments of the present invention comprise an improved 5TPPD pixel having a multi-pinned (MP) pixel architecture.
• the improvement arises from placing an MP implant into the PPD region along with the diode and pinning implants, as well as extending the MP implant layer at least through at least one transfer gate region (TG1 and/or TG2).
• TG1 and/or TG2 transfer gate region
• satisfactory performance is achieved when the entire 5TPPD pixel is uniformly implanted with the MP implant.
• the entire silicon wafer can be globally implanted as the first step in the fabrication process.
• the use of a MP implant layer is compatable with other known 5TPPD techniques such as drain and sense node shielding, additional PPD barrier layers, implants for improving channel coupling from the transfer gate to the sense node and the like. The alternatives will be discussed below.
• FIG 2 is a simplified cross-sectional view of an n-type CMOS (NMOS) MP pixel 200 operable to have a very low dark current, according to an embodiment of the present invention.
• the NMOS MP 5TPPD pixel 200 includes a first transfer gate (TG1 ) 202 and, optionally, a second transfer gate (TG2) 204 formed upon epitaxial silicon 206 (e.g., p_epi or p_SOI).
• the epitaxial silicon 206 resides upon a highly doped substrate 250 (e.g., p-substrate).
• the NMOS MP pixel 200 includes a layer 208 of insulating material that may be, for example, an oxide of silicon (e.g., SiO 2 ) that overlies the epitaxial silicon 206 and underlies the first transfer gate 202 and the second transfer gate 204.
• the gates 204 and 202 are typically fabricated from polysilicon.
• a sense node contact implant 222 (e.g., n_phosphorus) forms the sense node 224.
• the sense node 224 is coupled to the "read" MOSFETS 252.
• a drain contact implant 226 (e.g., n_phosphorus) forms a drain region 228 coupled to a surface drain contact 230.
• a pinned-photodiode (PPD) 210 is formed in the epitaxial silicon 206 between the gates 202 and 204.
• the PPD 210 comprises a diode 212 (e.g., n_phosphorous), a pinning layer 214 (e.g., p_boron) and a portion (dashed line) of an MP implant layer 216 (e.g., n_arsenic or n_phosphorus).
• the MP implant layer 216 can entirely cover NMOS MP pixel 200 extending about 450 A below the surface 254 of the epitaxial silicon 206.
• the MP implant 216 slightly alters the the potential of the PPD 210.
• the dashed line within the PPD 210 is intended to indicate the blending of the pinning layer 214 and the MP implant layer 216.
• a control circuit 260 shown in Fig. 2A negatively biases the transfer gates (TG1 and TG2) creating a very shallow, but highly concentrated, inversion layer of holes at the epitaxial to oxide (e.g., Si-SiO 2 ) interface which come from the p-well 134 and p_substrate regions 250.
• the holes prevent the potential under the gates 202 and 204 from dropping no further than the substrate potential no matter how much additional negative bias is applied.
• the transfer gates 202 and 204 are 'pinned' to substrate potential (0V) when this happens. This special condition typically takes place when the gates 202 and 204 are negatively biased to -0.5 to -1 .0V.
• the holes provided in this manner recombine with thermal dark current electrons generated by the gates thus passivating the Si-SiO2 region.
• the first transfer gate (TG1 ) 202 is positively clocked (TG2 204 always assumes the pinned state). This, in turn, causes signal electrons to move from the PPD 210 to the sense node 224.
• the MP implant layer 216 under the gate 202 helps this process by creating a 'buried channel' that allows signal electrons to efficiently transfer to the sense node 224 deep in the silicon without Si-SiO2 interface interaction and without recombining with remnant trapped holes still present at the surface of the gate TG1 202 after inversion.
• the MP implant 216 simultaneously yields ultra-low dark current performance (usually limited by dark current generated in the PPD region) while also achieving near perfect charge transfer efficiency without trapping and recombination issues commonly related to the transfer gate 202.
• the pixel 200 as a whole is referred to as being 'multi-pinned' (MP), i.e., pinned at the photodiode 210 by the PPD pinning layer 214 and pinned at the transfer gates 202 and 204 by the MP implant 216.
• MP multi-pinned'
• the NMOS MP pixel 200 may include a deep implant 232 (e.g., p_boron) underlying (i.e., beneath) the sense node 224.
• This deep implant 232 forms a shield that prevent carriers from reaching the sense node 224 that are generated deep within the sepitaxial silicon 206.
• a similar second deep implant 234 e.g., p_boron
• the MP pixel 200 is fabricated by incorporating the MP implant followed by the PPD pixel fabrication process.
• the energy and dose of the MP implant are relatively low compared to other implants that the wafer receives.
• the dose is approximately 1 e12 ions/cm 2 BF2 at an energy of 20 keV producing an implant depth of 750 A.
• the dose is about 1 e12 ions/cm 2 P with an energy of 30 keV producing an implant depth of 450 A..
• the energy level for the MP implant is relatively low so as to not disturb the PPD potential.
• Using a high energy implant could mix with the diode implant and result in a lower PPD potential, which would reduce the charge capacity of the pixel.
• the MP and the PPD pinning layers are implanted using similar energy levels, but their dose is over an order of magnitude different. As such, the mixing of the MP and the PPD pinning layers takes place. However, this combination only causes a slight change in the diode potential and maintains the pinning function (i.e., the surface of the diode is firmly held at substrate potential).
• the MP dose is also sufficiently adjusted to ensure that the signal carriers are kept from the surface beneath the transfer gates to circumvent surface trapping and recombination, while having the dose low enough to not significantly influence full well performance defined by the diode implant.
• the fabrication process represents, in a very simplistic manner, only one way of fabrication. From the description herein, those skilled in the art may utilize other processes for fabricating NMOS or PMOS multi-pinned pixel.
• Figure 3 is a representation of potential conditions during the exposure time when signal electrons collect in the pinned-photodiode 210 for the NMOS MP pixel 200 of Figure 2.
• Figure 4 is a companion drawing to Figure 3 showing the transfer gate potential as a function of distance into the epitaxial silicon. Note the transfer gates 202, 204 are inverted and pinned to substrate potential by holes (h+) 402 supplied from the p-well and epitaxial silicon 206 that move under the surface 254 beneath the gate. The sense node 224 and the drain region 126 are held at +3.3 volts during this time. As photons impinge on the PPD 210, signal electrons collect in the PPD 210 causing the potential of the PPD 210 to "fall" towards substrate potential (0V) until full well is reached.
• Figure 5 is a representation of potential conditions for the transfer gates 202 and 204 during charge transfer for the NMOS MP pixel 200 of Figure 2.
• Figure 6 supports Figure 5 showing a representation of the transfer gate potential as a function of distance into the epitaxial silicon.
• the transfer gate 202 is clocked with a positive voltage (typcially to 2.0V for 1 us) to transfer signal electrons "e-" 606 to the sense node 224. This action also releases this transfer gate from the pinned/inverted state by releasing free holes 602 back into the p-epitaxial silicon 206 and the p-well 134.
• CMOS 5TPPD pixel For a p-type CMOS 5TPPD pixel, the p doped regions are n doped and the n doped regions are p doped.
• the voltages for drain and sense node are 0V rather than 3.3V and the epitaxial silicon voltage is biased at 3.3V instead of 0V.
• the operation of a PMOS 5TPPD MT pixel is substantially similar to the NMOS 5TPPD MP pixel, although holes are collected in the PPD rather than electrons and electrons are used to passivate the dark current instead of holes when the transfer gates are inverted.
• FIG. 18 is a simplified cross-sectional view of a p-type CMOS (PMOS) MP pixel 1800 operable to have a very low dark current, according to an embodiment of the present invention.
• the PMOS MP 5TPPD pixel 1800 includes a first transfer gate (TG1 ) 1802 and, optionally, a second transfer gate (TG2) 1804 formed upon epitaxial silicon 1806 (e.g., n_epi or p_SOI).
• the epitaxial silicon 1806 resides upon a highly doped substrate 1850 (e.g., n-substrate).
• the PMOS MP pixel 1800 includes a layer 1808 of insulating material that may be, for example, an oxide of silicon (e.g., S1O2) that overlies the epitaxial silicon 1806 and underlies the first transfer gate 1802 and the second transfer gate 1804.
• the gates 1804 and 1802 are typically fabricated from polysilicon.
• a sense node contact implant 1822 (e.g., p_boron) forms the sense node 1824.
• the sense node 1824 is coupled to the "read" MOSFETS 1852.
• a drain contact implant 1826 (e.g., P_borons) forms a drain region 1828 coupled to a surface drain contact 1830.
• a pinned-photodiode (PPD) 1810 is formed in the epitaxial silicon 1806 between the gates 1802 and 1804.
• the PPD 1810 comprises a diode 1812 (e.g., n_phosphorous), a pinning layer 1814 (e.g., n_phosphorus) and a portion (dashed line) of an MP implant layer 1816 (e.g., p_boron).
• the MP implant layer 1816 can entirely cover NMOS MP pixel 1800 extending about 450 A below the surface 1854 of the epitaxial silicon 1806.
• the MP implant 1816 slightly alters the the potential of the PPD 1810.
• the dashed line within the PPD 1810 is intended to indicate the blending of the pinning layer 1814 and the MP implant layer 1816.
• a control circuit 1860 shown in Fig. 18 positively biases the transfer gates (TG1 and TG2) creating a very shallow, but highly concentrated, inversion layer of electrons at the epitaxial to oxide (e.g., Si-SiO 2 ) interface which come from the n-well 1862 and n_substrate regions 1850.
• the electrons prevent the potential under the gates 1802 and 1804 from dropping no further than the substrate potential no matter how much additional positive bias is applied.
• the transfer gates 1802 and 1804 are 'pinned' to substrate potential (3.3V) when this happens. This special condition typically takes place when the gates 1802 and 1804 are negatively biased to -3.3 to 4.0 volts.
• the electrons provided in this manner recombine with thermal dark current holes generated by the gates thus passivating the Si-SiO 2 region.
• the first transfer gate (TG1 ) 1802 is negatively clocked (TG2 1804 always assumes the pinned state). This, in turn, causes signal holes to move from the PPD 1810 to the sense node 1824.
• the MP implant layer 1816 under the gate 1802 helps this process by creating a 'buried channel' that allows signal electrons to efficiently transfer to the sense node 1824 deep in the silicon without Si-SiO 2 interface interaction and without recombining with remnant trapped electrons still present at the surface of the gate TG1 1802 after inversion.
• the MP implant 1816 simultaneously yields ultra-low dark current performance (usually limited by dark current generated in the PPD region) while also achieving near perfect charge transfer efficiency without trapping and recombination issues commonly related to the transfer gate 1802.
• the pixel 1800 as a whole is referred to as being 'multi-pinned' (MP), i.e., pinned at the photodiode 1810 by the PPD pinning layer 1814 and pinned at the transfer gates 1802 and 1804 by the MP implant 1816.
• MP multi-pinned'
• the PMOS MP pixel 1800 may include a deep implant 1832 (e.g., n_phosphorus) underlying (i.e., beneath) the sense node 1824.
• This deep implant 1832 forms a shield that prevent carriers from reaching the sense node 1824 that are generated deep within the epitaxial silicon 1806.
• a similar second deep implant 1834 e.g., n_phosphorus
• Figure 7 is a representation of the potential conditions during the exposure time when signal charge (holes) collect in the pinned-photodiode 702 for the PMOS MP pixel.
• Figure 8 is a companion drawing to Figure 7 representing the transfer gate potential as a function of distance into the epitaxial silicon.
• the transfer gates 704, 706 are inverted and pinned to substrate potential (3.3 V) by electrons "e-" 806 supplied from the n-well and n-epitaxial silicon 800 that move under the surface 704 beneath the gate. Approximately 3.5 to 4.0 V is applied to the transfer gates for the inverted condition.
• the sense node 708 and the drain region 710 are held at +0 V during this time.
• signal holes collect in the PPD 210 causing the potential of the PPD 702 to "increase" towards substrate potential (3.3V) at which time full well is reached.
• Figure 9 represents potential voltage conditions for the transfer gates 704 and 706 as a function of distance into the epitaxial silicon during charge transfer for the PMOS MP pixel.
• the transfer gate 704 is clocked with a positive voltage (typically 2.0V for 1 us) to transfer signal holes "h+" to the sense node 708. This also releases this transfer gate from the pinned/inverted state by releasing free electrons 806 to back into the n-epitaxial silicon 800 and n-well. At the same time, a very small number of electrons 806 remain trapped at the surface 804 beneath the gate 704 which recombine with signal carriers for non MP pixels as they pass through.
• a positive voltage typically 2.0V for 1 us
• the buried channel potential provided by MP implant layer 810 keeps holes 808 from the surface where the trapped electrons are located. Hence, signal holes can fully propogate through the transfer gate region without substantial recombination loss or trapping. This action also automatically resets the PPD region 702 for the next exposure.
• the N (or P) MOS pixel may include an additional lightly doped implant (not shown) (e.g., n_phosphorus for NMOS or p_boron for PMOS) to better connect the transfer gates to the sense node or drain regions.
• an additional lightly doped implant e.g., n_phosphorus for NMOS or p_boron for PMOS.
• the use of such implants to enhance charge transfer is well-known in the art.
• the use of an MP implant layer to passivate transfer gate dark current without signal recombination loss in accordance with various embodiments of the invention is compatible with such a technique.
• Figure 1 1 depicts a cross-sectional view of an alternative embodiment of an NMOS MP pixel 1 100 comprising a barrier implant 1 102 (e.g., p_boron) underlying an edge 1 104 of both gates 202, 204 nearest the PPD 210.
• the TG barrier implant 1 102 is implanted proximate the PPD 210.
• the TG barrier implant 1 102 extends beneath the gates 202 and 204 by approximately 0.2um. This barrier implant 1 102 provides an improved barrier as charge collects within PPD 210.
• the addition of the barrier implant ensures collected signal electrons don't "leak” into the transfer gate regions and, thus, facilitates the use of shorter transfer gate lengths ( ⁇ 1 urn).
• the low dose barrier implant 1 102 does not significantly affect transfer gate inversion and CTE characteristics.
• the use of an MP implant layer in accordance with an embodiment of the invention is compatible with the use of a TG barrier implant.
• Figure 12 represents the potential conditions when signal charge collects in the PPD 210 for the NMOS MP pixel 1 100 of Figure 1 1 .
• Figure 13 represents potential conditions when charge is transferred for the NMOS MP pixel 1 100 of Figure 1 1 .
• the epitaxial layer 206 and the transfer gates 202, 204 are held at a pinned potential equal to substrate potential while the sense node 224 (and the drain region 226) are held at about +3.3 volts.
• the barrier implant 1 102 provides a pair of "shoulders" 1200 having a slightly lower potential than the rest of the transfer gate.
• signal electrons 'e-' collect in the PPD 210 that causes the potential of the PPD 210 to "fall" towards substrate potential.
• a potential e.g., about 2.0 V
• the electrons dump into the sense node 224, i.e., the charges move from region 1302 to the sense node 224.
• Figure 14 is a cross-sectional view of a "large" NMOS MP pixel 1400 configured to have a very low dark current, according to an embodiment of the present invention.
• a "large" pixel can be defined as a pixel that is greater than about 16 urn square where the amount of time necessary to charge transfer is greater than 1 us.
• Pixel 1400 comprises an MP implant layer 1404 that only includes a portion (e.g., about half) of the PPD 1406 on the transfer gate side. This partial implant increases the potential of the PPD 1406 and in turn, signal carriers migrate to this region instead of collecting in the entire PPD 1406 region. The remainder of pixel 1400 is the same as pixel 200 of Figure 2.
• Figure 15 depicts a potential representation 1500 depicting the potential levels of pixel 1400 during charge collection.
• Figure 16 depicts a potential representation 1600 depicting the potential levels of pixel 1400 during charge transfer.
• the sense node 224 is held at 3.3v (for an n-type device) while the transfer gate 202 is inverted and pinned. Since the MP implant layer 1404 extends partially into the PPD 1406, two different potentials are created within the PPD 1406.
• the region 1502 without the MP implant layer 1404 has a slightly lower potential than the region 1504 compared to the MP implanted layer 1404; thus, causing all signal charge to move and collect in the PPD 210 toward the transfer gate 202 side into MP implant layer 1404.
• Figure 17 depicts a top plan view of a CMOS MP pixel 1700 in accordance with one embodiment of the invention.
• the pixel 1700 may be NMOS or PMOS.
• the first and second transfer gates 1702 and 1704 are formed on each side of a PPD 1706, while the read MOSFETs 1708 are placed in a well 1710 circumscribing the PPD 1706.
• the pixel 1700 is repeated in rows and columns to form an MxN pixel sensor, where M and N are integers.

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