WO2014012323A1 - 一种倒装焊发光二极管的制造方法 - Google Patents

一种倒装焊发光二极管的制造方法 Download PDF

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Publication number
WO2014012323A1
WO2014012323A1 PCT/CN2012/086087 CN2012086087W WO2014012323A1 WO 2014012323 A1 WO2014012323 A1 WO 2014012323A1 CN 2012086087 W CN2012086087 W CN 2012086087W WO 2014012323 A1 WO2014012323 A1 WO 2014012323A1
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Prior art keywords
electrode
layer
gallium nitride
light
emitting diode
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PCT/CN2012/086087
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English (en)
French (fr)
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廖丰标
顾玲
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江苏扬景光电有限公司
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Publication of WO2014012323A1 publication Critical patent/WO2014012323A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Definitions

  • the present invention relates to the field of fabrication of flip-chip LEDs, and more particularly to III-nitride flip-chip bonded LEDs for illumination applications.
  • the earliest nitride LED (Light Emitting Diode) flip-chip package uses a metal bump to accurately position the bump on the die to a conductive contact on a flip-chip board. Thereafter, the metal balls are heated by microwaves or the like to electrically connect the crystal grains to the flip chip. Finally, the gap between the die and the flip chip is packaged by the dispensing technology, thereby completing the package fabrication of a chip; in addition, the chip usually needs to be baked once again to cure the material filled during dispensing. Because the contact area of the metal ball is still small, it does not fully meet the heat dissipation and injection current uniformity requirements of the power LED.
  • the insulating layer is located between the first electrode layer and the second electrode layer to electrically isolate and support the first electrode layer and the second electrode layer.
  • the conductive bonding agent is made of silver paste
  • the above exposed area must be at least 625 square microns for direct coating.
  • the exposed area described above must be at least 10,000 square micrometers for direct coating.
  • the isoplanar characteristics of the two electrodes are important for the yield of the process, but the disadvantage is that the two electrodes do not actually reach the true equi-plane, or the two electrodes reach the equi-plane, but there are Wasted light-emitting area; n semiconductor contact failure; no reflective layer under P-electrode; reflective layer and ohmic layer separated by insulating layer, so the reflectivity is reduced; P-electrode area is small, so the heat dissipation and injection current of the power LED are not uniform sexual needs.
  • an object of the present invention is to provide a method for manufacturing a flip-chip light-emitting diode, in which the upper surfaces of the two electrodes have the same height and improve the process yield during direct bonding. No waste of light-emitting area; n good semiconductor contact; high reflectivity; large P-electrode area, in line with the heat dissipation of the power LED and uniformity of injection current.
  • the technical solution adopted by the present invention is a method for manufacturing a flip-chip light emitting diode, comprising the following steps:
  • gallium nitride buffer layer and sequentially forming a gallium nitride buffer layer and a gallium nitride light emitting diode epitaxial layer on the substrate, wherein the gallium nitride light emitting diode epitaxial layer comprises n-type gallium nitride arranged in sequence a layer, a light emitting layer and a P-type gallium nitride layer; (2) forming a p-electrode on the p-type gallium nitride layer;
  • an etching mask is used so that only the insulating layers of the P-electrode and the upper portion of the n-electrode are dry-etched to form contact holes.
  • an ohmic contact layer of an n-electrode is formed on the n-type gallium nitride layer, and then a second bonding metal layer is formed on the ohmic contact layer of the n-electrode.
  • both the P-electrode and the n-electrode control a region where the electrode is formed by a photolithography etching process. Further, the upper surfaces of the P-electrode and the n-electrode are the same height.
  • the P-electrode comprises a first transparent conductive layer, a metal reflective layer and a first bonding metal layer which are sequentially disposed.
  • the material of the first transparent conductive layer is an alloy of nickel oxide and gold, indium tin oxide, zinc oxide or aluminum zinc oxide for forming an ohmic contact with the p-type gallium nitride layer;
  • the metal reflective layer The material is nickel, palladium, chromium, platinum, aluminum or silver for reflecting light emitted by the epitaxial layer of the gallium nitride light emitting diode and as a diffusion barrier layer;
  • the material of the first bonding metal layer is gold or gold alloy, Used to engage with the mounting table.
  • the insulating layer includes a first insulating layer made of SiO 2 or SiN by PECVD and a second insulating layer made of an organic polymer material covered by the first insulating layer, and the second insulating layer is made by a planarization process. The upper surface of the second insulating layer is flush.
  • the present invention can effectively increase the light output and luminous efficiency of a nitride flip-chip bonded LED. Because the n-electrode and the p-electrode of the light-emitting diode are of the same height, when the LED is flip-chip soldered, the electrode can be directly connected to the solder pad without using bumps, thereby improving the heat dissipation and current distribution uniformity of the light-emitting diode, thereby increasing the light-emitting diode. Luminous efficiency and longevity, and reduced light decay.
  • FIG. 1 is a schematic structural view of a flip-chip light-emitting tube of Embodiment 1 (excluding a mounting table), wherein the horizontal line region is an n-electrode, and the oblique line region is a P-electrode;
  • Figure 2 is a cross-sectional view taken along line A-A' of Figure 1;
  • FIG. 3 is a schematic structural view showing the formation of the first step of the embodiment 1;
  • FIG. 4 is a schematic structural view of the second step of the first embodiment
  • FIG. 5 is a schematic structural view showing a third process of the first embodiment
  • FIG. 6 is a schematic structural view showing a fourth process of Embodiment 1;
  • FIG. 7 is a schematic structural view of a fifth process of the first embodiment
  • FIG. 8 is a schematic structural view showing the formation of the sixth step of the embodiment 1;
  • Figure 9 is a schematic view showing the structure of the flip-chip welding tube of the first embodiment (including the mounting table);
  • Figure 10 is a schematic view showing the structure of the flip-chip light-emitting tube of Embodiment 2 (excluding the mounting table), wherein the horizontal line area is an n-electrode, and the oblique line area is a P-electrode;
  • Figure 11 is a cross-sectional view taken along line B-B' of Figure 11;
  • FIG. 12 is a schematic structural view of a flip-chip light-emitting tube of Embodiment 3 (excluding a mounting table), wherein the horizontal line region is an ohmic contact layer of an n-electrode and a second bonding metal layer of an n-electrode, and the oblique line region is P-electrode, the black area is an ohmic contact layer of the n-electrode;
  • Figure 13 is a cross-sectional view taken along line C-C' of Figure 12;
  • Figure 14 is a cross-sectional view taken along line D-D' of Figure 12;
  • FIG. 15 is a schematic structural view of a flip-chip light-emitting tube of Embodiment 4 (excluding a mounting table), wherein the horizontal line region is an ohmic contact layer of an n-electrode and a second bonding metal layer of an n-electrode, and the oblique line region is P-electrode, the black area is an ohmic contact layer of the n-electrode;
  • Figure 16 is a cross-sectional view taken along line E-E' of Figure 15;
  • Figure 17 is a cross-sectional view taken along line FF' of Figure 15.
  • the P-metal Due to the high resistivity of the P-type gallium nitride layer, the P-metal is covered in the LED design to provide a better current distribution at the P-end. Because of the sapphire substrate insulation, the N-terminal current diffusion must pass through the N-type gallium nitride layer.
  • the N-type gallium nitride layer typically has a thickness of 2 microns and a sheet resistance of about 10-3 Q cm . To ignore this part of the resistor, the current conduction distance is less than 200 microns. Therefore, when the LED is larger than 400*400 microns 2 (large size LED), the n-electrode needs to be extended to form multiple whiskers to reduce the resistance. . This structure makes the flip-chip soldering process difficult because the P-metal and the n-metal must remain insulated when the LED is flip-chip mounted on the mounting table.
  • Example 1 Small size LED, no etched shield
  • a substrate is provided.
  • the material of the substrate may be, for example, sapphire in this embodiment.
  • a gallium nitride buffer layer (GaN bumper layer) 31 and a gallium nitride light emitting diode epitaxial layer are sequentially formed on the substrate 30.
  • the epitaxial layer of the gallium nitride light emitting diode sequentially includes an n-type gallium nitride layer 32, and more
  • a multi-quantum wel-active layer ( MQW active layer) 33 and a p-type gallium nitride layer 34 are provided.
  • a P-electrode is formed on the p-type gallium nitride layer 34 by a photol ithography process. As shown in FIG. 4, a first transparent conductive layer 35, a metal reflective layer 36, and a first layer are sequentially formed on a P-type GaN layer 34 by vapor deposition, sputtering, or electroplating. The metal layer 37 is bonded, and the first transparent conductive layer 35, the metal reflective layer 36, and the first bonding metal layer 37 serve as P-electrodes.
  • the material of the first transparent conductive layer 35 may be, for example, an alloy of nickel oxide and gold (NiO/Au), Indium Tin Oxide (ITO), zinc oxide ( ⁇ ) or aluminum zinc oxide ( Aluminum Zinc
  • the material of the metal reflective layer 36 may be, for example, nickel (Ni), palladium (Pd), chromium (Cr), platinum Pt, Aluminum (A1) or silver (Ag) for reflecting light emitted from the epitaxial layer of the gallium nitride light emitting diode and as a diffusion barrier layer;
  • the material of the first bonding metal layer 37 may be, for example, in this embodiment It is gold (Au) or gold alloy (Au al loy) for bonding with the mounting table 41 (as shown in Figure 9).
  • Dry etching also known as plasma etching, using a P-electrode as a hard mask, using gas as the main etching medium, such as C1 2 /BC1 3 .
  • the plasma energy drives the reaction, dry etching GaN, and reaches the n-GaN semiconductor ( ⁇ -type gallium nitride layer 32) as shown in FIG.
  • Another implementation manner is to first apply a photosensitive material (photo-adhesive) on the surface of the wafer, and place a photomask on the wafer, and the photomask is provided with a pattern and a number of patterns with respect to the etched and non-etched regions. Then, an exposure step is performed to selectively illuminate the photosensitive material through the reticle, and the pattern on the reticle is completely transferred to the wafer, and then developed and developed by exposure.
  • a photosensitive material photo-adhesive
  • the photoresist obtains the same or complementary pattern as the mask pattern, and then dry etching (Dry Etching), also known as plasma etching, uses gas as the main etching medium, such as C1 2 /BC1 3 , and borrows
  • the reaction is driven by the plasma energy, the GaN is dry etched, and the n-GaN semiconductor is reached, after which the photoresist on the wafer is removed.
  • n-electrode the amount of etching thickness (starting from the top of the P-electrode), using a micro-etching
  • a (photol ithography) process forms an n-electrode on the n-type gallium nitride layer 32.
  • an n-type GaN layer 32 is plated with an n-electrode by an evaporation, sputtering or plating technique, and the n-electrode is made of an alloy of Ti and A1 or An alloy of Cr and Au or an alloy of Ti and Au or an alloy of Ti, Al, Cr and Au has a high P-electrode and an n-electrode.
  • First insulating layer As shown in FIG. 7, SiO 2 (Plasma Enhanced Chemical Vapor Deposition) is used to grow Si0 2 or SiN as a first insulating layer, and has a thickness of 100 to 300 nm. 6.
  • Second insulating layer As shown in FIG. 8, the first insulating layer is coated with benzocyclobutene (BCB), perfluorocyclobutane (PFBC), epoxy resin (Epoxy), silica gel (Silicone) or poly
  • An organic polymer material such as polyimide is used as the second insulating layer, and a second insulating layer planarization process is performed to make the surface of the second insulating layer flat, the first insulating layer and the second insulating layer. Make sure that the P- and n-electrodes remain insulated and secure the position of the protruding n-electrode.
  • Opening the electrode directly etching the first insulating layer and the second insulating layer without using an etch mask, for example, RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma) ). After the surface of the p_electrode and the n-electrode are exposed, in order to ensure good electrical conductivity, over-etching is performed, but less than the semiconductor (gp n -type gallium nitride layer 32), as shown in FIGS. 1 and 2. .
  • RIE Reactive Ion Etching
  • ICP Inductively Coupled Plasma
  • soldering (silver gel) 38 is applied to the upper surfaces of the first bonding metal layer 37 and the n-electrode, respectively, through the first bonding pad 39 and the second bonding pad, respectively. 40 is welded to the mounting table 41.
  • Example 2 Small size LED with etched shield
  • Opening the electrode using an etch mask, first coating a photosensitive material (photo glue) on the surface of the wafer, and placing a photomask over the wafer, the mask being provided with a pattern relative to the area of the insulating layer to be etched. Then, an exposure step is performed, so that the parallel light is selectively sensitized to the photosensitive material through the reticle, and then the pattern on the reticle is completely transferred to the wafer, and then developed and developed by exposure.
  • the photoresist obtains a pattern identical or complementary to the mask pattern, and the first insulating layer and the second insulating layer are dry etched.
  • Example 3 Large size LED, no etched shield
  • n-electrode first forming an ohmic contact layer of the n-electrode: forming an ohmic contact layer of the n-electrode on the n-type gallium nitride layer 32 by a photolithography process, the thickness of the ohmic contact layer being less than p - the sum of the electrode thickness and the etching depth, the material of the ohmic contact layer of the n-electrode may be an alloy of Cr and Au or an alloy of Ti and Au or an alloy of Ti and Al or an alloy of Ti, Al, Cr and Au; a second bonding metal layer of the n-electrode: a thickness (from the top of the P-electrode to the top of the ohmic contact layer of the n-electrode), forming a second bonding metal layer of the n-electrode by a photolithography process, The material of the second bonding metal layer may be titanium, nickel, gold (Au), copper (Cu
  • Electrode opening When over-etching, it is not as good as the ohmic contact layer of the n-electrode and less than the semiconductor.
  • Example 4 Large size LED with etched shield
  • Electrode opening Using etch shielding, first coating the surface of the wafer with photosensitive material (light glue), and A reticle is disposed above the wafer, and the reticle is provided with a pattern relative to the region where the insulating layer is to be etched, and then an exposure step is performed to selectively illuminate the photosensitive material through the reticle through the reticle, and then the reticle is mounted thereon. The pattern is completely transferred to the wafer. When exposed, the development is used to obtain the same or complementary pattern of the photoresist pattern, and then the first insulating layer and the second insulating layer are dry etched. When over-etching, it is not as good as the ohmic contact layer of the n-electrode and less than the semiconductor.
  • photosensitive material light glue

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Abstract

提供一种倒装悍发光二级管的制造方法，包括歩骤：提供一衬底（30），在衬底（30）上依次形成氮化镓缓冲层（31）和氮化镓发光二级管磊晶层，其中氮化镓发光二级管磊晶层包括依次设置的n型氮化镓层（32），发光层（33）和p型氮化镓层（34）；在p型氮化镓层（34）上形成p-电极；对未被p-电极覆盖的氮化镓发光二级管磊晶层进行干蚀刻，到达n型氮化镓层（32）；在n型氮化镓层（32）上形成n-电极；在p-电极，n型氮化镓层（32）和n-电极上形成绝缘层，使得绝缘层覆盖p-电极和n-电极；干蚀刻平坦化的绝缘层，露出p-电极和n-电极，但不及于半导体，将p-电极和n-电极悍接在安装台（41）上。如此能有效地增加氮化物倒装悍结合LED的出光量与发光效率。

Description

一种倒装焊发光二极管的制造方法 技术领域
本发明涉及一种倒装焊发光二极管的制造领域，特别涉及用于照明应用之经 III族氮化物倒装焊接合之发光二极管。
背景技术
最早氮化物 LED (发光二极管） 倒装焊封装使用金属突球 (Bump), 将晶粒 上的金属突球 (Bump)精准定位在一覆晶转接板 (Board)上的导电接点。 之后， 再 以微波等方式加热金属突球， 使晶粒与覆晶转接板电性连接。最后， 利用点胶技 术封装晶粒与覆晶转接板间的空隙， 至此完成一芯片之封装制作； 此外， 芯片通 常还需要再进行一次烘烤， 以固化点胶时填充之材料。 因为金属突球接触面积仍 小， 不完全符合功率 LED的散热及注入电流均匀性需求。 而且需要焊线机或覆 晶植球机、固晶机或表面黏着贴片机 (Surface Mounting Technology, SMT)等设备， 乃至于消耗性备料与覆晶转接板的支出。在制造成本及单位时间产能上皆不符需 求。
也有使用覆晶发光二极管晶粒的电极金属裸露面积以供直接涂布一导电接 合剂。绝缘层则位于第一电极层与第二电极层间， 以电性隔离且支撑第一电极层 与第二电极层。当导电接合剂选用银胶时，上述的裸露面积须至少 625平方微米， 以供直接涂布。当导电接合剂选用锡膏时， 上述的裸露面积须至少 10000平方微 米， 以供直接涂布。 当直接接合时， 两个电极的等平面特性对制程的良率是很重 要的，但出现的不良是两个电极其实并未达到真正的等平面， 或两个电极虽然达 到等平面， 但是有浪费发光面积； n半导体接触不良； P-电极下无反射层； 反射 层与奥姆层中隔着绝缘层， 所以反射率降低； P-电极面积小， 所以不符功率 LED 的散热及注入电流均匀性需求。
发明内容
发明目的： 针对上述现有技术存在的问题和不足， 本发明的目的是提供一种 倒装焊发光二极管的制造方法， 在直接接合时， 两个电极的上表面高度相同， 提 高制程良率， 不浪费发光面积； n半导体接触良好； 反射率高； P-电极面积大， 符合功率 LED的散热及注入电流均匀性需求。
技术方案： 为实现上述发明目的， 本发明采用的技术方案为一种倒装焊发光 二极管的制造方法， 包括如下步骤：
( 1 ) 提供一衬底， 并在所述衬底上依次形成氮化镓缓冲层和氮化镓发光二 极管磊晶层， 其中氮化镓发光二极管磊晶层包括依次设置的 n型氮化镓层、发光 层和 P型氮化镓层； ( 2 ) 在 p型氮化镓层上形成 p-电极；
( 3 )对未被 P-电极覆盖的氮化镓发光二极管磊晶层进行干蚀刻， 到达 n型 氮化镓层；
( 4) 在 n型氮化镓层上形成 n-电极；
( 5 )在 P-电极、 n型氮化镓层和 n-电极上形成绝缘层， 使得该绝缘层覆盖 P-电极和 n-电极；
( 6 ) 干蚀刻绝缘层， 露出 P-电极和 n-电极， 但不及于半导体；
( 7 ) 将 P-电极和 n-电极焊接在安装台上。
进一步地， 在所述步骤（6 ) 中， 使用蚀刻屏蔽， 使得仅 P-电极和 n-电极上 方部分区域的绝缘层被干蚀刻， 形成接触孔。
进一步地， 在所述步骤 （4) 中， 先在 n型氮化镓层上形成 n-电极的欧姆接 触层， 然后在 n-电极的欧姆接触层上形成第二接合金属层。
进一步地，所述 P-电极和 n-电极均利用微影蚀刻工艺控制形成电极的区域。 进一步地， 所述 P-电极和 n-电极的上表面高度相同。
进一步地， 所述 P-电极包括依次设置的第一透明导电层、 金属反射层和第 一接合金属层。 更进一步地， 所述第一透明导电层的材料为氧化镍和金的合金、 氧化铟锡、氧化锌或氧化铝锌， 用于与 p型氮化镓层形成欧姆接触； 所述金属反 射层的材料为镍、 钯、 铬、 铂、 铝或银， 用于反射氮化镓发光二极管磊晶层发出 的光及作为扩散阻碍层； 所述第一接合金属层的材料为金或金合金， 用于与安装 台接合。
进一步地， 所述绝缘层包括使用 PECVD形成材质为 Si02或 SiN的第一绝缘 层和被第一绝缘层包覆的有机高分子材质的第二绝缘层，第二绝缘层通过平坦化 工艺使得第二绝缘层的上表面平齐。
有益效果：本发明能有效增加氮化物倒装焊接合 LED的出光量与发光效率。 因为发光二极管的 n电极与 p电极高度相等， 发光二极管倒装焊时， 电极可以直 接连接焊垫， 不必使用凸块， 因此可以改善发光二极管的散热性与电流分布的 均匀性， 进而增加发光二极管的发光效率及使用寿命， 并减少光衰。
附图说明
图 1为实施例 1的倒装焊发光管的结构示意图 （不含安装台）， 图中横线区 为 n-电极， 斜线区为 P-电极；
图 2为图 1的 A-A' 剖视示意图；
图 3为实施例 1的第一步制程形成的结构示意图；
图 4为实施例 1的第二步制程形成的结构示意图； 图 5为实施例 1的第三步制程形成的结构示意图；
图 6为实施例 1的第四步制程形成的结构示意图；
图 7为实施例 1的第五步制程形成的结构示意图；
图 8为实施例 1的第六步制程形成的结构示意图；
图 9为实施例 1的倒装焊发光管的结构示意图 （含安装台）；
图 10为实施例 2的倒装焊发光管的结构示意图（不含安装台）， 图中横线区 为 n-电极， 斜线区为 P-电极；
图 11为图 11的 B-B' 剖视示意图；
图 12为实施例 3的倒装焊发光管的结构示意图（不含安装台）， 图中横线区 为 n-电极的欧姆接触层和 n-电极的第二接合金属层， 斜线区为 P-电极， 实黑区 为 n-电极的欧姆接触层；
图 13为图 12的 C-C' 剖视示意图；
图 14为图 12的 D-D' 剖视示意图；
图 15为实施例 4的倒装焊发光管的结构示意图（不含安装台）， 图中横线区 为 n-电极的欧姆接触层和 n-电极的第二接合金属层， 斜线区为 P-电极， 实黑区 为 n-电极的欧姆接触层；
图 16为图 15的 E-E' 剖视示意图；
图 17为图 15的 F-F' 剖视示意图。
具体实施方式
下面结合附图和具体实施例，进一步阐明本发明， 应理解这些实施例仅用于 说明本发明而不用于限制本发明的范围，在阅读了本发明之后， 本领域技术人员 对本发明的各种等价形式的修改均落于本申请所附权利要求所限定的范围。
由于 P型氮化镓层的高电阻率， LED的设计中 P-金属铺满发光区域， 以提供 P- 端较佳的电流分布。 因为蓝宝石衬底绝缘， N-端的电流扩散必须藉由 N型氮化镓 层。 N型氮化镓层典型的厚度是 2 微米， 片电阻约 10-3 Q cm。 要忽略不计这部分 电阻， 需要电流传导距离小于 200微米， 因此， 发光二极管比 400*400微米 2大时 (大尺寸发光二极管)， n-电极需要延伸出去， 形成多个须状， 以减少电阻。这种 结构增加倒装焊制程困难， 因为发光二极管倒装焊在安装台时， P-金属和 n-金 属必须保持绝缘。
实施例 1 : 小尺寸发光二极管， 无蚀刻屏蔽
1、 如图 3所示， 首先， 提供一基板， 基板的材质于本实施例中可例如为蓝宝 石 （sapphire)。 于衬底 30上依序形成氮化镓缓冲层 (GaN buff er layer) 31及氮 化镓发光二极管磊晶层。 氮化镓发光二极管磊晶层依序包含 n型氮化镓层 32、 多 层量子井主动层 (multi— quantum wel l active layer, MQW active layer, 即发 光层) 33以及 p型氮化镓层 34。
2、 p-电极： 利用一微影蚀刻（photol ithography)制程于 p型氮化镓层 34上形 成 P-电极。如图 4所示，利用蒸镀、溅镀或电镀技术，在 P型氮化镓层 (P— type GaN layer) 34上，依序形成第一透明导电层 35、金属反射层 36以及第一接合金属层 37， 该第一透明导电层 35、金属反射层 36以及第一接合金属层 37作为 P-电极。于本实 施例中，第一透明导电层 35之材料可例如为氧化镍和金的合金 (NiO/Au)、氧化铟 锡（Indium Tin Oxide, ITO)、 氧化锌（ΖηΟ)或氧化铝锌（Aluminum Zinc
Oxide, AlZnO) , 用以与半导体层形成欧姆接触（ohmic contact)； 金属反射层 36 之材料于本实施例中可例如为镍 (Ni)、钯 (Pd)、铬 (Cr)、铂 Pt、铝 (A1)或银 (Ag)， 用以反射氮化镓发光二极管磊晶层发出的光及作为扩散阻碍层 (diffusion barrier layer)； 第一接合金属层 37之材料于本实施例中可例如为金 (Au)或金合 金 (Au al loy) , 用以与安装台 41接合 （如图 9所示） 。
3、 做 GaN干蚀刻， 到达 n-GaN半导体。
以 P-电极为蚀刻硬屏蔽（hard mask) , 进行干式蚀刻（Dry Etching)又称电浆 蚀刻（Plasma Etching) , 系利用气体为主要的蚀刻媒介， 例如 C12/BC13， 并藉由 电浆能量来驱动反应， 干蚀刻 GaN， 到达 n-GaN半导体（δΡη型氮化镓层 32 )，如图 5所示。
另一执行方式是首先于晶圆的表面涂布感光材料 (光胶），并于晶圆上方放置 光罩， 该光罩上设有相对于蚀刻区与非蚀刻区之图形及数量的图案， 再进行曝光 (Exposure)步骤，使平行光经过光罩对感光材料进行选择性的感光， 于是光罩上 的图案便完整的转移至晶圆上， 当曝光后再利用显影 (Development) , 可使光阻 获得与光罩图案相同或互补之图形， 再进行干式蚀刻 (Dry Etching)又称电浆蚀 刻（Plasma Etching) , 系利用气体为主要的蚀刻媒介， 例如 C12/BC13， 并藉由电 浆能量来驱动反应，干蚀刻 GaN， 到达 n-GaN半导体，之后， 再移除晶圆上的光阻。
4、 n-电极： 量蚀刻厚度 (从 P-电极顶开始)， 利用一微影蚀刻
(photol ithography)制程于 n型氮化镓层 32上形成 n_电极。如图 6所示，利用蒸镀、 溅镀或电镀技术， 在 n型氮化镓层（n— type GaN layer) 32上， 镀 n_电极， n_电极 的材料为 Ti和 A1的合金或 Cr和 Au的合金或 Ti和 Au的合金或 Ti、 Al、 Cr和 Au的合 金，让 P-电极和 n-电极等高。
5、 第一绝缘层： 如图 7所示， 全面使用 PECVD ( Plasma Enhanced Chemical Vapor Deposition,等离子体增强化学气相沉积法）成长 Si02或 SiN作为第一绝缘层， 厚度为 100至 300纳米。 6、 第二绝缘层： 如图 8所示， 第一绝缘层包覆苯并环丁烯 (BCB)、 过氟环丁 垸 (PFBC)、 环氧树脂 (Epoxy)、 硅胶 (Silicone)或聚酰亚胺 （Polyimide)等有机高分 子材质做为第二绝缘层， 做第二绝缘层平坦化 （planarization) 工序， 使得第二 绝缘层的表面变得平整， 第一绝缘层和第二绝缘层确保 P-电极和 n-电极保持绝 缘， 并固定突出的 n-电极的位置。
7、 电极开窗： 不使用蚀刻屏蔽， 直接干蚀刻第一绝缘层和第二绝缘层， 例 如采用 RIE ( Reactive Ion Etching, 反应离子刻蚀） 或 ICP ( Inductively Coupled Plasma, 反应耦合等离子体刻蚀） 。 p_电极和 n-电极表面曝出后， 为确保导电效果 良好， 再过蚀刻 (over-etching), 但不及于半导体 （gpn型氮化镓层 32 ) ， 如图 1和 图 2所示。
8、倒装焊： 如图 9所示， 分别在第一接合金属层 37和 n-电极的上表面涂覆焊 锡 （银胶也可） 38， 分别通过第一焊垫 39和第二焊垫 40焊接在安装台 41上。
实施例 2: 小尺寸发光二极管， 有蚀刻屏蔽
如图 10和 11所示， 本实施例与实施例 1的不同在于：
7、 电极开窗： 使用蚀刻屏蔽， 首先于晶圆的表面涂布感光材料 (光胶)， 并于 晶圆上方放置光罩， 该光罩上设有相对于要蚀刻绝缘层区域的图案， 再进行曝光 (Exposure)步骤， 使平行光经过光罩对感光材料进行选择性的感光， 于是光罩上 的图案便完整的转移至晶圆上， 当曝光后再利用显影 (Development),可使光阻获 得与光罩图案相同或互补之图形， 再干蚀刻第一绝缘层和第二绝缘层。
实施例 3: 大尺寸发光二极管， 无蚀刻屏蔽
如图 12、 13和 14所示， 本实施例与实施例 1的不同在于：
4、 n-电极： 先形成 n-电极的欧姆接触层： 利用一微影蚀刻 (photolithography) 制程于 n型氮化镓层 32上形成 n-电极的欧姆接触层， 欧姆接触层的厚度小于 p-电 极厚度与蚀刻深度的和， n-电极的欧姆接触层的材料可以是 Cr和 Au的合金或 Ti 和 Au的合金或 Ti和 A1的合金或 Ti、 Al、 Cr和 Au的合金； 再形成 n-电极的第二接合 金属层： 量厚度 (从 P-电极顶开始到 n-电极的欧姆接触层顶)， 利用一微影蚀刻 (photolithography)制程形成 n-电极的第二接合金属层， 第二接合金属层的材料可 以是钛、 镍、 金 （Au)、 铜 (Cu)、 铝、 钯、 铟 (In)或锡 (Sn)， 第二接合金属层的顶 部与第一接合金属层 37的顶部平齐。
7、 电极开窗： 过蚀刻时， 不及于 n-电极的欧姆接触层且不及于半导体。 实施例 4: 大尺寸发光二极管， 有蚀刻屏蔽
如图 15、 16和 17所示， 本实施例与实施例 3的不同在于：
7、 电极开窗： 使用蚀刻屏蔽， 首先于晶圆的表面涂布感光材料 (光胶)， 并于 晶圆上方放置光罩， 该光罩上设有相对于要蚀刻绝缘层区域的图案， 再进行曝光 (Exposure)步骤， 使平行光经过光罩对感光材料进行选择性的感光， 于是光罩上 的图案便完整的转移至晶圆上， 当曝光后再利用显影 (Development),可使光阻获 得与光罩图案相同或互补之图形，再干蚀刻第一绝缘层和第二绝缘层。过蚀刻时， 不及于 n-电极的欧姆接触层且不及于半导体。

Claims

权 利 要 求 书
1、 一种倒装焊发光二极管的制造方法， 包括如下步骤：
( 1 ) 提供一衬底， 并在所述衬底上依次形成氮化镓缓冲层和氮化镓发光二 极管磊晶层， 其中氮化镓发光二极管磊晶层包括依次设置的 n型氮化镓层、发光 层和 P型氮化镓层；
( 2 ) 在 p型氮化镓层上形成 P-电极；
( 3 )对未被 P-电极覆盖的氮化镓发光二极管磊晶层进行干蚀刻， 到达 n型 氮化镓层；
( 4) 在 n型氮化镓层上形成 n-电极；
( 5 )在 P-电极、 n型氮化镓层和 n-电极上形成绝缘层， 使得该绝缘层覆盖 P-电极和 n-电极；
( 6 ) 干蚀刻绝缘层， 露出 P-电极和 n-电极， 但不及于半导体；
( 7 ) 将 P-电极和 n-电极焊接在安装台上。
2、 根据权利要求 1所述一种倒装焊发光二极管的制造方法， 其特征在于： 在所述步骤（6 ) 中， 使用蚀刻屏蔽， 使得仅 P-电极和 n-电极上方部分区域 的绝缘层被干蚀刻， 形成接触孔。
3、 根据权利要求 1所述一种倒装焊发光二极管的制造方法， 其特征在于： 在所述步骤（4) 中， 先在 n型氮化镓层上形成 n-电极的欧姆接触层， 然后在 n- 电极的欧姆接触层上形成第二接合金属层。
4、 根据权利要求 1所述一种倒装焊发光二极管的制造方法， 其特征在于： 所述 P-电极和 n-电极均利用微影蚀刻工艺控制形成电极的区域。
5、 根据权利要求 1所述一种倒装焊发光二极管的制造方法， 其特征在于： 所述 P-电极和 n-电极的上表面高度相同。
6、 根据权利要求 1所述一种倒装焊发光二极管的制造方法， 其特征在于： 所述 P-电极包括依次设置的第一透明导电层、 金属反射层和第一接合金属层。
7、 根据权利要求 6所述一种倒装焊发光二极管的制造方法， 其特征在于： 所述第一透明导电层的材料为氧化镍和金的合金、氧化铟锡、氧化锌或氧化铝锌， 用于与 P型氮化镓层形成欧姆接触； 所述金属反射层的材料为镍、 钯、 铬、 铂、 铝或银， 用于反射氮化镓发光二极管磊晶层发出的光及作为扩散阻碍层； 所述第 一接合金属层的材料为金或金合金， 用于与安装台接合。
8、 根据权利要求 1所述一种倒装焊发光二极管的制造方法， 其特征在于： 所述绝缘层包括使用 PECVD形成材质为 Si02或 SiN的第一绝缘层和被第一绝缘 层包覆的有机高分子材质的第二绝缘层，第二绝缘层通过平坦化工艺使得第二绝 缘层的上表面平齐。
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