WO2013155845A1 - Procédé de fabrication d'un substrat de matrice, substrat de matrice, et dispositif d'affichage - Google Patents

Procédé de fabrication d'un substrat de matrice, substrat de matrice, et dispositif d'affichage Download PDF

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Publication number
WO2013155845A1
WO2013155845A1 PCT/CN2012/085967 CN2012085967W WO2013155845A1 WO 2013155845 A1 WO2013155845 A1 WO 2013155845A1 CN 2012085967 W CN2012085967 W CN 2012085967W WO 2013155845 A1 WO2013155845 A1 WO 2013155845A1
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WIPO (PCT)
Prior art keywords
electrode
gate
layer
data line
substrate
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PCT/CN2012/085967
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English (en)
Chinese (zh)
Inventor
金玟秀
邓立赟
周纪登
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Publication of WO2013155845A1 publication Critical patent/WO2013155845A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer

Definitions

  • Embodiments of the present invention relate to a method of fabricating an array substrate, an array substrate, and a display device. Background technique
  • Thin film transistor liquid crystal displays have a small size, low power consumption, and no radiation, and they dominate the current flat panel display market.
  • the advanced super-dimensional field switching technology uses a field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer to form a multi-dimensional electric field, so that the liquid crystal cell is narrow. All the aligned liquid crystal molecules between the electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field switching technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • FIG. 1 is a cross-sectional view showing an array substrate of a prior art ADS mode liquid crystal display. As shown in FIG. 1, in the array substrate, a gate electrode 2 is formed on a substrate 1, a gate insulating layer 4 is formed on the gate electrode 2, and a semiconductor layer 5, a source electrode 6 and a drain electrode are formed on the gate insulating layer 4.
  • the pixel electrode 12 is formed on the gate insulating layer 4 and electrically connected to the drain electrode 7, and the common electrode 16 is formed on the protective film 13, a gate line (not shown) and a data line 8 defines a pixel region, a gate pad 3 is formed on the substrate 1, and a data pad 9 is formed on the gate insulating layer 4.
  • a portion of the common electrode 162 is formed over the data line 8.
  • a technical problem to be solved by embodiments of the present invention is to provide a method for fabricating an array substrate, an array substrate, and a display device to reduce signal delay on a data line in the array substrate.
  • Embodiments of the present invention provide an array substrate including a display area and a non-display area, the display area including a gate line, a data line, and a plurality of pixel units defined by the gate line and the data line, each of which
  • the pixel unit includes a thin film transistor, a pixel electrode, and a common electrode, and an organic insulating film is disposed between the pixel electrode and the data line.
  • the embodiment of the invention further provides a method for manufacturing an array substrate, comprising:
  • a pixel electrode is formed on the substrate on which the organic insulating film is formed, and the pixel electrode is electrically connected to the drain electrode through the first contact hole.
  • the embodiment of the invention further provides a display device comprising the above array substrate.
  • the technical solution of the embodiment of the present invention reduces the parasitic capacitance between the common electrode and the data line by applying a low dielectric constant organic insulating film to the array substrate, thereby reducing signal delay on the data line and improving display quality.
  • the technical solution of the present invention can also reduce the process time and reduce the manufacturing cost.
  • FIG. 1 is a cross-sectional view of an array substrate of a prior art ADS mode liquid crystal display
  • FIG. 2 to FIG. 13 are cross-sectional views of an array substrate in a method of fabricating an array substrate according to an embodiment of the present invention
  • Figure 14 is a cross-sectional view of an array substrate in accordance with an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide an array substrate including a display area including a gate line, a data line, and a plurality of pixel units between the gate line and the data line, wherein the non-display area includes a gate a pad and a data pad, wherein the pixel unit includes a thin film transistor, a pixel electrode, and a common electrode, wherein the pixel electrode is connected to a drain electrode of the thin film transistor, wherein the common electrode includes a pixel electrode a first common electrode and a second common electrode located above the data line; a protective film is disposed between the layer where the common electrode is located and the layer where the pixel electrode is located; between the pixel electrode and the data line, and An organic insulating film is disposed between the thin film transistor and the protective film.
  • the technical solution of the embodiment of the present invention reduces the parasitic capacitance between the common electrode and the data line by applying a low dielectric constant organic insulating film to the array substrate, thereby reducing signal delay on the data line and improving display quality.
  • the substrate structure of the array substrate may be set according to actual conditions, for example, the thin film transistor may be a top gate structure or a bottom gate structure; a connection manner of the pixel electrode and the drain electrode It may be a lap joint, a through-hole connection, or the like, which is not limited herein.
  • the thin film transistor may be a top gate structure or a bottom gate structure; a connection manner of the pixel electrode and the drain electrode It may be a lap joint, a through-hole connection, or the like, which is not limited herein.
  • the following is an exemplary example of an array substrate, which is a technical method of an embodiment of the present invention. The case is explained.
  • Figure 14 is a cross-sectional view of an array substrate in accordance with an embodiment of the present invention.
  • the array substrate may include: a substrate 1; a gate electrode 2, a gate line (not shown), and a gate pad 3 formed on the substrate 1; a gate insulating layer 4 formed on the gate electrode 2 and the gate line
  • the semiconductor layer 5, the data line 8 and the data pad 9, are formed on the gate insulating layer 4; the source electrode 6 and the drain electrode 7 are formed on the semiconductor layer 5; the organic insulating film 10 is formed at the source electrode 6, and the drain electrode
  • a first contact hole 11 is formed in the organic insulating film 10; a pixel electrode 12 is formed on the organic insulating film 10, and the pixel electrode 12 passes through the first contact hole 11 and the drain electrode 7 Electrically connected; a protective film 13 formed on the pixel electrode 12 and the organic insulating film 10; a common electrode 16 formed on the protective film 13, the common electrode 16 including the first common electrode 161
  • the data line 8 can be reduced by applying the low dielectric constant (2.0 to 4.0) of the organic insulating film 10 to the array substrate to reduce the parasitic capacitance between the common electrode 162 and the data line 8. Signal delay on the board to improve display quality.
  • the embodiment of the present invention can also reduce the process time and reduce the manufacturing cost as compared with the prior art by reducing the thickness of the protective film 13 to reduce the parasitic capacitance.
  • the organic insulating film 10 having a low dielectric constant since the organic insulating film 10 having a low dielectric constant is used, it is also possible to reduce the horizontal direction (i.e., the direction parallel to the substrate 1) between the pixel electrode 12 and the data line 8 The distance is increased to increase the aperture ratio of the pixel, wherein the distance between the pixel electrode 12 and the data line 8 in the direction parallel to the substrate 1 can be reduced to 0 to 1 ⁇ .
  • the material of the organic insulating film 10 may be made of polyacrylic acid or an organic insulating film.
  • the thickness of 10 can be 10,000 to 40,000 ⁇ . If the thickness of the organic insulating film 10 is too small, the parasitic capacitance is not significantly reduced; if the thickness of the organic insulating film 10 is too large, the interlayer step portion will more likely cause a defect in the pixel electrode to be broken. When the thickness of the organic insulating film 10 is 10,000 40000 A, the above two problems can be well balanced, and the effect of reducing the parasitic capacitance can be better achieved on the basis of ensuring the yield. In addition to polyacrylic acid, the organic insulating film 10 can also be used with other organic materials having similar dielectric coefficients. Material.
  • the protective film 13 may be made of an inorganic insulating material such as silicon nitride or the like, and has a thickness of 2000 4000 A; of course, a suitable organic material such as a transparent resin or the like may also be used.
  • the semiconductor layer may be left under the data line (as shown in FIG. 13), or the semiconductor layer may not be retained (as shown in FIG. 14); the source electrode and/or the drain electrode may be completely located above the semiconductor layer ( As shown in FIG. 13), it is also possible to extend to a region other than the semiconductor layer (as shown in FIG. 14).
  • the semiconductor layer 5 may be a normal silicon semiconductor (intrinsic semiconductor or doped semiconductor), an organic semiconductor, or an oxide semiconductor.
  • the common electrode 16 may be in the shape of a slit, and the pixel electrode 12 may be in the form of a plate or a slit.
  • the embodiment of the invention further provides a display device, which comprises any of the array substrates described above.
  • the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.
  • Step S11 providing a substrate, forming a gate line, a gate electrode and a gate pad on the substrate; specifically, first, sputtering, thermal evaporation or other film forming method may be used on the glass substrate or other type of transparent substrate
  • the gate metal layer may be made of chromium (Cr), molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), niobium (Nd) or alloys thereof, and the gate metal layer may be One or more layers; then, a photoresist is formed on the gate metal layer; then, the photoresist is exposed and developed by using a patterned mask to form a photoresist mask; then, photolithography is used The glue mask etches the gate metal layer to form a pattern of gate lines, gate electrodes, and gate pads; finally, the remaining photoresist is stripped.
  • the common electrode lines may be formed while forming the patterns of the gate lines, the gate
  • Step S12 forming a gate insulating layer on the substrate completing step S11;
  • a gate insulating layer 4 having a thickness of 2000 8000 A may be deposited on the substrate 1 on which step S11 is completed by plasma enhanced chemical vapor deposition (PECVD) or the like.
  • the gate insulating layer 4 may be made of an oxide (e.g., SiOx) or a nitride (e.g., SiNx).
  • Step S13 forming a semiconductor layer on the substrate on which step S12 is completed; Specifically, as shown in FIG. 3, first, a semiconductor material layer having a thickness of 1000 4000 A may be formed on the substrate 1 on which step S12 is completed by a method such as PECVD; then, a photoresist is formed on the semiconductor material layer; Etching and developing the photoresist with a patterned mask to form a photoresist mask; next, etching the semiconductor material layer with a photoresist mask to form a pattern of the semiconductor layer 5; , peel off the remaining photoresist.
  • PECVD PECVD
  • Step S14 forming a source electrode, a drain electrode, a data line and a data pad on the substrate completing step S13;
  • a source/drain metal layer having a thickness of 1000 to 6000 A may be formed on the substrate 1 on which the step S13 is completed by using sputtering, thermal evaporation or other film forming methods, and the source/drain metal layer may be used.
  • the source and drain metal layers may be one or more layers; Forming a photoresist on the source/drain metal layer; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; next, using a photoresist mask to the source The drain metal layer is etched to form a pattern of the source electrode 6, the drain electrode 7, the data line 8 and the data pad 9; finally, a portion of the semiconductor layer 5 between the source electrode 6 and the drain electrode 7 is etched away, and The remaining photoresist is stripped to complete the channel of the thin film transistor.
  • Cr chromium
  • Mo molybdenum
  • Al aluminum
  • Cu copper
  • W tungsten
  • Nd niobium
  • etching away a portion of the semiconductor layer 5 between the source electrode 6 and the drain electrode 7 mainly means etching The ohmic contact layer between the source electrode 6 and the drain electrode 7 is dropped; and when the semiconductor layer 5 is an organic semiconductor or an oxide semiconductor, "etching away a portion of the semiconductor layer 5" is mainly due to etching of the source and drain metal layer Due to the etching, it is not necessary to etch away a part of the semiconductor layer 5, and it is only necessary to ensure that the source and drain metal layers of the channel region are completely etched away.
  • Step S15 forming an organic insulating film on the substrate on which step S14 is completed, and patterning the organic insulating film;
  • an organic insulating film 10 having a thickness of 10000-40000 A is formed on the substrate 1 on which the step S14 is completed, and the organic insulating film 10 can be made of an organic photosensitive material such as polyacrylic acid;
  • the organic insulating film is exposed and developed by a patterned mask to form a first contact hole 11 and expose the gate insulating layer 4 and the gate pad 9 at positions corresponding to the data pad 3; finally, the organic insulating film 10 Curing (Cure) treatment.
  • the thickness of the organic insulating film 10 is too small, the effect of reducing the parasitic capacitance between the subsequent common electrode and the data line (relative to the inorganic insulating film) is not significant; if the organic insulating film If the thickness of 10 is too high, the slope of the step between the layers may increase, which may cause defects such as disconnection of the pixel electrode.
  • the curing temperature may be 230 to 260 ° C and the time may be 30 to 60 minutes. If the curing temperature is lower than 230 ° C, the micro-cure of the protective film may cause contamination and film lift, etc.; if the curing temperature is higher than 260 ° C, the organic insulating film 10 may be denatured, thereby This makes the transmission rate low.
  • Step S16 forming a pixel electrode on the substrate of step S15, wherein the pixel electrode is electrically connected to the drain electrode through the first contact hole;
  • a transparent conductive layer having a thickness of 100 lOOOA may be formed on the substrate 1 on which the step S15 is completed by using magnetron sputtering, thermal evaporation, or other film forming methods, and the transparent conductive layer may be ⁇ using indium tin oxide (ITO), indium oxide ( ⁇ ) or alumina, etc.; then, forming a photoresist on the transparent conductive layer; then, using a patterned mask to expose the photoresist And developing, forming a photoresist mask; next, etching the transparent conductive layer with a photoresist mask to form a pattern of the pixel electrode 12, the pixel electrode 12 passing through the first contact hole 11 and leakage
  • the pole 7 is electrically connected; thereafter, the exposed gate insulating layer 4 is etched away with a photoresist mask to expose the gate pad 3; finally, the remaining photoresist is stripped.
  • the pixel electrode may be in the form of
  • Fig. 7 is a cross-sectional view of the array substrate after forming the pixel electrode according to the prior art
  • the right half is a cross-sectional view of the array substrate after forming the pixel electrode according to an embodiment of the present invention.
  • the distance between the pixel electrode 12 and the data line 8 is dl. It is required to be larger, generally about 2 ⁇ , which results in a decrease in the aperture ratio of the pixel.
  • the organic insulating mold 10 since the organic insulating mold 10 is used, even between the pixel electrode 12 and the data line 8 The distance d2 in the horizontal direction is made smaller, and the parasitic capacitance between the pixel electrode and the data line is not too large. Therefore, the distance d2 can be reduced to 0 to 1 ⁇ m to increase the aperture ratio of the pixel.
  • Step S17 forming a protective film on the substrate on which step S16 is completed, and patterning the protective film; specifically, as shown in FIG. 8, first, a thickness of the substrate 1 on which the step S16 is completed may be formed by a method such as PECVD. 2000 4000 ⁇ protective film 13 , which can use SiNx Or a material such as SiOx; then, forming a photoresist on the protective film 13; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; The mask mask etches the protective film 13 to form second contact holes 14 and third contact holes 15 to expose the gate pads 3 and the data pads 9, respectively; finally, the remaining photoresist is stripped.
  • the thickness of the protective film 13 is less than 2000 A, the storage capacitor (Cst) rises, causing an increase in signal delay; if the thickness of the protective film 13 is larger than 4000 A, the process time and manufacturing cost are excessively high.
  • Step S18 forming a common electrode, a gate pad electrode, and a data pad electrode on the substrate on which the step S17 is completed.
  • a transparent conductive layer having a thickness of 100 lOOOA may be formed on the substrate 1 on which the step S17 is completed by using magnetron sputtering, thermal evaporation or other film forming methods, and the transparent conductive layer may be ⁇ using indium tin oxide (ITO), indium oxide ( ⁇ ) or alumina, etc.; then, forming a photoresist on the transparent conductive layer; then, using a patterned mask to expose the photoresist And developing, forming a photoresist mask; next, etching the transparent conductive layer with a photoresist mask to form a pattern of the common electrode 16, the gate pad electrode 17, and the data pad electrode 18; finally, stripping Remaining photoresist.
  • ITO indium tin oxide
  • ⁇ indium oxide
  • alumina etc.
  • the common electrode 16 may include a first common electrode 161 located above the pixel electrode 12 and a second common electrode 162 located above the data line 8.
  • the common electrode 16 may have a slit shape.
  • the gate pad electrode 17 is electrically connected to the gate pad 3 through the second contact hole 14, and the data pad electrode 18 is electrically connected to the data pad 9 through the third contact hole 15.
  • the second common electrode 162 is located above the data line 8, and can shield the electromagnetic field between the pixel electrode 12 and the data line 8, thereby reducing the width of the black matrix on the color filter, thereby being able to increase The aperture ratio of the pixel.
  • Step S21 providing a substrate, forming a gate line, a gate electrode and a gate pad on the substrate; specifically, first, sputtering, thermal evaporation or other film forming method may be used on the glass substrate or other type of transparent substrate
  • the gate metal layer may be made of chromium (Cr), molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), niobium (Nd) and alloys thereof, and the gate metal layer may be One a layer or a plurality of layers; then, forming a photoresist on the gate metal layer; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; The glue mask etches the gate metal layer to form a pattern of gate lines, gate electrodes, and gate pads; finally, the remaining photoresist is stripped.
  • the common electrode lines may be formed while forming the patterns of the gate lines, the gate electrode
  • Step S22 forming a gate insulating layer on the substrate on which step S21 is completed;
  • a gate insulating layer 4 having a thickness of 2000 8000 A may be deposited on the substrate 1 on which step S21 is completed by plasma enhanced chemical vapor deposition (PECVD) or the like.
  • the gate insulating layer 4 may be selected from an oxide (e.g., SiOx) or a nitride (e.g., SiNx).
  • Step S23 forming a semiconductor material layer on the substrate completing step S22;
  • a semiconductor material layer 20 having a thickness of 1000 4000 A can be formed on the substrate 1 on which step S22 is completed by a method such as PECVD.
  • Step S24 forming a source/drain metal layer on the substrate of step S23;
  • a source/drain metal layer having a thickness of 1000 6000 A may be formed on the substrate 1 on which the step S24 is completed by using sputtering, thermal evaporation or other film forming method, and the source/drain metal layer may be made of chromium (Cr) or molybdenum. (Mo), aluminum (Al), copper (Cu), tungsten (W), niobium (Nd) or an alloy thereof, and the source/drain metal layer may be one or more layers.
  • Step S25 forming a photoresist mask on the substrate completing step S24;
  • a photoresist layer 19 is formed on the source/drain metal layer; then, the photoresist layer 19 is exposed and developed by using a gray tone or halftone mask patterned with a pattern, A photoresist mask including a photoresist completely reserved region, a photoresist portion remaining region, and a photoresist unretained region is formed.
  • Step S26 forming a pattern of the data line and the data pad
  • the source/drain metal layer of the unretained region of the photoresist is etched by a photoresist mask to form a pattern of the data line 8 and the data pad 9.
  • Step S27 etching a semiconductor material layer in the unreserved region of the photoresist, and performing an ashing process; specifically, as shown in FIG. 12, first, using a photoresist mask to the semiconductor material in the unreserved region of the photoresist The layer 20 is etched to form a pattern of the semiconductor layer 5; then, the photoresist in the remaining portion of the photoresist is removed by an ashing process, and the photoresist in the completely remaining region of the photoresist is thinned to form a new photoresist.
  • Mask forming a pattern of the source electrode and the drain electrode;
  • the exposed source/drain metal layer is etched by a photoresist mask to form a pattern of the source electrode 6 and the drain electrode 7; then, the source electrode 6 and the drain electrode 7 are etched away. A portion of the semiconductor layer 5 is interposed and the remaining photoresist is stripped to form a channel of the thin film transistor.
  • etching away a portion of the semiconductor layer 5 between the source electrode 6 and the drain electrode 7 mainly means etching The ohmic contact layer between the source electrode 6 and the drain electrode 7 is dropped; and when the semiconductor layer 5 is an organic semiconductor or an oxide semiconductor, "etching away a portion of the semiconductor layer 5" is due to etching of the source and drain metal layer Therefore, it is not necessary to intentionally etch away a portion of the semiconductor layer 5, and it is only necessary to ensure that the source and drain metal layers of the channel region are completely etched away.
  • Step S29 forming an organic insulating film on the substrate on which step S28 is completed, and patterning the organic insulating film;
  • a thickness is formed on the substrate 1 which is completed in step S28.
  • the organic insulating film 10 can be coated with an organic photosensitive material such as polyacrylic acid; then, the organic insulating film is exposed and developed by using a patterned mask to form a first contact hole 11, The gate insulating layer 4 and the gate pad 9 at the data pad 3 are exposed; finally, the organic insulating film 10 is subjected to a curing (Cure) process.
  • an organic photosensitive material such as polyacrylic acid
  • the thickness of the organic insulating film 10 is too small, the effect of reducing the parasitic capacitance between the subsequent common electrode and the data line (relative to the inorganic insulating film) is not significant; if the thickness of the organic insulating film 10 is too large , the slope of the step between the layers will increase, which may cause defects such as disconnection of the pixel electrode.
  • the curing temperature can be 230 ⁇ 260 °C, and the processing time can be 30 ⁇ 60 minutes. If the curing temperature is lower than 230 ° C, the micro-cure of the protective film may cause contamination and film lift, etc.; if the curing temperature is higher than 260 ° C, the organic insulating film 10 may be denatured, thereby This makes the transmission rate low.
  • Step S30 forming a pixel electrode on the substrate completing step S29, the pixel electrode being electrically connected to the drain electrode through the first contact hole;
  • a transparent conductive layer having a thickness of 100 lOOOA formed on the substrate 1 of the step S29 the transparent conductive layer may be made of indium tin oxide (ITO), indium oxide ( ⁇ ) or alumina, etc.; Forming a photoresist on the transparent conductive layer; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; next, using a photoresist mask to perform the transparent conductive layer Etching, forming a pattern of the pixel electrode 12, the pixel electrode 12 is electrically connected to the drain electrode 7 through the first contact hole 11; thereafter, the exposed gate insulating layer 4 is etched away by a photoresist mask to expose the gate soldering Disk 3; Finally, the remaining photoresist is stripped.
  • the pixel electrode may have a plate shape or a
  • Fig. 7 is a cross-sectional view of the array substrate after completion of the pixel electrode according to the prior art
  • the right half is a cross-sectional view of the array substrate after completion of the pixel electrode according to an embodiment of the present invention.
  • the distance between the pixel electrode 12 and the data line 8 is dl. It is required to be larger, generally about 2 ⁇ , which causes the aperture ratio of the pixel to decrease.
  • the distance d2 is made smaller, and the parasitic capacitance between the pixel electrode and the data line is not too large. Therefore, the distance d2 can be reduced to 0 ⁇ 1 ⁇ ⁇ to increase the aperture ratio of the pixel.
  • Step S31 forming a protective film on the substrate on which step S30 is completed, and patterning the protective film; specifically, as shown in FIG. 8, first, a thickness of the substrate 1 on which the step S30 is completed may be formed by a method such as PECVD. 2000 4000 ⁇ protective film 13, the protective mold 13 can be made of SiNx or SiOx; then, a photoresist is formed on the protective film 13; then, the photoresist is exposed and developed by using a patterned mask. Forming a photoresist mask; next, etching the protective film 13 with a photoresist mask to form a second contact hole 14 and a third contact hole 15 to expose the gate pad 3 and the data pad 9, respectively Finally, strip the remaining photoresist.
  • a thickness of the substrate 1 on which the step S30 is completed may be formed by a method such as PECVD. 2000 4000 ⁇ protective film 13, the protective mold 13 can be made of SiNx or SiOx; then, a photoresist is formed on the
  • the thickness of the protective film 13 is less than 2000 A, the storage capacitor (Cst) rises, causing an increase in signal delay; if the thickness of the protective film 13 is larger than 4000 A, the process time and manufacturing cost are excessively high.
  • Step S32 forming a common electrode, a gate pad electrode, and a data pad electrode on the substrate on which step S31 is completed.
  • a transparent conductive layer having a thickness of 100 lOOOA may be formed on the substrate 1 on which the step S32 is completed by using magnetron sputtering, thermal evaporation or other film forming methods, and the transparent conductive layer may be ⁇ using indium tin oxide (ITO), indium oxide ( ⁇ ) or alumina, etc.; then, forming a photoresist on the transparent conductive layer; then, using a patterned mask to expose the photoresist And developing, forming a photoresist mask; next, etching the transparent conductive layer with a photoresist mask to form a pattern of the common electrode 16, the gate pad electrode 17, and the data pad electrode 18; finally, stripping Remaining photoresist.
  • ITO indium tin oxide
  • ⁇ indium oxide
  • alumina alumina
  • the common electrode 16 may include a first common electrode 161 located above the pixel electrode 12 and a second common electrode 162 located above the data line 8.
  • the gate pad electrode 17 may be electrically connected to the gate pad 3 through the second contact hole 14, and the data pad electrode 18 may be electrically connected to the data pad 9 through the third contact hole 15.
  • the second common electrode 162 is located above the data line 8, and can shield the electromagnetic field between the pixel electrode 12 and the data line 8, thereby reducing the width of the black matrix on the color filter, thereby increasing The aperture ratio of the pixel. Further, in forming the semiconductor layer 5, the source electrode 6, and the drain electrode 7, since the ashing process is used, the number of masks can be reduced, thereby reducing the manufacturing cost.
  • An array substrate comprising a display area including a gate line, a data line, and a plurality of pixel units defined by the gate line and the data line, each of the pixel unit A thin film transistor, a pixel electrode, and a common electrode are disposed, wherein an organic insulating film is disposed between the pixel electrode and the data line.
  • a gate electrode of the thin film transistor and the gate line are formed on a substrate;
  • a gate insulating layer is formed on the gate electrode and the gate line;
  • a semiconductor layer and the data line are formed on the gate insulating layer
  • a source electrode and a drain electrode of the thin film transistor are formed on the semiconductor layer;
  • the organic insulating film is formed on the source electrode, the drain electrode, the data line, and the semiconductor layer, and a first contact hole is formed in the organic insulating film;
  • the pixel electrode is formed on the organic insulating film, and the pixel electrode passes through the first connection a contact hole is electrically connected to the drain electrode;
  • the common electrode is formed on the protective film, and the common electrode includes a first common electrode positioned above the pixel electrode and a second common electrode positioned above the data line.
  • a data pad in the non-display area and in the same layer as the data line; a gate pad electrode formed on the protective film and at a position corresponding to the gate pad, the gate pad The electrode is electrically connected to the gate pad through a second contact hole, the second contact hole passing through the organic insulating film and the protective film;
  • a data pad electrode formed on the protective film and at a position corresponding to the data pad, the data pad electrode being electrically connected to the data pad through a third contact hole, the third contact hole being worn
  • the organic insulating film and the protective film are passed through.
  • the distance between the pixel electrode and the data line in the horizontal direction is 0 ⁇ 1 ⁇ .
  • the material of the organic insulating film is polyacrylic acid.
  • the organic insulating film has a thickness of 10,000 to 40,000 ⁇ .
  • the protective film is made of an inorganic insulating material and has a thickness of 2000 to 4000 ⁇ .
  • a method of manufacturing an array substrate comprising:
  • a pixel electrode is formed on the substrate on which the organic insulating film is formed, and the pixel electrode is electrically connected to the drain electrode through the first contact hole.
  • a common electrode, a gate pad electrode, and a data pad electrode on the substrate on which the protective film is formed, the common electrode including a first common electrode above the pixel electrode and a second common electrode above the data line
  • the gate pad electrode is electrically connected to the gate pad through a second contact hole
  • the data pad electrode is electrically connected to the data pad through the third contact hole.
  • the organic insulating film is subjected to a curing treatment, the curing treatment temperature is 230 to 260 ° C, and the curing treatment is carried out for 30 to 60 minutes.
  • the pixel electrode and the data line have a distance of 0 to 1 ⁇ m in a direction parallel to the substrate.
  • the material of the organic insulating film is polyacrylic acid.
  • the organic insulating film has a thickness of 10,000 to 40,000 ⁇ .
  • the protective film is made of an inorganic insulating material and has a thickness of 2000 to 4000A.
  • Patterning the layer of semiconductor material to form a semiconductor layer Forming a metal layer on the substrate on which the semiconductor layer is formed;
  • the metal layer is patterned to form a source electrode, a drain electrode, a data line, and a data pad, and a semiconductor layer between the source electrode and the drain electrode forms a channel.
  • a portion of the metal layer and the layer of semiconductor material in the remaining portion of the photoresist portion is etched away.
  • a display device comprising the array substrate according to any one of (1) to (8).

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention se rapporte à un procédé de fabrication d'un substrat de matrice, à un substrat de matrice et à un dispositif d'affichage. Le substrat de matrice peut comprendre une zone d'affichage et une zone de non-affichage. La zone d'affichage comprend une ligne de grille, une ligne de données (8) et de multiples unités de pixel définies par la ligne de grille et par la ligne de données (8). Chaque unité de pixel peut comprendre un transistor à couches minces, une électrode de pixel (12) et une électrode commune (16). L'électrode de pixel (12) est raccordée à une électrode déversoir (7) du transistor à couches minces. Un film isolant organique (10) peut être agencé entre l'électrode de pixel (12) et la ligne de données (8). Le substrat de matrice peut réduire les retards du signal sur la ligne de données (8) dans le substrat de matrice et augmenter le rapport d'ouverture des pixels.
PCT/CN2012/085967 2012-04-20 2012-12-05 Procédé de fabrication d'un substrat de matrice, substrat de matrice, et dispositif d'affichage WO2013155845A1 (fr)

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CN201210119293.6 2012-04-20

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CN103117284A (zh) * 2013-02-01 2013-05-22 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN103487999B (zh) 2013-05-24 2016-03-02 合肥京东方光电科技有限公司 一种阵列基板、制备方法以及显示装置
CN103336396B (zh) * 2013-06-28 2016-03-23 京东方科技集团股份有限公司 阵列基板及其制造方法和显示装置
KR102198111B1 (ko) 2013-11-04 2021-01-05 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
CN103681488A (zh) * 2013-12-16 2014-03-26 合肥京东方光电科技有限公司 阵列基板及其制作方法，显示装置
CN103745980B (zh) * 2014-01-28 2017-02-15 昆山龙腾光电有限公司 薄膜晶体管阵列基板及其制作方法及液晶显示装置
CN103824866A (zh) * 2014-03-03 2014-05-28 深圳市华星光电技术有限公司 一种阵列基板及其制备方法、液晶显示面板
CN103928400A (zh) * 2014-03-31 2014-07-16 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104600030B (zh) * 2015-02-02 2017-08-29 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104698630B (zh) * 2015-03-30 2017-12-08 合肥京东方光电科技有限公司 阵列基板及显示装置
CN104898335B (zh) * 2015-07-09 2018-10-19 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
CN105575978A (zh) * 2016-02-25 2016-05-11 昆山龙腾光电有限公司 薄膜晶体管阵列基板及其制造方法以及液晶显示装置
CA3019219A1 (fr) * 2016-07-25 2018-02-01 Shenzhen Royole Technologies Co., Ltd. Procede de fabrication de substrat de matrice
CN106298647B (zh) 2016-08-31 2017-12-19 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板及其制备方法
CN106783747A (zh) * 2017-01-03 2017-05-31 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置
CN106684155B (zh) 2017-01-05 2021-03-30 京东方科技集团股份有限公司 双栅薄膜晶体管及其制备方法、阵列基板及显示装置
CN107024813B (zh) * 2017-06-06 2020-10-02 厦门天马微电子有限公司 阵列基板、液晶显示面板及显示装置
CN110412805A (zh) * 2019-07-29 2019-11-05 昆山龙腾光电有限公司 阵列基板及其制作方法、液晶显示装置
WO2021226868A1 (fr) * 2020-05-13 2021-11-18 京东方科技集团股份有限公司 Substrat d'attaque, procédé de fabrication associé, et appareil d'affichage

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