WO2013155830A1 - Procédé de fabrication d'un substrat de matrice, substrat de matrice, et dispositif d'affichage - Google Patents

Procédé de fabrication d'un substrat de matrice, substrat de matrice, et dispositif d'affichage Download PDF

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Publication number
WO2013155830A1
WO2013155830A1 PCT/CN2012/083889 CN2012083889W WO2013155830A1 WO 2013155830 A1 WO2013155830 A1 WO 2013155830A1 CN 2012083889 W CN2012083889 W CN 2012083889W WO 2013155830 A1 WO2013155830 A1 WO 2013155830A1
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WO
WIPO (PCT)
Prior art keywords
electrode
insulating film
gate
layer
substrate
Prior art date
Application number
PCT/CN2012/083889
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English (en)
Chinese (zh)
Inventor
金玟秀
邓立赟
周纪登
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2013155830A1 publication Critical patent/WO2013155830A1/fr

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • Embodiments of the present invention provide an array substrate including a display area and a non-display area, the display area including a gate line, a data line, and a plurality of pixel units defined by the gate line and the data line, wherein each The pixel unit includes a thin film transistor, a pixel electrode, and a common electrode, the pixel electrode being electrically connected to a drain electrode of the thin film transistor, wherein an inorganic insulating film is formed on the data line and a source electrode and a drain electrode of the thin film transistor On the semiconductor layer of the channel region, an organic insulating film is formed on the inorganic insulating film, a protective film is formed on the pixel electrode and the organic insulating film, and the common electrode is formed on the protective film such that The protective film is disposed between a layer where the common electrode is located and a layer where the pixel electrode is located, and the inorganic insulating film and the organic insulating film are disposed between the pixel electrode and the data line and
  • Embodiments of the present invention provide a method for fabricating an array substrate, including:
  • the semiconductor layer may be left under the data line (as shown in FIG. 13), or the semiconductor layer may not be retained (as shown in FIG. 14); the source electrode and/or the drain electrode may be completely located above the semiconductor layer ( As shown in Figure 13, it can also extend to areas outside the semiconductor layer (as shown in Figure 14). When the source electrode and/or the drain electrode extend to a region other than the semiconductor layer, it is possible to have a better contact effect.
  • the semiconductor layer 5 may be a common silicon semiconductor (intrinsic semiconductor or doped semiconductor), an organic semiconductor, or an oxide semiconductor.
  • the common electrode 16 may be in the shape of a slit, and the pixel electrode 12 may be in the form of a plate or a slit.
  • the embodiment of the invention further provides a display device, which may include any of the above array substrates.
  • the display device can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, a cell phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Step S11 providing a substrate, forming a gate line, a gate electrode and a gate pad on the substrate; specifically, first, sputtering, thermal evaporation or other film forming method may be used on the glass substrate or other type of transparent substrate
  • the gate metal layer may be made of chromium (Cr), molybdenum (Mo), aluminum (A1), copper (Cu), tungsten (W), niobium (Nd) or alloys thereof, and the gate metal layer may One or more layers; then, forming a photoresist on the gate metal layer; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; A photoresist mask etches the gate metal layer to form a pattern of gate lines, gate electrodes, and gate pads; finally, the remaining photoresist is stripped.
  • the common electrode lines may be formed while forming the patterns of the gate lines, the gate electrodes, and the gate
  • a source/drain metal layer having a thickness of 1000 to 6000 A may be formed on the substrate 1 on which the step S13 is completed by using sputtering, thermal evaporation or other film forming methods, and the source/drain metal layer may be used.
  • the thickness of the organic insulating film 10 is too small, the effect of reducing the parasitic capacitance between the subsequent common electrode and the data line (relative to the inorganic insulating film) is not significant; if the thickness of the organic insulating film 10 is too high , the slope of the step between the layers will increase, which may cause defects such as disconnection of the pixel electrode.
  • the exposed inorganic insulating film 21 is etched using the organic insulating film 10 as a mask to form a first contact hole 11 and expose the gate insulating layer 4 and data at the gate pad 3.
  • the organic insulating mold 10 since the organic insulating mold 10 is used, even between the pixel electrode 12 and the data line 8 The distance d2 in the horizontal direction is made smaller, and the parasitic capacitance between the pixel electrode and the data line is not too large. Therefore, the distance d2 can be reduced to 0 to 1 ⁇ m to increase the aperture ratio of the pixel.
  • Step S21 providing a substrate, forming a gate line, a gate electrode and a gate pad on the substrate; specifically, first, sputtering, thermal evaporation or other film forming method may be used on the glass substrate or other type of transparent substrate
  • the gate metal layer may be made of chromium (Cr), molybdenum (Mo), aluminum (A1), copper (Cu), tungsten (W), niobium (Nd) and alloys thereof, and the gate metal layer may be One or more layers; then, a photoresist is formed on the gate metal layer; then, the photoresist is exposed and developed by using a patterned mask to form a photoresist mask; The gate mask etches the gate metal layer to form a pattern of gate lines, gate electrodes and gate pads; finally, the remaining photoresist is stripped.
  • a common electrode line may be formed while forming a pattern of a gate line, a gate electrode, and
  • Step S25 forming a photoresist mask on the substrate completing step S24;
  • a photoresist layer 19 is formed on the source/drain metal layer; then, the photoresist layer 19 is exposed and developed by using a gray tone or halftone mask patterned with a pattern, A photoresist mask including a photoresist completely reserved region, a photoresist portion remaining region, and a photoresist unretained region is formed.
  • Step S27 etching a semiconductor material layer in the unreserved region of the photoresist, and performing an ashing process; specifically, as shown in FIG. 14, first, using a photoresist mask to the semiconductor material in the region where the photoresist is not reserved The layer 20 is etched to form a pattern of the semiconductor layer 5; then, the photoresist in the remaining portion of the photoresist is removed by an ashing process, and the photoresist in the completely remaining region of the photoresist is thinned to form a new photoresist.
  • Mask etching a semiconductor material layer in the unreserved region of the photoresist
  • Step S28 forming a pattern of the source electrode and the drain electrode
  • an inorganic insulating film 21 having a thickness of 1000 2000 A may be deposited on the substrate 1 on which step S28 is completed by a method such as PECVD.
  • the inorganic insulating film 21 may be selected from an oxide (e.g., SiOx) or a nitride (e.g., SiNx).
  • the curing temperature may be 230 to 260 ° C, and the treatment time may be 30 to 60 minutes. If the curing temperature is lower than 230 ° C, the micro-cure of the protective film may cause contamination and film lift, etc.; if the curing temperature is higher than 260 ° C, the organic insulating film 10 may be denatured, thereby This makes the transmission rate low.
  • Step S31 etching away the exposed inorganic insulating film
  • the storage capacitor (Cst) rises, causing an increase in signal delay; if the thickness of the protective film 13 is larger than 4000 A, the process time and the manufacturing cost are too high.
  • the common electrode 16 may include a first common electrode 161 located above the pixel electrode 12 and a second common electrode 162 located above the data line 8.
  • the gate pad electrode 17 may be electrically connected to the gate pad 3 through the second contact hole 14, and the data pad electrode 18 may be electrically connected to the data pad 9 through the third contact hole 15.
  • the second common electrode 162 is located above the data line 8, and can shield the electromagnetic field between the pixel electrode 12 and the data line 8, thereby reducing the width of the black matrix on the color filter. Thereby, the aperture ratio of the pixel can be increased. Further, in forming the semiconductor layer 5, the source electrode 6, and the drain electrode 7, since the ashing process is used, the number of masks can be reduced, thereby reducing the manufacturing cost.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention se rapporte à un procédé de fabrication d'un substrat de matrice, à un substrat de matrice et à un dispositif d'affichage. Une zone d'affichage du substrat de matrice comprend une ligne de grille, une ligne de données (8) et de multiples unités de pixel définies par la ligne de grille et par la ligne de données (8). Chaque unité de pixel comprend un transistor à couches minces (TFT), une électrode de pixel (12) et une électrode commune (16). L'électrode de pixel (12) est raccordée électriquement à une électrode déversoir (7) du transistor TFT. Un film de protection (13) est agencé entre la couche au niveau de laquelle se trouve l'électrode commune (16) et la couche au niveau de laquelle se trouve l'électrode de pixel (12). Un film isolant inorganique (21) et un film isolant organique (10) sont agencés entre l'électrode de pixel (12) et la ligne de données (8) et entre le transistor TFT et le film de protection (13), ce qui permet de réduire les retards du signal sur la ligne de données (8) et d'empêcher la production d'un courant de drain dans le transistor TFT à des températures élevées.
PCT/CN2012/083889 2012-04-20 2012-10-31 Procédé de fabrication d'un substrat de matrice, substrat de matrice, et dispositif d'affichage WO2013155830A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210119008.0 2012-04-20
CN2012101190080A CN102645808A (zh) 2012-04-20 2012-04-20 一种阵列基板的制造方法、阵列基板及显示装置

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WO2013155830A1 true WO2013155830A1 (fr) 2013-10-24

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Cited By (3)

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CN104966721A (zh) * 2015-07-15 2015-10-07 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板和显示装置
CN106298647A (zh) * 2016-08-31 2017-01-04 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板及其制备方法
JP2017500727A (ja) * 2013-11-12 2017-01-05 深▲セン▼市華星光電技術有限公司 薄膜トランジスタ基板の製造方法及び前記方法によって製造された薄膜トランジスタ基板

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CN102707523A (zh) * 2012-04-20 2012-10-03 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置
CN102645808A (zh) * 2012-04-20 2012-08-22 京东方科技集团股份有限公司 一种阵列基板的制造方法、阵列基板及显示装置
TWI501015B (zh) * 2013-04-03 2015-09-21 Au Optronics Corp 畫素結構及其製作方法
CN103219319B (zh) * 2013-04-26 2015-11-25 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN103325792A (zh) * 2013-05-23 2013-09-25 合肥京东方光电科技有限公司 一种阵列基板及制备方法、显示装置
CN103325794A (zh) * 2013-05-30 2013-09-25 合肥京东方光电科技有限公司 一种阵列基板、显示装置及阵列基板的制作方法
CN103346160B (zh) * 2013-07-10 2016-04-06 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN103439840B (zh) * 2013-08-30 2017-06-06 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制造方法
CN104766819B (zh) * 2014-01-06 2017-12-08 瀚宇彩晶股份有限公司 画素基板及其制造方法
CN103943637B (zh) 2014-04-10 2016-08-31 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
CN104298040B (zh) * 2014-10-31 2018-07-06 京东方科技集团股份有限公司 一种coa基板及其制作方法和显示装置
CN110112145B (zh) * 2015-01-21 2023-08-29 群创光电股份有限公司 显示装置
CN105185789A (zh) * 2015-09-07 2015-12-23 昆山龙腾光电有限公司 阵列基板的制造方法、阵列基板与液晶显示装置
CA3019219A1 (fr) * 2016-07-25 2018-02-01 Shenzhen Royole Technologies Co., Ltd. Procede de fabrication de substrat de matrice
CN107086220A (zh) * 2017-04-24 2017-08-22 惠科股份有限公司 一种主动开关阵列基板及其制造方法、显示面板
KR102418577B1 (ko) * 2017-12-13 2022-07-08 엘지디스플레이 주식회사 터치 센서를 가지는 표시 장치 및 그 제조 방법
CN110310921B (zh) * 2019-07-09 2021-10-01 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示面板及显示装置
CN114114763B (zh) * 2020-08-27 2023-08-08 合肥京东方显示技术有限公司 一种显示基板和显示面板
CN113867028A (zh) * 2021-10-09 2021-12-31 福建华佳彩有限公司 一种低触控负载的像素结构

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JP2017500727A (ja) * 2013-11-12 2017-01-05 深▲セン▼市華星光電技術有限公司 薄膜トランジスタ基板の製造方法及び前記方法によって製造された薄膜トランジスタ基板
CN104966721A (zh) * 2015-07-15 2015-10-07 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板和显示装置
CN106298647A (zh) * 2016-08-31 2017-01-04 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板及其制备方法
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