CN106298647A - 一种阵列基板及其制备方法、显示面板及其制备方法 - Google Patents

一种阵列基板及其制备方法、显示面板及其制备方法 Download PDF

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CN106298647A
CN106298647A CN201610797896.XA CN201610797896A CN106298647A CN 106298647 A CN106298647 A CN 106298647A CN 201610797896 A CN201610797896 A CN 201610797896A CN 106298647 A CN106298647 A CN 106298647A
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electrode
layer
drain
source
substrate
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CN106298647B (zh
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崔承镇
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US15/747,722 priority patent/US10763283B2/en
Priority to PCT/CN2017/094059 priority patent/WO2018040795A1/zh
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Abstract

本发明的实施例提供一种阵列基板及其制备方法、显示面板及其制备方法,涉及显示技术领域，可减少构图工艺次数，降低成本。该阵列基板的制备方法包括：在衬底上通过一次构图工艺形成栅金属层；在形成有栅金属层和栅绝缘层的衬底上，通过一次构图工艺形成半导体层和源漏金属层；源漏金属层包括数据线和与数据线连接的金属电极；在形成有半导体层和源漏金属层的衬底上，通过一次构图工艺形成第一电极，并形成沟道区，沟道区使金属电极形成源极和漏极；在形成有第一电极的衬底上，通过一次构图工艺形成钝化层和有机绝缘层；有机绝缘层至少与数据线对应；在形成有所述有机绝缘层的衬底上，通过一次构图工艺形成第二电极。用于阵列基板的制造。

Description

一种阵列基板及其制备方法、显示面板及其制备方法
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板及其制备方法。
背景技术
液晶显示器(Liquid Crystal Display，简称LCD)具有体积小、功耗低、无辐射等优点，在显示领域中占据了主导地位。
液晶显示器中的液晶显示面板包括阵列基板、对盒基板以为位于二者之间的液晶层。
目前，一种结构的阵列基板，其制备方法需要经过六次采用掩模板的构图工艺，具体为：通过第一次构图工艺形成栅极和栅线；通过第二次构图工艺形成有源层、源极和漏极、以及数据线；通过第三次构图工艺形成第一钝化层和有机绝缘层；通过第四次沟通工艺形成第一电极；通过第四次沟通工艺形成第二钝化层；通过第五次构图工艺形成第二电极；其中，第一电极和第二电极互为像素电极和公共电极。
发明内容
本发明的实施例提供一种阵列基板及其制备方法、显示面板及其制备方法，可减少构图工艺次数，降低成本。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，提供一种阵列基板的制备方法，包括：在衬底上通过一次构图工艺形成栅金属层；在形成有所述栅金属层和栅绝缘层的衬底上，通过一次构图工艺形成半导体层和源漏金属层；所述源漏金属层包括数据线和与所述数据线连接的金属电极；在形成有所述半导体层和源漏金属层的衬底上，通过一次构图工艺形成第一电极，并形成沟道区，所述沟道区使所述金属电极形成源极和漏极；在形成有所述第一电极的衬底上，通过一次构图工艺形成钝化层和有机绝缘层；所述有机绝缘层至少与所述数据线对应；在形成有所述有机绝缘层的衬底上，通过一次构图工艺形成第二电极。
优选的，所述第一电极和所述第二电极均为透明电极。
可选的，所述第一电极为公共电极；所述第二电极为像素电极；所述像素电极至少通过设置在所述钝化层上的过孔与所述漏极电连接；或者，所述第一电极为像素电极；所述像素电极与所述漏极直接相连；所述第二电极为公共电极。
优选的，所述半导体层和所述源漏金属层的图案形状相同；通过一次构图工艺形成第一电极，并形成沟道区，包括：在形成有所述半导体层和所述源漏金属层的衬底上形成导电薄膜，并形成光刻胶；采用普通掩模板对所述光刻胶进行曝光，显影后形成光刻胶保留图案，所述光刻胶保留图案与待形成的所述第一电极、待形成的所述源极和所述漏极、以及所述数据线对应；采用刻蚀工艺对基板进行刻蚀，使所述金属电极形成所述源极和所述漏极，并形成所述第一电极，同时形成位于所述数据线、所述源极和所述漏极上方的保留图案。
进一步，优选的，所述半导体层包括a-si层和n+a-si层；采用刻蚀工艺对基板进行刻蚀，使所述金属电极形成所述源极和所述漏极，包括：采用刻蚀工艺对基板进行刻蚀，使所述金属电极形成所述源极和所述漏极，使所述n+a-si层形成欧姆接触层。
可选的，所述有机绝缘层与所述数据线、所述源极和所述漏极、以及所述沟道区对应。
进一步优选的，所述钝化层的厚度为所述有机绝缘层的厚度为1.5～2.2μm。
可选的，所述有机绝缘层平铺于所述衬底上；所述有机绝缘层包括第一部分和第二部分；所述第一部分与所述数据线、所述源极和所述漏极、以及所述沟道区对应；所述第二部分对应其他区域；所述第一部分的厚度为1.8～2.7μm，所述第二部分的厚度为所述钝化层的厚度为
进一步优选的，在所述第一电极为公共电极，所述第二电极为像素电极的情况下，通过一次构图工艺形成钝化层和有机绝缘层，包括：在形成有所述第一电极的衬底上，依次形成钝化薄膜和感光树脂薄膜；采用半色调掩模板对所述感光树脂薄膜进行曝光，形成感光树脂完全保留部分、感光树脂半保留部分和完全去除部分；所述感光树脂完全保留部分与所述数据线、所述源极和所述漏极、以及所述沟道区对应；所述完全去除部分与待形成的露出所述漏极的过孔对应；所述感光树脂半保留部分与其他区域对应；采用刻蚀工艺对所述钝化薄膜进行刻蚀，形成包括过孔的钝化层，所述过孔露出所述漏极；采用灰化工艺对所述感光树脂完全保留部分和所述感光树脂半保留部分进行灰化，形成所述有机绝缘层。
进一步的，所述感光树脂完全保留部分的厚度为2.0～3.0μm；所述感光树脂半保留部分的厚度为
第二方面，提供一种显示面板的制备方法，包括第一方面所述阵列基板的制备方法。
第三方面，提供一种阵列基板，包括：衬底、依次设置在所述衬底上的包括栅极的栅金属层、栅绝缘层、半导体层、源极、漏极和数据线，所述源极和所述漏极之间形成沟道区，所述阵列基板还包括与所述源极和所述漏极分别对应且接触的保留图案、与所述保留图案同层的第一电极、依次设置在所述第一电极远离所述衬底一侧的钝化层、有机绝缘层和第二电极；其中，所述有机绝缘层至少与所述数据线对应。
优选的，所述第一电极和所述第二电极均为透明电极。
可选的，所述第一电极为公共电极；所述第二电极为像素电极；所述像素电极至少通过设置在所述钝化层上的过孔与所述漏极电连接；或者，所述第一电极为像素电极；所述像素电极与所述漏极直接相连；所述第二电极为公共电极。
可选的，所述有机绝缘层与所述数据线、所述源极和所述漏极、以及所述沟道区对应。
进一步优选的，所述钝化层的厚度为所述有机绝缘层的厚度为1.5～2.2μm。
可选的，所述有机绝缘层平铺于所述衬底上；所述有机绝缘层包括第一部分和第二部分；所述第一部分与所述数据线、所述源极和所述漏极、以及所述沟道区对应；所述第二部分对应其他区域；所述第一部分的厚度为1.8～2.7μm，所述第二部分的厚度为所述钝化层的厚度为
基于上述，优选的，所述半导体层包括a-si层和欧姆接触层。
第四方面，提供一种显示面板，包括第三方面所述的阵列基板。
本发明实施例提供一种阵列基板及其制备方法、显示面板及其制备方法，通过第一次构图工艺形成包括栅极的栅金属层，通过第二次构图工艺形成半导体层和包括数据线和金属电极的源漏金属层，通过第三次构图工艺形成第一电极，并形成沟道区；通过第四次构图工艺形成钝化层和有机绝缘层；通过第五次构图工艺形成第二电极，相对现有技术中的六次构图工艺可减少一次构图工艺次数，因而可以降低成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1(a)为本发明实施例提供的一种阵列基板制备方法的流程示意图一；
图1(b)为本发明实施例提供的一种阵列基板制备方法的流程示意图二；
图2(a)为本发明实施列提供的一种在衬底上形成栅金属层、半导体层和源漏金属层的俯视示意图；
图2(b)为图2(a)的AA′向剖视示意图；
图3(a)为在图2(a)的基础上形成第一电极、保留图案以及沟道区的俯视示意图一；
图3(b)为图3(a)的BB′向剖视示意图一；
图3(c)为图3(a)的BB′向剖视示意图二；
图4(a)～4(c)为本发明实施列提供的一种形成第一电极、保留图案以及沟道区的过程示意图；
图5(a)为在图3(a)的基础上形成钝化层和有机绝缘层的俯视示意图一；
图5(b)为图5(a)的CC′向剖视示意图；
图5(c)为在图3(a)的基础上形成钝化层和有机绝缘层的俯视示意图二；
图5(d)为图5(c)的DD′向剖视示意图；
图6(a)为在图3(a)的基础上形成钝化层和有机绝缘层的俯视示意图三；
图6(b)为图6(a)的EE′向剖视示意图；
图7(a)～7(c)为本发明实施列提供的一种形成钝化层和有机绝缘层的过程示意图；
图8(a)为在图5(c)或图6(a)的基础上形成第二电极的俯视示意图；
图8(b)为图8(a)的FF′向剖视示意图一；
图8(c)为图8(a)的FF′向剖视示意图二；
图9(a)为在图2(a)的基础上形成第一电极、保留图案以及沟道区的俯视示意图二；
图9(b)为图9(a)的GG′向剖视示意图；
图10(a)为在图9(b)的基础上形成钝化层和有机绝缘层的示意图一；
图10(b)为在图9(b)的基础上形成钝化层和有机绝缘层的示意图二；
图10(c)为在图9(b)的基础上形成钝化层和有机绝缘层的示意图三；
图11为在图10(c)的基础上形成第二电极的示意图。
附图标记：
01-衬底；02-普通掩模板；03-半色调掩模板；10-栅金属层；101-栅极；102-栅线；11-栅绝缘层；12-半导体层；121-a-si层；122-欧姆接触层；13-源漏金属层；131-数据线；132-金属电极；1321-源极；1322-漏极；14-导电薄膜；141-第一电极；142-保留图案；15-光刻胶；151-光刻胶保留图案；16-钝化薄膜；161-钝化层；162-过孔；17-感光树脂薄膜；171-有机绝缘层；172-感光树脂完全保留部分；173-感光树脂半保留部分；174-完全去除部分；18-第二电极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种阵列基板的制备方法，包括在衬底上通过一次构图工艺形成栅金属层；在形成有所述栅金属层和栅绝缘层的衬底上，通过一次构图工艺形成半导体层和源漏金属层；所述源漏金属层包括数据线和与所述数据线连接的金属电极；在形成有所述半导体层和源漏金属层的衬底上，通过一次构图工艺形成第一电极，并形成沟道区，所述沟道区使所述金属电极形成源极和漏极；在形成有第一电极的衬底上，通过一次构图工艺形成钝化层和有机绝缘层；所述有机绝缘层至少与所述数据线对应；在形成有所述有机绝缘层的衬底上，通过一次构图工艺形成第二电极。
需要说明的是，第一，栅金属层可以包括栅极、栅线。在形成栅金属层后，形成半导体层之间，还形成栅绝缘层。
第二，不对半导体层的材料进行限定，所述半导体层可以为有机半导层，也可以为金属氧化物半导体层，当然还可以包括a-si(非晶硅)层和n+a-si层等。
第三，在形成沟道区时，可根据半导体层的材料不同，选择是否对相应的半导体层进行刻蚀，例如，当半导体层包括a-si层和n+a-si层时，则需要对n+a-si层进行刻蚀，a-si层也可适当进行过刻。
第四，有机绝缘层至少与数据线对应，一种情况为有机绝缘层仅与数据线对应，另一种情况为有机绝缘层不仅与数据线对应，还与其他区域对应。
本发明实施例提供一种阵列基板的制备方法，通过第一次构图工艺形成包括栅极的栅金属层，通过第二次构图工艺形成半导体层和包括数据线和金属电极的源漏金属层，通过第三次构图工艺形成第一电极，并形成沟道区；通过第四次构图工艺形成钝化层和有机绝缘层；通过第五次构图工艺形成第二电极，相对现有技术中的六次构图工艺可减少一次构图工艺次数，因而可以降低成本。
可选的，所述第一电极和所述第二电极均为透明电极。
进一步可选的，所述第一电极为公共电极；所述第二电极为像素电极；所述像素电极至少通过设置在所述钝化层上的过孔与所述漏极电连接。
或者，所述第一电极为像素电极；所述像素电极与所述漏极直接相连；所述第二电极为公共电极。
实施例一，如图1(a)所示，提供一种阵列基板的制备方法，包括如下步骤：
S10、如图2(a)和图2(b)所示，在衬底01上通过一次构图工艺形成包括栅极101和栅线102的栅金属层10。
具体的，可先在衬底01上制备一层金属薄膜。金属材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种材料薄膜的组合结构。然后，采用普通掩模板通过曝光、显影、刻蚀、剥离等构图工艺处理，在衬底01上形成栅极101和栅线102。
S11、如图2(b)所示，在S10的基础上，形成栅绝缘层11。
具体的，可先在形成有栅极101的衬底01上制备绝缘薄膜，形成栅绝缘层11。栅绝缘层11的材料通常是氮化硅，也可以使用氧化硅和氮氧化硅等。
S12、如图2(a)和图2(b)所示，在S11的基础上，通过一次构图工艺形成半导体层12和源漏金属层13；半导体层12和源漏金属层13的图案形状相同；源漏金属层13包括数据线131和与数据线131连接的金属电极132。
具体的，可以先在栅绝缘层11上依次形成半导体薄膜和金属薄膜，并形成光刻胶；之后，采用普通掩模板对所述光刻胶进行曝光、显影，刻蚀后形成所述半导体层12和源漏金属层13。
其中，金属薄膜的材料通常可以采用钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以使用上述几种材料薄膜的组合结构。半导体薄膜根据具体要形成薄膜晶体管的结构而定，可以为一层，也可以为两层。
S13、如图3(a)和图3(b)所示，在S12的基础上，通过一次构图工艺形成第一电极141，并形成沟道区，所述沟道区使金属电极132形成源极1321和漏极1322；第一电极141为公共电极。
具体的，如图4(a)所示，可以先在形成有源漏金属层13的基板上形成导电薄膜14，导电薄膜14的材料可以采用ITO(Indium Tin Oxides，铟锡氧化物)或IZO(Indium ZincOxide，铟锌氧化物)等，并形成光刻胶15。之后，采用普通掩模板02对光刻胶15进行曝光，显影后，如图4(b)所示，形成光刻胶保留图案151，光刻胶保留图案151与待形成的第一电极141、待形成的源极和漏极、以及数据线131对应。之后，如图4(c)所示，采用刻蚀工艺对基板进行刻蚀，使所述金属电极132形成源极1321和漏极1322，并形成第一电极141，同时形成位于数据线131、源极1321和漏极1322上方的保留图案142。最后，将光刻胶保留图案151去除，形成如图3(b)所示的结构。
其中，如图3(c)所示，在半导体层12包括a-si层121和n+a-si层的情况下，可在刻蚀形成源极1321和漏极1322的同时，继续对n+a-si层进行刻蚀，使n+a-si层形成欧姆接触层122。
此处，在形成欧姆接触层122时，可适当的对a-si层121进行过刻，以避免a-si层121表面附着的导电离子渗入沟道中，影响薄膜晶体管的性能。此时，薄膜晶体管包括：栅极101、栅绝缘层11、a-si层121、欧姆接触层122、源极1321和漏极1322。
S14、如图5(a)～5(d)、以及图6(a)和图6(b)所示，在S13的基础上，通过一次构图工艺形成钝化层161和有机绝缘层171；有机绝缘层171至少与数据线131对应。
此处，有机绝缘层171优选为有机树脂层。进一步优选的，有机绝缘层171的材料为感光树脂材料。
具体的，分如下三种情况具体进行说明：
第一种情况：如图5(a)和图5(b)所示，有机绝缘层171可以仅与数据线131对应。基于此，优选的，钝化层161的厚度为有机绝缘层171的厚度为1.5～2.2μm。
在此情况下，所述阵列基板可应用在高Cst(存储电容)的产品中。例如，在高分辨率的产品中，像素面积变小，导致Cst变小，而Vop(驱动电压)与Cst有相关性，需要符合产品规格进行最佳设计，而本发明实施例通过在像素区域不形成有机绝缘层且使钝化层161的厚度为可提高Cst，从而使Vop也满足设计要求，因而可适用于高分辨率的产品中。此外，将钝化层161的厚度设置为还可避免公共电极与像素电极发生短路。
第二种情况：如图5(c)和图5(d)所示，有机绝缘层171可以与数据线131、源极1321和漏极1322、以及沟道区对应，即有机绝缘层171不仅与数据线131对应，还与薄膜晶体管对应。基于此，优选的，钝化层161的厚度为有机绝缘层171的厚度为1.5～2.2μm。
在此情况下，所述阵列基板可应用在高Cst的产品中。
第三种情况：如图6(a)和图6(b)所示，有机绝缘层171平铺于衬底01上。此时，有机绝缘层171可以包括第一部分和第二部分；第一部分与数据线131、源极1321和漏极1322、以及沟道区对应；第二部分对应其他区域。其中，第一部分的厚度大于第二部分的厚度，这是因为第二部分的厚度若太大，则会导致阵列基板的存储电容Cst太小。
基于此，优选的，所述第一部分的厚度为1.8～2.7μm，所述第二部分的厚度为所述钝化层的厚度为
在此情况下，所述阵列基板可应用在减少Cst的产品中。例如，在低分辨率的产品例如TV(Television，电视机)产品中，像素面积变大，Cst变的过大，因而，本发明实施例通过在像素区域形成有机绝缘层171且使钝化层161的厚度为可降低Cst。此外，在像素区域也形成有机绝缘层171，可使阵列基板整体更趋于平坦。
其中，针对图5(c)和5(d)所示的情况，如图7(a)所示，可以先在形成有第一电极141和保留图案142的基板上，形成钝化薄膜16，并形成感光树脂薄膜17。之后，采用半色调掩模板03对感光树脂薄膜17进行曝光，显影后，如图7(b)所示，形成感光树脂完全保留部分172、感光树脂半保留部分173和完全去除部分174；感光树脂完全保留部分172与数据线131、源极1321和漏极1322、以及所述沟道区对应；完全去除部分174与待形成的露出漏极1322的过孔对应；所述感光树脂半保留部分与其他区域对应。如图7(c)所示，采用刻蚀工艺对钝化薄膜16进行刻蚀，形成包括过孔162的钝化层161。然后，可采用灰化工艺将感光树脂半保留部分173去除，由于感光树脂完全保留部分172的厚度大于感光树脂半保留部分173的厚度，因而感光树脂完全保留部分172的部分厚度被保留，形成如图5(d)所示的有机绝缘层171。
优选的，感光树脂完全保留部分172的厚度为2.0～3.0μm；感光树脂半保留部分173的厚度为这样，一方面，可使有机绝缘层171与数据线131对应的部分满足产品设计要求，另一方面，当感光树脂半保留部分173的部分厚度保留下来时，也可满足产品设计要求。
针对图5(a)和5(b)所示的情况，与上述过程类似，只是感光树脂完全保留部分172仅与数据线131对应。
针对如图6(a)和图6(b)所示的情况，与上述过程类似，只是在灰化工艺时，可不将感光树脂完全保留部分172去除，而仅去除部分厚度，从而形成如图6(b)所示的有机绝缘层171。
S15、如图8(a)和图8(b)以及图8(c)所示，在S14的基础上，形成第二电极18，第二电极18为像素电极，第二电极18通过露出漏极1322的过孔162与漏极1322电连接。
具体的，可以在形成有有机绝缘层171的基板上形成透明导电薄膜，然后，用普通掩膜板通过曝光、显影、刻蚀、剥离等构图工艺处理，形成所述第二电极18。
实施例二，如图1(b)所示，提供一种阵列基板的制备方法，包括如下步骤：
S20、如图2(a)和图2(b)所示，在衬底01上通过一次构图工艺形成包括栅极101和栅线102的栅金属层10。
S21、如图2(b)所示，在S10的基础上，形成栅绝缘层11。
S22、如图2(a)和图2(b)所示，在S11的基础上，通过一次构图工艺形成半导体层12和源漏金属层13；半导体层12和源漏金属层13的图案形状相同；源漏金属层13包括数据线131和与数据线131连接的金属电极132。
S23、如图9(a)和图9(b)所示，在S22的基础上，通过一次构图工艺形成第一电极141，并形成沟道区，所述沟道区使金属电极132形成源极1321和漏极1322；第一电极141为像素电极。
此处，在形成第一电极141的同时，还形成位于数据线131、源极1321和漏极1322上方的保留图案142，位于漏极1322上方的保留图案142与第一电极141相连。
如图9(b)所示，在半导体层12包括a-si层121和n+a-si层的情况下，可在刻蚀形成源极1321和漏极1322的同时，继续对n+a-si层进行刻蚀，使n+a-si层形成欧姆接触层122。
其中，在形成欧姆接触层122时，可适当的对a-si层121进行过刻，以避免a-si层121表面附着的导电离子渗入沟道中，影响薄膜晶体管的性能。此时，薄膜晶体管包括：栅极101、栅绝缘层11、a-si层121、欧姆接触层122、源极1321和漏极1322。
S24、如图10(a)～10(c)所示，在S23的基础上，通过一次构图工艺形成钝化层161和有机绝缘层171；有机绝缘层171至少与数据线131对应。
此处，有机绝缘层171优选为有机树脂层。进一步优选的，有机绝缘层171的材料为感光树脂材料。
具体的，分如下三种情况具体进行说明：
第一种情况：如图10(a)所示，有机绝缘层171可以仅与数据线131对应。基于此，优选的，钝化层161的厚度为有机绝缘层171的厚度为1.5～2.2μm。
在此情况下，所述阵列基板可应用在高Cst的产品中。例如，在高分辨率的产品中，像素面积变小，导致Cst变小，而Vop与Cst有相关性，需要符合产品规格进行最佳设计，而本发明实施例通过在像素区域不形成有机绝缘层且使钝化层161的厚度为可提高Cst，从而使Vop也满足设计要求，因而可适用于高分辨率的产品中。此外，将钝化层161的厚度设置为还可避免公共电极与像素电极发生短路。
第二种情况：如图10(b)所示，有机绝缘层171可以与数据线131、源极1321和漏极1322、以及沟道区对应，即有机绝缘层171不仅与数据线131对应，还与薄膜晶体管对应。基于此，优选的，钝化层161的厚度为有机绝缘层171的厚度为1.5～2.2μm。
在此情况下，所述阵列基板可应用在高Cst的产品中。
第三种情况：如图10(c)所示，有机绝缘层171平铺于衬底01上。此时，有机绝缘层171可以包括第一部分和第二部分；第一部分与数据线131、源极1321和漏极1322、以及沟道区对应；第二部分对应其他区域。其中，第一部分的厚度大于第二部分的厚度，这是因为第二部分的厚度若太大，则会导致阵列基板的存储电容Cst太小。
基于此，优选的，第一部分的厚度为1.8～2.7μm，第二部分的厚度为钝化层161的厚度为
在此情况下，所述阵列基板可应用在减少Cst的产品中。例如，在低分辨率的产品例如TV产品中，像素面积变大，Cst变的过大，因而，本发明实施例通过在像素区域形成有机绝缘层171且使钝化层161的厚度为可降低Cst。此外，在像素区域也形成有机绝缘层171，可使阵列基板整体更趋于平坦。
S25、如图11所示，在S24的基础上，形成第二电极18，第二电极18为公共电极。
本发明实施还提供一种显示面板的制备方法，包括上述阵列基板的制备方法。
本发明实施例提供一种显示面板的制备方法，其中在制备阵列基板时，可通过第一次构图工艺形成包括栅极的栅金属层，通过第二次构图工艺形成半导体层和包括数据线和金属电极的源漏金属层，通过第三次构图工艺形成第一电极，并形成沟道区；通过第四次构图工艺形成钝化层和有机绝缘层；通过第五次构图工艺形成第二电极，相对现有技术中的六次构图工艺可减少一次构图工艺次数，因而可以降低成本。
本发明实施例还提供一种阵列基板，如图8(b)、图8(c)和图11所示，包括：衬底01、依次设置在衬底01上的包括栅极101的栅金属层、栅绝缘层11、半导体层、源极1321、漏极1322和数据线131，源极1321和漏极1322之间形成沟道区，所述阵列基板还包括与源极1321和漏极1322分别对应且接触的保留图案142、与所述保留图案142同层的第一电极141、依次设置在所述第一电极141远离衬底01一侧的钝化层161、有机绝缘层171和第二电极18；其中，有机绝缘层171至少与数据线131对应。
可选的，所述半导体层包括a-si层121和欧姆接触层122。
此时，薄膜晶体管包括：栅极101、栅绝缘层11、a-si层121、欧姆接触层122、源极1321和漏极1322。
可选的，所述第一电极141和所述第二电极18均为透明电极。
进一步可选的，如图8(b)和图8(c)所示，第一电极141为公共电极；第二电极18为像素电极；像素电极至少通过设置在钝化层161上的过孔162与漏极1322电连接。
或者，如图11所示，第一电极141为像素电极；像素电极与漏极1322直接相连；第二电极18为公共电极。
基于上述，可选的，如图8(c)所示，有机绝缘层171与数据线131、源极1321和漏极1322、以及所述沟道区对应。此时，像素电极通过设置在钝化层161上的过孔162与漏极1322电连接。
基于此，优选的，钝化层161的厚度为有机绝缘层171的厚度为1.5～2.2μm。
在此情况下，所述阵列基板可应用在高Cst的产品中。例如，在高分辨率的产品中，像素面积变小，导致Cst变小，而Vop与Cst有相关性，需要符合产品规格进行最佳设计，而本发明实施例通过在像素区域不形成有机绝缘层且使钝化层161的厚度为可提高Cst，从而使Vop也满足设计要求，因而可适用于高分辨率的产品中。此外，将钝化层161的厚度设置为还可避免公共电极与像素电极发生短路。
当然，参考图5(a)和图5(b)所示，有机绝缘层171可以仅与数据线131对应。
如图8(b)所示，有机绝缘层171平铺于衬底01上。有机绝缘层171可以包括第一部分和第二部分；第一部分与数据线131、源极1321和漏极1322、以及沟道区对应；第二部分对应其他区域。此时，像素电极通过设置在钝化层161和有机绝缘层171上的过孔162与漏极1322电连接。
基于此，优选的，所述第一部分的厚度为1.8～2.7μm，所述第二部分的厚度为所述钝化层的厚度为
在此情况下，所述阵列基板可应用在减少Cst的产品中。例如，在低分辨率的产品例如TV产品中，像素面积变大，Cst变的过大，因而，本发明实施例通过在像素区域形成有机绝缘层171且使钝化层161的厚度为可降低Cst。此外，在像素区域也形成有机绝缘层171，可使阵列基板整体更趋于平坦。
本发明实施例提供一种阵列基板，可通过第一次构图工艺形成包括栅极的栅金属层，通过第二次构图工艺形成半导体层和包括数据线和金属电极的源漏金属层，通过第三次构图工艺形成第一电极，并形成沟道区；通过第四次构图工艺形成钝化层和有机绝缘层；通过第五次构图工艺形成第二电极，相对现有技术中的六次构图工艺可减少一次构图工艺次数，因而可以降低成本。
本发明实施例还提供一种显示面板，其包括上述的阵列基板。
所述显示面板具体可以为液晶显示面板。
进一步的，本发明实施例还提供一种显示装置，所述显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (19)

1.一种阵列基板的制备方法，其特征在于，包括：
在衬底上通过一次构图工艺形成栅金属层；
在形成有所述栅金属层和栅绝缘层的衬底上，通过一次构图工艺形成半导体层和源漏金属层；所述源漏金属层包括数据线和与所述数据线连接的金属电极；
在形成有所述半导体层和源漏金属层的衬底上，通过一次构图工艺形成第一电极，并形成沟道区，所述沟道区使所述金属电极形成源极和漏极；
在形成有所述第一电极的衬底上，通过一次构图工艺形成钝化层和有机绝缘层；所述有机绝缘层至少与所述数据线对应；
在形成有所述有机绝缘层的衬底上，通过一次构图工艺形成第二电极。
2.根据权利要求1所述的制备方法，其特征在于，所述第一电极和所述第二电极均为透明电极。
3.根据权利要求2所述的制备方法，其特征在于，所述第一电极为公共电极；
所述第二电极为像素电极；所述像素电极至少通过设置在所述钝化层上的过孔与所述漏极电连接；或者，
所述第一电极为像素电极；所述像素电极与所述漏极直接相连；
所述第二电极为公共电极。
4.根据权利要求1所述的制备方法，其特征在于，所述半导体层和所述源漏金属层的图案形状相同；
通过一次构图工艺形成第一电极，并形成沟道区，包括：
在形成有所述半导体层和所述源漏金属层的衬底上形成导电薄膜，并形成光刻胶；
采用普通掩模板对所述光刻胶进行曝光，显影后形成光刻胶保留图案，所述光刻胶保留图案与待形成的所述第一电极、待形成的所述源极和所述漏极、以及所述数据线对应；
采用刻蚀工艺对基板进行刻蚀，使所述金属电极形成所述源极和所述漏极，并形成所述第一电极，同时形成位于所述数据线、所述源极和所述漏极上方的保留图案。
5.根据权利要求4所述的制备方法，其特征在于，所述半导体层包括a-si层和n+a-si层；
采用刻蚀工艺对基板进行刻蚀，使所述金属电极形成所述源极和所述漏极，包括：
采用刻蚀工艺对基板进行刻蚀，使所述金属电极形成所述源极和所述漏极，使所述n+a-si层形成欧姆接触层。
6.根据权利要求1所述的制备方法，其特征在于，所述有机绝缘层与所述数据线、所述源极和所述漏极、以及所述沟道区对应。
7.根据权利要求6所述的制备方法，其特征在于，所述钝化层的厚度为
所述有机绝缘层的厚度为1.5～2.2μm。
8.根据权利要求1所述的制备方法，其特征在于，所述有机绝缘层平铺于所述衬底上；
所述有机绝缘层包括第一部分和第二部分；所述第一部分与所述数据线、所述源极和所述漏极、以及所述沟道区对应；所述第二部分对应其他区域；
所述第一部分的厚度为1.8～2.7μm，所述第二部分的厚度为
所述钝化层的厚度为
9.根据权利要求6或8所述的制备方法，其特征在于，所述第一电极为公共电极；所述第二电极为像素电极；
通过一次构图工艺形成钝化层和有机绝缘层，包括：
在形成有所述第一电极的衬底上，依次形成钝化薄膜和感光树脂薄膜；
采用半色调掩模板对所述感光树脂薄膜进行曝光，形成感光树脂完全保留部分、感光树脂半保留部分和完全去除部分；所述感光树脂完全保留部分与所述数据线、所述源极和所述漏极、以及所述沟道区对应；所述完全去除部分与待形成的露出所述漏极的过孔对应；所述感光树脂半保留部分与其他区域对应；
采用刻蚀工艺对所述钝化薄膜进行刻蚀，形成包括过孔的钝化层，所述过孔露出所述漏极；
采用灰化工艺对所述感光树脂完全保留部分和所述感光树脂半保留部分进行灰化，形成所述有机绝缘层。
10.根据权利要求9所述的制备方法，其特征在于，所述感光树脂完全保留部分的厚度为2.0～3.0μm；所述感光树脂半保留部分的厚度为
11.一种显示面板的制备方法，其特征在于，包括形成权利要求1-10任一项所述阵列基板的制备方法。
12.一种阵列基板，其特征在于，包括：衬底、依次设置在所述衬底上的包括栅极的栅金属层、栅绝缘层、半导体层、源极、漏极和数据线，所述源极和所述漏极之间形成沟道区，所述阵列基板还包括与所述源极和所述漏极分别对应且接触的保留图案、与所述保留图案同层的第一电极、依次设置在所述第一电极远离所述衬底一侧的钝化层、有机绝缘层和第二电极；
其中，所述有机绝缘层至少与所述数据线对应。
13.根据权利要求12所述的阵列基板，其特征在于，所述第一电极和所述第二电极均为透明电极。
14.根据权利要求13所述的阵列基板，其特征在于，所述第一电极为公共电极；
所述第二电极为像素电极；所述像素电极至少通过设置在所述钝化层上的过孔与所述漏极电连接；或者，
所述第一电极为像素电极；所述像素电极与所述漏极直接相连；
所述第二电极为公共电极。
15.根据权利要求12所述的阵列基板，其特征在于，所述有机绝缘层与所述数据线、所述源极和所述漏极、以及所述沟道区对应。
16.根据权利要求15所述的阵列基板，其特征在于，所述钝化层的厚度为
所述有机绝缘层的厚度为1.5～2.2μm。
17.根据权利要求12所述的阵列基板，其特征在于，所述有机绝缘层平铺于所述衬底上；
所述有机绝缘层包括第一部分和第二部分；所述第一部分与所述数据线、所述源极和所述漏极、以及所述沟道区对应；所述第二部分对应其他区域；
所述第一部分的厚度为1.8～2.7μm，所述第二部分的厚度为
所述钝化层的厚度为
18.根据权利要求12-17任一项所述的阵列基板，其特征在于，所述半导体层包括a-si层和欧姆接触层。
19.一种显示面板，其特征在于，包括权利要求12-18任一项所述的阵列基板。
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