WO2013152458A1 - 一种薄膜晶体管存储器及其制备方法 - Google Patents

一种薄膜晶体管存储器及其制备方法 Download PDF

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WO2013152458A1
WO2013152458A1 PCT/CN2012/000549 CN2012000549W WO2013152458A1 WO 2013152458 A1 WO2013152458 A1 WO 2013152458A1 CN 2012000549 W CN2012000549 W CN 2012000549W WO 2013152458 A1 WO2013152458 A1 WO 2013152458A1
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layer
thin film
charge
film transistor
source
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PCT/CN2012/000549
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English (en)
French (fr)
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丁士进
陈笋
崔兴美
王鹏飞
张卫
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复旦大学
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Priority to EP12794625.9A priority Critical patent/EP2672514A4/en
Publication of WO2013152458A1 publication Critical patent/WO2013152458A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation

Definitions

  • Non-volatile memory is an indispensable component in modern electronic devices. Most of the non-volatile memories on the market today are still based on silicon-based devices. However, the conventional floating gate structure non-volatile memory based on a single crystal silicon substrate is complicated in manufacturing process and usually involves a high temperature process, so it is difficult to fabricate an embedded non-volatile memory on a glass substrate, thereby causing integration thereof. Limited to the display panel.
  • a non-volatile memory based on a thin film transistor (TFT) structure has attracted wide attention.
  • the memory can be fabricated not only on glass or flexible substrates, but also in a process that is well compatible with conventional TFT process processes.
  • SOP system packaging area
  • TFT memories are mostly concentrated on TFT memories in which polysilicon is used as a channel.
  • polysilicon-based TFT memories are not only ideal in terms of erasing efficiency and data retention, but also after the application of source or drain bias stress, the threshold voltage fluctuations are more obvious.
  • An object of the present invention is to provide a thin film transistor memory having a large erase window, good data retention performance, fast erase speed, and stable threshold voltage. It is still another object of the present invention to provide a method of preparing the above memory.
  • the present invention provides a thin film transistor memory with a gate electrode as The substrate, from bottom to top, has: a charge blocking layer; a charge trapping layer of a double-layered metal nanocrystal; a charge tunneling layer of a symmetric stacked structure; an active region of the device; a source and a drain electrode;
  • the substrate may be selected from heavily doped P-type single crystal silicon wafers, heavily doped N-type single crystal silicon wafers, ITO thin films, metal silicide films, and other low-resistance conductive materials;
  • the charge blocking layer is an A1 2 0 3 film grown by atomic layer deposition and has a thickness of 15-200 nm.
  • the charge trapping layer is a two-layer metal nanocrystal structure comprising a first metal nanocrystalline layer, an insulating dielectric layer and a second metal nanocrystalline layer sequentially grown from bottom to top by a method of atomic layer deposition.
  • a charge trapping layer a material of the first metal nanocrystal layer and the second metal nanocrystal layer: (any one of 3 ⁇ 4 nanocrystals and Pt nanocrystals, that is, the first metal nanocrystal layer and the second metal
  • the nanocrystalline layer may be the same material (such as RuO x nanocrystals) or different material nanocrystals (such as Pt nanocrystals and RuO x nanocrystals).
  • RuO x nanocrystals are a composite of cerium and cerium oxide, 1 > ⁇ > 0 ⁇
  • the charge tunneling layer is a symmetric stacked structure comprising a first single layer, a second single layer and a third single layer sequentially grown from bottom to top by a method of atomic layer deposition, wherein the second single The layer is ⁇ «3 ⁇ 4, the first single layer is the same as the third single layer material, and ⁇ 2 ⁇ 3 or Si o 2 is selected;
  • the active region of the device is an IGZO thin film grown by magnetron sputtering.
  • the thickness of the thin film is 10-120 nm, and the IGZO active region is formed by a standard photolithography process and a wet etching method.
  • the gate electrode substrate is a heavily doped P-type single crystal silicon wafer.
  • the areal density of the first metal nanocrystal layer and the second metal nanocrystal layer is In order to increase the storage density of the charge, the memory erase window is enlarged, and the data retention capability is improved.
  • the low surface density of the nanocrystalline layer is not conducive to obtaining sufficient charge storage effect. If the density is too high, the nanocrystals are too close to each other, which easily leads to charge loss, and reduces the data retention capability of the memory.
  • each of the single layer films has a thickness of from 1 to 10 nm, and the first and third single layers have the same thickness.
  • the IGZO thin film has a thickness of 10 to 120 nm.
  • the source and drain electrodes are A1 or Ag electrodes formed by a lift-off method, and the electrode has a thickness of 50-250 nm.
  • Non-volatile TFT memory has great potential applications in advanced system panel or system package (SOP) technology.
  • SOP system panel or system package
  • the present invention uses a two-layer structure of metal nanocrystals and a laminated structure film as charge trapping layers and tunneling layers, respectively. , can effectively increase the memory storage window, improve the erasing speed, enhance the data retention of the device and the tolerance of repeated erasing.
  • the invention also provides a method for preparing the above-mentioned thin film transistor memory, the method comprising: Step 1: performing standard cleaning on the substrate, the substrate can be selected from heavily doped P-type single crystal silicon wafer, heavily doped N-type single crystal silicon wafer, ITO thin film, metal silicide film and other low-resistance conductive materials; preferably, a heavily doped P-type single crystal silicon wafer having a resistivity of 0.008-0.100 ⁇ is used as a substrate, Perform standard cleaning and remove the oxide layer on the surface of the silicon wafer with hydrofluoric acid;
  • Step 2 depositing a charge blocking layer on the substrate by atomic layer deposition, the charge blocking layer is ⁇ 1 2 0 3 , the thickness is 15-200 nm, and the deposition temperature is controlled at 100-300 ° C.
  • the source is trimethylaluminum and water vapor.
  • Step 3 depositing a first metal nanocrystalline layer, an insulating dielectric layer, and a second metal nanocrystalline layer on the charge blocking layer from bottom to top by atomic layer deposition;
  • Step 4 depositing a first single layer, a second single layer and a third single layer of the stacked structure from bottom to top on the second metal nanocrystalline layer by atomic layer deposition to form a symmetric laminated structure.
  • the reactive sources of SiO 2 film is tris (dimethylamino) silane and oxygen
  • reactive sources of A1 2 0 3 film is trimethylaluminum and water vapor
  • ⁇ reaction source 2 film is tetrakis (ethylmethylamino ) ⁇ and water vapor.
  • the deposition temperatures of the Si0 2 , A1 2 0 3 and HfD 2 films are all controlled within the range of 100-300 °C.
  • Each of the single-layer films in the laminate structure has a thickness of from 1 to 10 nm, and the thickness of the first single layer is the same as that of the third single layer.
  • Step 5 depositing a layer of IGZO film on the third single layer by magnetron sputtering, the film has a thickness of 10-120 nm, a sputtering power of 50-200 W, and a ratio of oxygen to argon of 1:1. -1 : 100, deposition temperature is 20-100 ° C ;
  • Step 6 spin-coating a layer of the first photoresist on the IGZO film, forming a protective layer of the active region of the device on the first photoresist by using a standard photolithography method; then, using the wet etching method to the active region
  • the IGZO film is etched by using an IGZO film having a concentration of 0.01% to 2%, and the IGZO film outside the active region is etched for an etching time of 10-600 s;
  • Step 7 removing the first photoresist to form an active region of a single device
  • Step 8 Spin-coating a second photoresist on the third single layer of the laminated structure and the IGZO film; Forming source and drain opening regions of the device on the second photoresist by photolithography; Step 9. Depositing a source and drain electrode layer by electron beam evaporation to a thickness of 50-250 nm; Step 10 The second photoresist and the source and drain electrode layers deposited thereon are removed by a lift-off method to form source and drain electrodes of the device.
  • the device is annealed in a nitrogen atmosphere at 250 ° C for 0.5 to 1.5 hours to improve the performance and stability of the device.
  • the materials of the first metal nanocrystal layer and the second metal nanocrystal layer may be the same or different, and specifically, the RuO x nanocrystal and the Pt nanocrystal may be selected.
  • any one of the RuO x nanocrystals is a composite of lanthanum and cerium oxide, l >x>0; the reaction source of the RuO x nanocrystal is bis(cyclopentadienyl) ruthenium and oxygen; wherein the insulating medium
  • the material of the layer is selected to be A1 2 0 3 or SiO 2 ; the thickness of the insulating dielectric layer is 5-50 nm; the reaction source of the A1 2 0 3 film is trimethylaluminum and water vapor.
  • the material of the source and drain electrode layers is A1 or Ag.
  • Using double-layer nanocrystals as the trapping layer of the thin film transistor memory can increase the storage density of the charge, expand the erase window of the memory, and improve the data retention capability.
  • Using a symmetrical laminated film as the tunneling layer of the thin film transistor memory can improve the erasing speed of the device and reduce the operating voltage of the device without affecting data retention.
  • amorphous IGZO thin film as the active region of the thin film transistor memory provides uniform carrier mobility for the device and enhances the uniformity of memory electrical performance.
  • the present invention has a good application prospect in transparent and flexible electronic devices.
  • the growth of metal nanocrystals by atomic layer deposition can be carried out at temperatures as low as 400 ° C, thus reducing the thermal budget during device fabrication and being compatible with conventional TFT processes.
  • the use of atomic layer deposition techniques to grow a dielectric film not only allows precise control of the thickness of the film, but also provides a high quality insulating film. In particular, in the formation of a stacked structure charge tunneling layer, it exhibits digital controllability.
  • the present invention uses an atomic layer deposition technique to prepare a charge blocking layer, a charge trapping layer, and a charge
  • the tunneling layer can therefore be completed sequentially in a series of atomic layer deposition systems, avoiding the transfer between different devices and the contamination caused by exposure to air.
  • FIG. 1 is a schematic view of depositing a charge blocking layer A1 2 0 3 film on a heavily doped P-type single crystal silicon wafer substrate.
  • FIG. 2 is a schematic view showing the structure of depositing a first metal nanocrystal layer, an insulating dielectric layer, and a second metal nanocrystal layer in this order from bottom to top on an A1 2 0 3 film.
  • FIG 3 is a schematic view showing a stacked structure film of Si0 2 , HfO 2 , Si0 2 or A1 2 0 3 , Hf0 2 , and A1 2 0 3 sequentially deposited from the bottom to the top on the second metal nanocrystal layer.
  • Figure 4 is a schematic illustration of the deposition of an IGZO film on a laminated structure film.
  • Figure 5 is a cross-sectional view after wet etching of an IGZO film.
  • Figure 6 is a diagram showing the formation of the active region of the device.
  • Figure 7 is a schematic illustration of the source and drain opening regions of a device formed on a photoresist.
  • Fig. 8 is a schematic view showing the deposition of the metal electrode material Ag or A1.
  • Figure 9 is a schematic illustration of the source and drain electrodes of a device formed by a lift-off method. The best way to implement the invention
  • FIG. 9 is a schematic structural diagram of a thin film transistor memory of the present invention.
  • the memory has a gate electrode 200 as a substrate, and from bottom to top: a charge blocking layer 201; a charge trapping layer comprising a double-layer metal nanocrystal structure; a charge tunneling layer of a symmetric stacked structure; an active region of the device; a source and a drain electrode; wherein - the gate electrode substrate 200 can be selected from a heavily doped P-type single crystal silicon wafer, a heavily doped N-type Monocrystalline silicon wafer, ITO thin film, metal silicide film and other low resistance conductive materials;
  • the charge blocking layer 201 is an A1 2 0 3 film grown by an atomic layer deposition technique, and has a thickness of 15-200 legs;
  • the double-layer metal nanocrystalline charge trapping layer is formed by atomic layer deposition technology, from bottom to top
  • the grown first metal nanocrystal layer 202, the insulating dielectric layer 203 and the second metal nanocrystalline layer 204 are composed.
  • the first metal nanocrystal layer and the second metal nanocrystal layer may be the same material (such as RuO x nanocrystals, wherein 1 >x>0), or may be different material nanocrystals (such as Pt nanocrystals and respectively) RuO x nanocrystals).
  • the surface density of each layer of nanocrystals is SxK ⁇ Sxli ⁇ cm' ⁇
  • the dielectric layer between the two layers of nanocrystals is A1 2 0 3 or Si0 2 , and the thickness of the insulating dielectric layer is 5-50 nm.
  • the RuO x nanocrystals are a composite of cerium and cerium oxide.
  • the stacked structure charge tunneling layer is an Al 2 O 3 /H 0 2 /Al 2 O 3 or Si0 2 /Hf0 2 /Si0 2 stacked structure sequentially grown from bottom to top by an atomic layer deposition technique. film.
  • each of the single-layer films has a thickness of from 1 to 10 nm, and the first and third single layers have the same thickness.
  • the active region of the device is an indium gallium zinc oxide (IGZO) film grown by magnetron sputtering, and the thickness of the film is 10-120 nm.
  • IGZO active region is formed by a standard photolithography process and a wet etching method.
  • the source and drain electrodes are A1 or Ag electrodes formed by a lift-off method, and the electrode thickness is 50-250 nm.
  • Step 1 Standardly clean the heavily doped P-type single crystal silicon wafer as a substrate, and remove the oxide layer on the surface of the silicon wafer with hydrofluoric acid.
  • the resistivity of the silicon wafer is 0.008-0.010 ⁇ .
  • Step 2 A layer of charge blocking layer 201 is grown on the substrate 200 by atomic layer deposition techniques, as shown in FIG.
  • the substrate 200 is a heavily doped ⁇ -type single crystal silicon wafer after cleaning, the charge blocking layer 201 is ⁇ 1 2 0 3 , and the deposition temperature is controlled at about 100 to 300 ° C, preferably 200 ° C, and the reaction source is Trimethylaluminum and water vapor, the film has a thickness of 15 to 200 nm, preferably 70 nm.
  • Step 3 depositing a first metal nanocrystal layer 202, an insulating dielectric layer 203, and a second metal nanocrystal layer 204 on the charge blocking layer 201 from bottom to top by atomic layer deposition technique, as shown in FIG.
  • the metal nanocrystal material of the first metal nanocrystal layer 202 and the second metal nanocrystal layer 204 may be selected from the same material or different materials, such as the first metal nanocrystal layer 202 and the second metal nanocrystal layer 204. Both are 1 11 (nanocrystals.
  • the insulating dielectric layer 203 is an A1 2 0 3 film.
  • the reaction source of RuO x nanocrystals is bis(cyclopentadienyl) ruthenium and oxygen, and the areal density of single-layer RuO x nanocrystals is about SxloH.
  • the reaction source of the cm ⁇ A1 2 0 3 film is trimethylaluminum and water vapor, and has a thickness of 5 to 50 nm, preferably 10 nm.
  • Step 4 using atomic layer deposition techniques on the second metal nanocrystalline layer 204 from bottom to top
  • a first single layer 205, a second single layer 206, and a third single layer 207 of a stacked structure are deposited, as shown in FIG. 3, to form a symmetric laminated film such as Al 2 0 3 /HfD 2 /Al 2 0 3 .
  • the first single layer 205 and the third single layer 207 are A1 2 0 3
  • the second single layer 206 is ⁇ 2 .
  • the reaction source of the A1 2 0 3 film is trimethyl aluminum and water vapor
  • the reaction source of the Hf0 2 film is tetrakis (ethyl methylamino) hydrazine and water vapor.
  • the deposition temperature of the A1 2 0 3 and HfO 2 films is controlled to be 100 to 300 ° (:, preferably 200 ° C, and the thickness of each of the single-layer films is about 1 to 10 nm, preferably 6 nm.
  • Step 5 depositing an IGZO film 208 on the third single layer 207 by magnetron sputtering, as shown in FIG.
  • the sputtering power is controlled at 50 to 200 W.
  • the control is about 150 W
  • the ratio of oxygen to argon is about 1:1 to 1:100.
  • the ratio is 1:7
  • the deposition temperature is The thickness of 20-100 is preferably room temperature, and the thickness is about 10 to 120 nm, preferably 60 nm.
  • Step 6 a layer of the first photoresist 209 is spin-coated on the IGZO film 208, and a protective layer of the active region of the device is formed on the first photoresist 209 by standard photolithography; then, by wet etching,
  • the IGZO film outside the active region is etched by using hydrochloric acid, nitric acid, phosphoric acid or hydrofluoric acid at a concentration of 0.01% to 2%, and the etching time is 10-600 s, as shown in FIG. Cross-sectional view after etching;
  • the IGZO film 208 outside the active region is etched using hydrochloric acid at a concentration of 1%.
  • Step 7 removing the first photoresist 209 to form an active region of a single device, as shown in FIG. Step 8.
  • a second photoresist 210 is spin-coated on the third single layer 207 of the laminated structure and the IGZO film 208.
  • the source and drain opening regions of the device are formed on the second photoresist 210 by photolithography, as shown in FIG.
  • a source and drain electrode layer 211 is deposited by electron beam evaporation, as shown in FIG. 8.
  • the material of the source and drain electrode layers 211 is selected from a metal A1 or Ag and has a thickness of about 50 to 250 nm. Al is preferred and has a thickness of about 100 nm.
  • Step 10 removing the second photoresist and the source and drain electrode layers 211 deposited thereon by a lift-off method to form source and drain electrodes of the device, as shown in FIG.
  • Step 11 The fabricated device was annealed at 250 ° C for 0.5 to 1.5 hours, preferably for 1 hour, in a nitrogen atmosphere.
  • the substrate material of the present invention is described herein as a heavily doped P-type single crystal silicon wafer, but the present invention is not limited thereto, and the substrate material of the present invention may be of various types, such as heavily doped N-type.
  • Monocrystalline silicon wafers, ITO thin films, metal silicide films, and other low-resistance conductive materials Any common skill in the art It is within the scope of the present invention to make equivalent changes without departing from the spirit and scope of the invention.
  • the invention proposes a TFT memory based on IGZO (InGaZnO) thin film, which adopts double-layer metal nanocrystal and symmetric laminated structure film as the trapping layer and tunneling layer of the TFT memory, respectively, which can effectively expand the erasing window of the memory and improve Data erasing speed, enhanced data retention of the device, and resistance to repeated erasing.
  • IGZO InGaZnO

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Abstract

提供一种薄膜晶体管存储器及其制备方法。该存储器以栅电极（200）为衬底，从下至上依次有：电荷阻挡层（201）、电荷俘获层、电荷隧穿层、器件的有源区以及源、漏电极（211）；该电荷阻挡层（201）为通过原子层淀积的方法生长的Al2O3薄膜；该电荷俘获层为双层金属纳米晶结构，其包括通过原子层淀积，自下而上依次生长的第一金属纳米晶层（202）、绝缘介质层（203）及第二金属纳米晶层（204）；该电荷隧穿层为对称叠层结构，其包含通过原子层淀积，自下而上依次生长的SiO2/HfO2/SiO2或Al2O3/HfO2/Al2O3叠层结构薄膜（205-207）；该器件的有源区为采用磁控溅射的方法生长的铟镓锌氧化物（IGZO）薄膜（208），采用标准的光刻工艺和湿法刻蚀的方法形成IGZO有源区。该薄膜晶体管存储器的擦写窗口大、数据保持性能好，擦写速度快、阈值电压稳定，制备工艺简单。

Description

一种薄膜晶体管存储器及其制备方法
技术领域 本发明属于半导体集成电路制造技术领域， 具体涉及一种薄膜晶体管存 储器及其制备方法。 背景技术 非挥发性存储器是现代电子器件中不可缺少的一种元器件， 目前市场上 的非挥发性存储器大部分仍是以硅基器件为主。 然而， 基于单晶硅衬底的传 统浮栅结构非挥发性存储器由于制作工艺复杂， 通常涉及到高温工艺， 因此 很难在玻璃衬底上来制作嵌入式的非挥发性存储器， 从而导致其在集成到显 示面板上时受到限制。
目前， 一种基于薄膜晶体管 （TFT) 结构的非挥发性存储器引起了大家 的广泛关注， 该存储器不仅可以制作在玻璃或柔性衬底上， 而且其制程工艺 能很好的与传统的 TFT制程工艺相兼容，在未来的先进系统面板或系统封装 领域 （SOP)有很大的应用前景。 目前， 关于 TFT存储器的研究大部分集中 在以多晶硅为沟道的 TFT存储器上。 但有研究表明， 基于多晶硅的 TFT存 储器不仅在擦写效率和数据的保持性方面不是很理想， 而且在施加源极或漏 极偏压应力后， 阈值电压的波动也会比较明显。
因此，亟需开发一种擦写效率和数据保持性良好，且阈值电压稳定的 TFT 存储器。 发明的公开
本发明的目的是提供一种擦写窗口大、 数据保持性能好， 擦写速度快、 阈值电压稳定的薄膜晶体管存储器。 本发明的再一目的是提供上述存储器的 制备方法。
为了达到上述目的， 本发明提供了一种薄膜晶体管存储器， 以栅电极为 衬底， 从下至上依次有： 电荷阻挡层； 双层金属纳米晶的电荷俘获层； 对称 叠层结构的电荷隧穿层； 器件的有源区； 源、 漏电极； 其中：
所述衬底可以选择重掺杂的 P型单晶硅片、重掺杂的 N型单晶硅片、 ITO 薄膜、 金属硅化物薄膜以及其他的低阻导电材料；
所述的电荷阻挡层为通过原子层淀积的方法生长的 A1203薄膜， 厚度为 15-200nm。
所述的电荷俘获层为双层金属纳米晶结构， 其包含通过原子层淀积的方 法， 自下而上依次生长的第一金属纳米晶层、 绝缘介质层及第二金属纳米晶 层， 作为电荷俘获层； 该第一金属纳米晶层与第二金属纳米晶层的材料选择 ^(¾纳米晶、 Pt纳米晶中的任意一种， 也就是说，第一金属纳米晶层与第二 金属纳米晶层可以为相同材料（如 RuOx纳米晶）， 也可以为不同材料纳米晶 (如 Pt纳米晶和 RuOx纳米晶）。 两层纳米晶之间的绝缘介质层的材料选择 A1203或 Si02，其厚度为 5-50nm。其中， RuOx纳米晶为钌和氧化钌的复合物， 1 >χ>0 ο
所述的电荷隧穿层为对称叠层结构， 其包含通过原子层淀积的方法， 自 下而上依次生长的第一单层、第二单层及第三单层，其中，第二单层为 Η«¾， 第一单层与第三单层材料相同， 选择 ΑΙ2Ο3或 Sio2;
所述的器件的有源区为采用磁控溅射的方法生长的 IGZO薄膜，该薄膜的 厚度为 10-120nm，采用标准的光刻工艺和湿法刻蚀的方法形成 IGZO有源区。
进一步地， 所述的栅电极衬底为重掺杂的 P型单晶硅片。
上述的薄膜晶体管存储器， 其中， 所述的第一金属纳米晶层与第二金属 纳米晶层的面密度为
Figure imgf000004_0001
以达到提高电荷的存储密度， 扩 大存储器的擦写窗口， 提高数据的保持能力的目的。 该纳米晶层的面密度太 低则不利于获得足够的电荷存储效果， 密度太高则纳米晶之间彼此相邻太 近， 容易导致电荷流失， 反而降低存储器的数据保持能力。
上述的薄膜晶体管存储器， 其中， 所述的电荷隧穿层中， 各单层薄膜厚 度为 l-10nm， 并且第一和第三单层的厚度相同。
上述的薄膜晶体管存储器，其中，所述的 IGZO薄膜的厚度为 10-120nm。 上述的薄膜晶体管存储器， 其中， 所述的源、 漏电极为通过剥离方法形 成的 A1或 Ag电极， 电极厚度为 50-250nm。 非挥发性的 TFT存储器在先进系统面板或系统封装（SOP)技术领域有 很大的潜在应用前景， 本发明采用双层结构金属纳米晶和叠层结构薄膜分别 作为电荷的俘获层和隧穿层， 能有效地增大存储器的存储窗口， 提高擦写速 度， 增强器件的数据保持性以及反复擦写的耐受性。
本发明还提供了一种上述的薄膜晶体管存储器的制备方法，该方法包含: 步骤 1，对衬底进行标准清洗，该衬底可以选择重掺杂的 P型单晶硅片、 重掺杂的 N型单晶硅片、 ITO薄膜、金属硅化物薄膜以及其他的低阻导电材 料； 优选地， 采用电阻率为 0.008-0.100 Ω·αη的重掺杂的 P型单晶硅片作为 衬底， 进行标准的清洗， 并用氢氟酸去除硅片表面的氧化层；
步骤 2， 在衬底上采用原子层淀积的方法生长一层电荷阻挡层， 该电荷 阻挡层为 Α1203， 其厚度为 15-200nm， 淀积温度控制在 100~300°C， 反应源 为三甲基铝和水蒸汽。
步骤 3， 采用原子层淀积的方法在电荷阻挡层上自下而上依次淀积第一 金属纳米晶层、 绝缘介质层、 第二金属纳米晶层；
步骤 4， 采用原子层淀积的方法在第二金属纳米晶层上自下而上依次淀 积叠层结构的第一单层、 第二单层和第三单层， 形成对称叠层结构， 如
Si02/Hf02/Si02或 Al203/HfD2/Al203叠层结构薄膜，作为电荷的隧穿层。其中， Si02薄膜的反应源为三 （二甲氨基）硅烷和氧气， A1203薄膜的反应源为三 甲基铝和水蒸汽， ΗίΌ2薄膜的反应源为四（乙基甲基氨基)铪和水蒸汽。 Si02、 A1203 以及 HfD2薄膜的淀积温度均控制在 100-300 °C范围内。该叠层结构中 的各单层薄膜厚度为 l-10nm， 且第一单层的厚度与第三单层相同。
步骤 5， 采用磁控溅射的方法在第三单层上淀积一层 IGZO薄膜， 该薄 膜的厚度为 10-120nm，溅射功率为 50-200w，氧气和氩气的比例为 1:1-1 :100， 淀积温度为 20-100°C ;
步骤 6， 在 IGZO薄膜上旋涂一层第一光刻胶， 利用标准光刻方法在第 一光刻胶上形成器件的有源区保护层； 然后， 利用湿法刻蚀方法对有源区以 外的 IGZO薄膜进行刻蚀， 即利用浓度为 0.01%~2%的盐酸、 硝酸、 磷酸或 氢氟酸， 对有源区之外的 IGZO薄膜进行刻蚀， 刻蚀时间为 10-600S;
步骤 7， 去除第一光刻胶， 形成单个器件的有源区；
步骤 8， 在叠层结构的第三单层及 IGZO薄膜上旋涂一层第二光刻胶； 利用光刻的方法在第二光刻胶上形成器件的源、 漏极开孔区域； 步骤 9，采用电子束蒸发的方法淀积一层源、漏电极层，厚度为 50-250nm; 步骤 10， 采用剥离的方法去除第二光刻胶及其上淀积的源、 漏电极层， 形成器件的源、 漏电极。
上述的薄膜晶体管存储器的制备方法， 其中， 该方法还包含- 步骤 11， 将制作的器件置于氮气的气氛中在 250°C下退火 0.5~1.5小时， 以提高器件的性能和稳定性。
上述的薄膜晶体管存储器的制备方法， 其中， 所述的步骤 3中， 第一金 属纳米晶层与第二金属纳米晶层的材料可以相同或不同， 具体可选择 RuOx 纳米晶、 Pt纳米晶中的任意一种，其中， RuOx纳米晶为钌和氧化钌的复合物， l >x>0; RuOx纳米晶的反应源为双 (环戊二烯)钌和氧气； 其中， 该绝缘介 质层的材料选择 A1203或 Si02; 绝缘介质层的厚度为 5-50nm; A1203薄膜的 反应源为三甲基铝和水蒸汽。
上述的薄膜晶体管存储器的制备方法， 其中， 所述的源、 漏电极层的材 料为 A1或 Ag。
本发明的有益效果为-
1 ) 采用双层纳米晶作为薄膜晶体管存储器的俘获层可以提高电荷的存 储密度， 扩大存储器的擦写窗口， 提高数据的保持能力。
2) 采用对称的叠层结构薄膜作为薄膜晶体管存储器的隧穿层可以在不 影响数据保持性的情况下提高器件的擦写速度， 降低器件的操作电压。
3 ) 采用非晶的 IGZO薄膜作为薄膜晶体管存储器的有源区可以为器件 提供均一的载流子迁移率，增强存储器电学性能的均匀性。此外， 由于 IGZO 薄膜的透光性高、 加工温度低等优点， 使得本发明在透明和柔性电子设备中 具有很好的应用前景。
4) 采用原子层淀积技术生长金属纳米晶， 可以在小于 400°C的低温下 进行，因此降低了器件制作过程中的热预算，并且与通常的 TFT工艺相兼容。 此外， 采用原子层淀积技术生长介质薄膜不仅可以精确地控制薄膜的厚度， 还可以获得高质量的绝缘薄膜。 尤其是在形成叠层结构电荷遂穿层时， 表现 出数字化的控制能力。
5 ) 本发明采用原子层淀积技术制备电荷阻挡层， 电荷俘获层以及电荷 隧穿层， 因此可以在串联的原子层淀积系统中依次完成， 避免了不同设备之 间的转移和暴露于空气所引起的污染。 附图的简要说明
图 1是在重掺杂的 P型单晶硅片衬底上淀积电荷阻挡层 A1203薄膜的示 意图。
图 2是在 A1203薄膜上自下而上依次淀积第一金属纳米晶层、 绝缘介质 层、 第二金属纳米晶层的结构示意图。
图 3是在第二金属纳米晶层上， 自下而上依次淀积 Si02、 HfO2、 Si02 或 A1203、 Hf02、 A1203叠层结构薄膜的示意图。
图 4是在叠成结构薄膜上淀积 IGZO薄膜的示意图。
图 5是湿法刻蚀 IGZO薄膜之后的剖面图。
图 6是器件有源区形成图。
图 7是在光刻胶上形成器件的源、 漏开孔区域的示意图。
图 8是淀积金属电极材料 Ag或 A1的示意图。
图 9是剥离 （lift-off) 方法形成器件的源、 漏电极的示意图。 实现本发明的最佳方式
下面结合附图与具体实施方式对本发明作进一步详细说明。 在图中， 为 了方便说明， 放大或縮小了不同层和区域的尺寸， 所示大小并不代表实际尺 寸， 也不反应尺寸的比例关系。
如图 9所示， 为本发明的薄膜晶体管存储器的结构示意图， 该存储器以 栅电极 200为衬底， 从下至上依次有： 电荷阻挡层 201 ; 包含双层金属纳米 晶结构的电荷俘获层； 对称叠层结构的电荷隧穿层； 器件的有源区； 源、 漏 电极； 其中- 所述的栅电极衬底 200可选择重掺杂的 P型单晶硅片、 重掺杂的 N型单 晶硅片、 ITO薄膜、 金属硅化物薄膜以及其他的低阻导电材料；
所述的电荷阻挡层 201为通过原子层淀积技术生长的 A1203薄膜，厚度为 15-200腿；
所述的双层金属纳米晶电荷俘获层为通过原子层淀积技术，自下而上依次 生长的第一金属纳米晶层 202、 绝缘介质层 203及第二金属纳米晶层 204组 成。其中， 第一金属纳米晶层和第二金属纳米晶层可以为相同材料（如 RuOx 纳米晶， 其中， 1 > x>0)， 也可以为不同材料纳米晶 （如分别采用 Pt纳米 晶和 RuOx纳米晶）。 每层纳米晶的面密度为 SxK^^Sxli^ cm'^ 两层纳米 晶之间的绝缘介质层为 A1203或 Si02， 该绝缘介质层的厚度为 5-50nm。所述 的 RuOx纳米晶为钌和氧化钌的复合物。
所述的叠层结构电荷隧穿层为通过原子层淀积技术， 自下而上依次生长 的 Al2O3/H 02/Al2O3或 Si02/Hf02/Si02叠层结构薄膜。 该叠层结构中， 各单 层薄膜厚度为 l-10nm， 并且第一和第三单层的厚度相同。
所述的器件的有源区为铟镓锌氧化物（IGZO)薄膜， 采用磁控溅射技术 生长， 薄膜的厚度为 10-120nm。采用标准的光刻工艺和湿法刻蚀的方法形成 IGZO有源区。
所述的源、 漏电极为通过剥离 （lift-off) 方法形成的 A1或 Ag电极， 电 极厚度为 50-250nm。
上述的薄膜晶体管存储器的制备方法如下：
步骤 1， 对作为衬底的重掺杂的 P型单晶硅片进行标准清洗， 并用氢氟 酸去掉硅片表面的氧化层， 硅片的电阻率为 0.008-0.010 Ω·αη。
步骤 2，在衬底 200上采用原子层淀积技术生长一层电荷阻挡层 201，如 图 1所示。其中，衬底 200为清洗后的重掺杂 Ρ型单晶硅片， 电荷阻挡层 201 为 Α1203， 淀积温度控制在 100〜300 °C左右， 优选为 200°C， 反应源为三甲基 铝和水蒸汽， 膜的厚度为 15~200nm， 优选 70nm。
步骤 3， 采用原子层淀积技术在电荷阻挡层 201上自下而上依次淀积第 一金属纳米晶层 202、绝缘介质层 203、第二金属纳米晶层 204,如图 2所示。 其中， 第一金属纳米晶层 202和第二金属纳米晶层 204的金属纳米晶材料， 可以选择相同材料， 也可以选择不同材料， 比如第一金属纳米晶层 202和第 二金属纳米晶层 204均为 1 11( 纳米晶。绝缘介质层 203为 A1203薄膜。 RuOx 纳米晶的反应源为双 (环戊二烯)钌和氧气， 单层 RuOx纳米晶的面密度约为 SxloH cm^ A1203薄膜的反应源为三甲基铝和水蒸汽， 厚度为 5~50nm， 优 选为 10nm。
步骤 4， 采用原子层淀积技术在第二金属纳米晶层 204上自下而上依次 淀积叠层结构的第一单层 205、 第二单层 206和第三单层 207， 如图 3所示， 形成对称叠层结构薄膜， 比如 Al203/HfD2/Al203。 其中， 第一单层 205和第 三单层 207为 A1203， 第二单层 206为 ΗίΌ2。其中， A1203薄膜的反应源为三 甲基铝和水蒸汽， Hf02薄膜的反应源为四（乙基甲基氨基）铪和水蒸汽。 A1203 和 HfO2薄膜的淀积温度均控制在 100~300° (：， 优选为 200°C， 各单层薄膜的 厚度约为 l~10nm， 优选 6nm。
步骤 5， 采用磁控溅射技术在第三单层 207上淀积一层 IGZO薄膜 208， 如图 4所示。 溅射功率控制在 50~200w， 更优的实施例中， 控制在 150w左 右， 氧气 *氩气的比例约为 1:1-1:100， 优选地， 该比例为 1:7， 淀积温度为 20-100 优选为室温， 淀积厚度约为 10〜120nm， 优选为 60nm。
步骤 6，在 IGZO薄膜 208上旋涂一层第一光刻胶 209，利用标准光刻方 法在第一光刻胶 209上形成器件的有源区保护层； 然后， 利用湿法刻蚀， 即 利用浓度为 0.01%~2%的盐酸、硝酸、磷酸或氢氟酸， 对有源区之外的 IGZO 薄膜进行刻蚀，刻蚀时间为 10-600s，如图 5所示，为该湿法刻蚀后的剖面图； 更优的实施例中，采用浓度为 1%的盐酸对有源区之外的 IGZO薄膜 208进行 刻蚀。
步骤 7， 去除第一光刻胶 209， 形成单个器件的有源区， 如图 6所示。 步骤 8， 在叠层结构的第三单层 207及 IGZO薄膜 208上旋涂一层第二 光刻胶 210。 利用光刻的方法在第二光刻胶 210上形成器件的源、 漏极开孔 区域， 如图 7所示。
步骤 9，采用电子束蒸发的方法淀积一层源、漏电极层 211，如图 8所示， 其中， 源、 漏电极层 211的材料， 选择金属 A1或 Ag， 厚度约为 50~250nm， 优选 Al， 厚度约为 100nm。
步骤 10， 采用剥离 （lift-off) 的方法去除第二光刻胶及其上淀积的源、 漏电极层 211， 形成器件的源、 漏电极， 如图 9所示。
步骤 11， 将制作的器件置于氮气的气氛中在 250°C下退火 0.5~1.5小时， 优选 1小时。
在此将本发明的衬底材料描述为重掺杂的 P型单晶硅片， 但本发明并不 局限于此，本发明的衬底材料可以是多种类型，例如重掺杂的 N型单晶硅片、 ITO薄膜、 金属硅化物薄膜以及其他的低阻导电材料。 任何本领域普通技术 人员， 在不脱离本发明的精神范围内， 可做等效变化， 均属于本发明的保护 范围。
本发明提出基于 IGZO (InGaZnO) 薄膜的 TFT存储器， 采用双层金属 纳米晶和对称的叠层结构薄膜分别作为 TFT存储器的俘获层和隧穿层，将能 有效地扩大存储器的擦写窗口、 提高数据的擦写速度、 增强器件的数据保持 性和反复擦写的耐受性。
尽管本发明的内容已经通 ¾：上述优选实施例作了详细介绍， 但应当认识 到上述的描述不应被认为是对本发明的限制。 在本领域技术人员阅读了上述 内容后， 对于本发明的多种修改和替代都将是显而易见的。 因此， 本发明的 保护范围应由所附的权利要求来限定。

Claims

权利要求
1. 一种薄膜晶体管存储器， 其特征在于， 该存储器以栅电极为衬底 （200)， 从下至上依次设置有： 电荷阻挡层（201 ); 电荷俘获层； 电荷隧穿层； 器 件的有源区； 及， 源、 漏电极；
其中， 所述的电荷阻挡层 （201 ) 为通过原子层淀积的方法生长的 A1203薄膜；
所述的电荷俘获层为双层金属纳米晶结构， 其包含通过原子层淀积 的方法，自下而上依次生长的第一金属纳米晶层 (202)、绝缘介质层 (203 ) 及第二金属纳米晶层 （204); 该第一金属纳米晶层（202)与第二金属纳 米晶层（204)的材料选择 ^(¾纳米晶、 Pt纳米晶中的任意一种， 其中， RuOx纳米晶为钌和氧化钌的复合物， 1〉χ〉0; 该绝缘介质层 （203 ) 的 材料选择 A1203或 Si02;
所述的电荷隧穿层为对称叠层结构，其包含通过原子层淀积的方法， 自下而上依次生长的第一单层（205)、第二单层（206)及第三单层（207)， 其中， 第二单层 （206) 为 HfD2， 第一单层 （205 ) 与第三单层 （207) 的材料相同， 选择 A1203或 Si02;
所述的器件的有源区为采用磁控溅射的方法生长的 IGZO薄膜 (208)。
2. 如权利要求 1所述的薄膜晶体管存储器， 其特征在于， 所述的栅电极衬底
(200) 为重掺杂的 P型单晶硅片。
3. 如权利要求 1或 2所述的薄膜晶体管存储器， 其特征在于， 所述的第一金 属纳米晶层 （202 ) 与第二金属纳米晶层 （204 ) 的面密度为 δχΐθ11 5xl012cm-2。
4. 如权利要求 1或 2所述的薄膜晶体管存储器， 其特征在于， 所述的电荷隧 穿层中，各单层薄膜厚度为 l-10nm，并且第一单层 (205)和第三单层 (207) 的厚度相同。
5. 如权利要求 4所述的薄膜晶体管存储器， 其特征在于， 所述的 IGZO薄膜
(208) 的厚度为 10-120nm。
6. 如权利要求 1或 2或 5所述的薄膜晶体管存储器，其特征在于，所述的源、 漏电极为通过剥离方法形成的 A1或 Ag电极。
7. —种根据权利要求 1所述的薄膜晶体管存储器的制备方法， 其特征在于， 该方法包含：
步骤 1， 对衬底 （200) 进行标准清洗；
步骤 2， 在衬底 （200) 上采用原子层淀积的方法生长一层电荷阻挡 层 （201 )， 该电荷阻挡层（201 )为 A1203， 淀积温度控制在 100~300 °C， 反应源为三甲基铝和水蒸汽；
步骤 3， 采用原子层淀积的方法在电荷阻挡层 （201 )上自下而上依 次淀积第一金属纳米晶层 （202)、 绝缘介质层 （203 )、 第二金属纳米晶 层 （204);
步骤 4， 采用原子层淀积的方法在第二金属纳米晶层 （204) 上自下 而上依次淀积叠层结构的第一单层（205)、 第二单层（206)和第三单层 (207), 形成对称叠层结构；
步骤 5， 采用磁控溅射的方法在第三单层（207)上淀积一层 IGZO薄 膜 （208)， 溅射功率为 50-200W, 氧气和氩气的比例为 1:1-1:100， 淀积 温度为 20-100°C ;
步骤 6， 在 IGZO薄膜（208)上旋涂一层第一光刻胶（209)， 利用标 准光刻方法在第一光刻胶（209)上形成器件的有源区保护层； 然后， 利 用浓度为 0.01%~2%的盐酸、硝酸、磷酸或氢氟酸，对有源区之外的 IGZO 薄膜 （208) 进行刻蚀， 刻蚀时间为 10-600S;
步骤 7, 去除第一光刻胶 （209), 形成单个器件的有源区；
步骤 8， 在叠层结构的第三单层 （207)及 IGZO薄膜 （208) 上旋涂 一层第二光刻胶（210); 利用光刻的方法在第二光刻胶（210)上形成器 件的源、 漏极开孔区域；
步骤 9， 采用电子束蒸发的方法淀积一层源、 漏电极层 （211 );
步骤 10， 采用剥离的方法去除第二光刻胶及其上淀积的源、漏电极层 (211 ), 形成器件的源、 漏电极。
8. 如权利要求 7所述的薄膜晶体管存储器的制备方法， 其特征在于， 该方法 还包含： 步骤 11， 将制作的器件置于氮气的气氛中在 250°C下退火 0.5~1.5小 时。
9. 如权利要求 7或 8所述的薄膜晶体管存储器的制备方法， 其特征在于， 所 述的步骤 3中， 第一金属纳米晶层与第二金属纳米晶层的材料选择 RuOx 纳米晶、 Pt纳米晶中的任意一种， 其中， RuOx纳米晶为钌和氧化钌的复 合物， 1 >χ〉0; 该绝缘介质层的材料选择 A1203或 Si02; 其中， 1 11( 纳 米晶的反应源为双 (环戊二烯)钌和氧气 ; A1203薄膜的反应源为三甲基铝和 水蒸汽。
10.如权利要求 9所述的薄膜晶体管存储器的制备方法， 其特征在于， 所述的 源、 漏电极层的材料为 A1或 Ag。
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