Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/40—Vertical BJTs
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D18/00—Thyristors
  • H10D18/60—Gate-turn-off devices 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/192—Base regions of thyristors
  • H10D62/199—Anode base regions of thyristors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/393—Body regions of DMOS transistors or IGBTs 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/60—Impurity distributions or concentrations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide

Definitions

• the present disclosure relates to semiconductor devices fabricated in Silicon Carbide (SiC).
• SiC Silicon Carbide
• SiC is a desirable material for high-power and high- temperature semiconductor devices due to its high breakdown field, high thermal conductivity, and wide bandgap.
• an efficient edge termination is needed. More specifically, field crowding at the edge of the device results in device breakdown at the edge of the device, which in turn decreases the blocking voltage of the device well below the ideal blocking voltage (i.e., the blocking voltage of the ideal parallel-plane device).
• edge termination is an important issue in the design of SiC semiconductor devices and particularly for high-power SiC semiconductor devices.
• FIG. 1 illustrates an exemplary SiC semiconductor device, namely, a thyristor 10 that includes a number of JTE wells 12, 14, and 1 6.
• the thyristor 10 includes a substrate 18, an injection layer 20, a field stop layer 22, a drift layer 24, a base layer 26, and an anode layer 28.
• the base layer 26 is etched down to the drift layer 24 as illustrated.
• the JTE wells 12, 14, and 1 6 are then formed by ion implantation into an exposed surface of the drift layer 24.
• An anode contact 30 is formed on the anode layer 28, a cathode contact 32 is formed on a bottom surface of the substrate 18 opposite the injection layer 20, and gate contacts 34 and 36 are formed on corresponding gate regions 38 and 40 in the base layer 26.
• a corner 42 is formed. The corner 42 causes electric field crowding, which in turn decreases the blocking voltage of the thyristor 10 to less than the ideal blocking voltage.
• the present disclosure relates to a Silicon Carbide (SiC)
• the semiconductor device having both a high blocking voltage and low on-resistance.
• the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (mQ-cm 2 ) and even more preferably less than 5 mQ-cm 2 .
• the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 mQ-cm 2 and even more preferably less than 7 mQ-cm 2 .
• the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 mQ-cm 2 and even more preferably less than 10 mQ-cm 2 .
• a semiconductor device includes a negative bevel edge termination that includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope.
• the negative bevel edge termination results in a high blocking voltage for the semiconductor device.
• the negative bevel edge termination includes at least five steps. In another embodiment, the negative bevel edge termination includes at least ten steps. In yet another embodiment, the negative bevel edge termination includes at least fifteen steps.
• the desired slope is, in one
• the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kV and an on-resistance of less than 10 mQ-cm 2 and even more preferably less than 5 mQ-cm 2 . In another embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 15 kV and an on-resistance of less than 15 mQ-cm 2 and even more preferably less than 7 mQ-cm 2 .
• the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 20 kV and an on-resistance of less than 20 mQ-cm 2 and even more preferably less than 10 mQ-cm 2 .
• the semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode. Further, in one embodiment, the semiconductor device has a die area greater than or equal to one centimeter squared.
• Figure 1 illustrates a Silicon Carbide (SiC) thyristor including a conventional Junction Termination Extension (JTE) edge termination;
• SiC Silicon Carbide
• JTE Junction Termination Extension
• Figure 2 illustrates a SiC thyristor including a negative bevel edge termination according to one embodiment of the present disclosure
• Figure 3 illustrates the negative bevel edge termination of Figure 2 in more detail where negative bevel edge termination is implemented as a multi- step negative bevel edge termination that includes a number of steps formed on a surface of a corresponding semiconductor layer according to one embodiment of the present disclosure
• Figure 4 graphically illustrates an electric field in the multi-step negative bevel edge termination of Figure 3 as compared to that of a JTE termination according to one embodiment of the present disclosure
• Figure 5 graphically illustrates a blocking voltage resulting from the multi-step negative bevel edge termination of Figure 3 as compared to that of a JTE termination according to one embodiment of the present disclosure
• Figure 6 illustrates a thyristor including a negative bevel edge termination formed by counter-doping the base layer according to another embodiment of the present disclosure
• Figure 7 illustrates an embodiment where a multi-step negative bevel edge termination is provided by first forming a sacrificial layer on the base layer and then etching the sacrificial layer such that the desired multi-step
• Figure 8 illustrates a SiC Bipolar Junction Transistor (BJT) having a negative bevel edge termination like that illustrated in Figure 3 according to one embodiment of the present disclosure
• Figure 9 illustrates a SiC BJT having a negative bevel edge termination formed by counter-doping the base layer according to another embodiment of the present disclosure
• Figure 10 illustrates a P-type SiC Insulated Gate Bipolar Transistor
• IGBT IGBT having a negative bevel edge termination like that illustrated in Figure 3 according to one embodiment of the present disclosure
• Figure 1 1 illustrates a P-type SiC IGBT having a negative bevel edge termination formed by counter-doping the base layer according to another embodiment of the present disclosure
• Figure 12 illustrates an n-type SiC IGBT having a negative bevel edge termination like that illustrated in Figure 3 according to one embodiment of the present disclosure
• Figure 13 illustrates an n-type SiC IGBT having a negative bevel edge termination formed by counter-doping the base layer according to another embodiment of the present disclosure
• Figure 14 illustrates a SiC PIN diode having a negative bevel edge termination like that illustrated in Figure 3 according to one embodiment of the present disclosure
• Figure 15 illustrates a SiC PIN diode having a negative bevel edge termination formed by counter-doping one of the semiconductor layers according to another embodiment of the present disclosure
• Figure 1 6 illustrates a SiC U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET) having a negative bevel edge termination like that illustrated in Figure 3 according to another embodiment of the present disclosure;
• UOSFET Metal-Oxide-Semiconductor Field Effect Transistor
• Figure 17 illustrates a SiC UMOSFET having a negative bevel edge termination formed by counter-doping the base layer according to another embodiment of the present disclosure
• Figure 18 graphically illustrates carrier distribution within a power thyristor in the on-state
• Figure 19 graphically illustrates carrier distribution under high-level injection conditions for a P-i-N rectifier
• Figure 20 graphically illustrates carrier distribution as a function of high-level carrier lifetime under high-level injection conditions for a P-i-N rectifier
• Figures 21 A through 21 D illustrates a process for forming the SiC thyristor of Figure 2 that includes a number of carrier lifetime enhancement techniques that result in a low on-resistance for the SiC thyristor according to one embodiment of the present disclosure
• Figures 22A through 22C graphically illustrate measurements of carrier lifetime for a number of exemplary thyristors formed according to the process of Figures 21 A through 21 D; and [0034] Figure 23 graphically illustrates forward condition characteristics including an on-resistance of a thyristor fabricated using carrier lifetime enhancement techniques according to one embodiment of the present disclosure.
• Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
• FIG. 2 illustrates a Silicon Carbide (SiC) thyristor 44 having a negative bevel edge termination 46 according to one embodiment of the present disclosure.
• the thyristor 44 is a Gate Turn-Off (GTO) thyristor.
• GTO Gate Turn-Off
• the thyristor 44 includes a substrate 48, an injection layer 50 on a surface of the substrate 48, a field stop layer 52 on a surface of the injection layer 50 opposite the substrate 48, a drift layer 54 on a surface of the field stop layer 52 opposite the injection layer 50, and a base layer 56 on a surface of the drift layer 54 opposite the field stop layer 52.
• Gate regions 58 and 60 are formed in a surface of the base layer 56 opposite the drift layer 54 and are separated by a desired lateral distance.
• An anode mesa, or region, 62 is on the surface of the base layer 56 between the gate regions 58 and 60.
• An anode contact 64 is on a surface of the anode mesa 62 opposite the base layer 56
• a cathode contact 66 is on a surface of the substrate 48 opposite the injection layer 50
• gate contacts 68 and 70 are on the surface of the base layer 56 over the gate regions 58 and 60, respectively.
• the thyristor 44 is fabricated on a semiconductor die having an area greater than or equal to 1 cm 2 .
• the substrate 48 is preferably a SiC substrate, and the injection layer 50, the field stop layer 52, the drift layer 54, the base layer 56, and the anode mesa 62 are preferably all epitaxial layers of SiC grown on the substrate 48.
• the gate regions 58 and 60 are preferably formed by injecting ions into the base layer 56 via, for example, ion implantation.
• the substrate 48 is highly doped N-type (N+)
• the injection layer 50 is highly doped N- type (N+)
• the field stop layer 52 is highly doped P-type (P+)
• the drift layer 54 is doped P-type (P)
• the base layer 56 is doped N-type (N)
• the gate regions 58 and 60 are highly doped N-type (N+)
• the anode mesa 62 is very highly doped P- type (P++).
• the substrate 48 has doping level in a range of and including 1 x10 18 to 1 x10 19 cm “3 and a thickness in a range of and including about 100 to 350 microns ( ⁇ )
• the injection layer 50 has a doping level greater than or equal to 1 x10 18 cm “3 and a thickness in a range of and including 1 to 5 ⁇
• the field stop layer 52 has a doping level in a range of and including 1 x10 16 to 5x10 17 cm “3 and a thickness in a range of and including 1 to 5 ⁇
• the drift layer 54 has a doping level less than 2x10 14 cm “3 and a thickness that is greater than or equal to 80 ⁇
• the base layer 56 has a doping level in a range of and including 1 x10 16 to 1 x10 18 cm “3 and a thickness in a range of and including 0.5 to 5 ⁇
• the anode mesa 62 has a doping level that is greater than 1 x10 19 cm "3 and
• the substrate 48 has doping level in a range of and including 1 x10 18 to 1 x10 19 cm “3 and a thickness in a range of and including about 100 to 350 ⁇
• the injection layer 50 has a doping level of 5x10 18 cm “3 and a thickness of 1 ⁇
• the field stop layer 52 has a doping level of 1 x10 16 cm “3 and a thickness of 4 ⁇
• the drift layer 54 has a doping level less than 2x10 14 cm “3 and a thickness of 90 ⁇
• the base layer 56 has a doping level of 1 x10 17 cm "3 and a thickness of 2.5 ⁇
• the anode mesa 62 has a doping level that is greater than 2x10 19 cm "3 and a thickness in a range of and including 0.5 to 5 ⁇ .
• the gate regions 58 and 60 are N+ regions that, in one embodiment, have a doping level greater than 1 x10 18 cm "3 .
• the contacts 64, 66, 68, and 70 are formed of any suitable contact material (e.g., metal, metal alloy, etc.).
• An edge of the thyristor 44 is terminated by the negative bevel edge termination 46.
• a width of the negative bevel edge termination 46 is 600 ⁇ .
• a slope angle (a) of the negative bevel edge termination 46 is less than or equal to 15 degrees.
• the negative bevel edge termination 46 is implemented as a multi-step negative bevel edge termination that approximates a smooth slope.
• a negative bevel having a smooth slope is not obtainable in SiC.
• wet etching can be used to form a negative bevel edge termination having a smooth slope for Silicon devices, but wet etching is not suitable for SiC and therefore cannot be used to form a negative bevel edge termination having a smooth slope for SiC devices. Therefore, as discussed herein, the negative bevel edge termination 46 is implemented as a multi-step negative bevel edge termination that approximates a smooth slope.
• the multi-step negative bevel edge termination 46 includes a number of steps that approximate a smooth slope at the desired slope angle (a). In one embodiment, the multi-step negative bevel edge termination 46 includes at least 10 steps that approximate a smooth slope at the desired slope angle (a). In another embodiment, the multi-step negative bevel edge termination 46 includes at least 15 steps that approximate a smooth slope at the desired slope angle (a).
• a blocking voltage of the thyristor 44 approaches a blocking voltage of an ideal parallel-plane device. In this particular embodiment, the blocking voltage is greater than or equal to 12 kilovolts (kV).
• the blocking voltage of a device is a voltage at which the device conducts a 1 microamp ( ⁇ ) current.
• the blocking voltage is a voltage that, when applied from the anode contact 64 to the cathode contact 66, will cause a 1 ⁇ current to flow through the thyristor 44 when no voltage is applied to the gate contacts 68 and 70.
• FIG 3 illustrates the negative bevel edge termination 46 of Figure 2 in more detail according to one embodiment of the present disclosure.
• the negative bevel edge termination 46 is more specifically a multi-step negative bevel edge termination 46.
• the multi-step negative bevel edge termination 46 includes 15 steps that approximate the desired slope angle (a).
• the multi-step negative bevel edge termination 46 relieves field crowding, thereby improving the blocking voltage.
• the blocking voltage is improved to at least 12 kV.
• the multi-step negative bevel edge termination 46 of this embodiment is formed by etching the base layer 56 using a suitable number of masks.
• the number of masks is equal to the number of steps (e.g., 15 masks to form 15 steps).
• the number of masks may be optimized to reduce the number of etching steps such that the total number of masks is less than the number of steps in the multi-step negative bevel edge termination 46 (e.g., 4-15 masks for 15 steps).
• FIG 4 graphically compares the electric field distribution along the multi-step negative bevel edge termination 46 of Figure 3 with that of a 15 well Junction Termination Extension (JTE) edge termination at 12 kV according to one embodiment of the present disclosure.
• the multi-step negative bevel edge termination 46 has effectively reduced the peak electric field found at the mesa trench corner (e.g., the corner 42 of the thyristor 10 of Figure 1 ) to less than 1 .4 Mega-Volts per centimeter (MV/cm). In other words, the peak electric field found at the junction edge is reduced by more than 0.2 MV/cm.
• Figure 5 graphically compares the blocking voltage of the thyristor 44 including the multi-step negative bevel edge termination 46 of Figure 3 with that of a thyristor (e.g., the thyristor 10 of Figure 1 ) having a 15 well JTE edge termination according to one embodiment of the present disclosure.
• a thyristor e.g., the thyristor 10 of Figure 1
• the thyristor 44 has a blocking voltage in a range of 1 1 .5 to 12 kV. This is a 3.5 to 4 kV improvement over the 9 kV blocking voltage resulting from the 15 well JTE edge termination.
• Figure 6 illustrates the thyristor 44 including the negative bevel edge termination 46 according to another embodiment of the present disclosure.
• the negative bevel edge termination 46 is formed by counter-doping the base layer 56 in an edge region 72 adjacent to the gate region 60 opposite the anode mesa 62 with a P-type ion that compensates the n-type conductivity of the base layer 56 in the edge region 72 to provide a neutral, or intrinsic, region 76 having a desired negative bevel characteristic.
• the P-type ion may be, for example, Aluminum (Al), Boron (B), or the like.
• the negative bevel edge termination 46 is thereby formed at an interface of the neutral region 76 and a remainder of the base layer 56. More specifically, in one embodiment, ions are implanted to varying depths that increase step-wise starting at the end of the edge region 72 adjacent to the gate region 60 and proceeding outwardly to provide the desired number of steps and slope (a) for the negative bevel edge termination 46.
• Figure 7 illustrates another process by which the negative bevel edge termination 46 can be formed.
• a sacrificial layer 78 is formed on the surface of the base layer 56 over an area where the negative bevel edge termination 46 is to be formed.
• the sacrificial layer 78 may be, for example, Si0 2 , photo-resist, or similar material.
• the sacrificial layer 78 is etched or otherwise processed to provide a negative bevel 80 having a desired multi- step characteristic (i.e., number of steps, slope angle, width, etc.) for the negative bevel edge termination 46.
• An etching process is then performed to remove the sacrificial layer 78. More specifically, an etching process is performed to etch to a desired depth (d), which in this example is equal to the thickness of the sacrificial layer 78 and also equal to the thickness of the base layer 56.
• d desired depth
• the present disclosure is not limited thereto.
• the negative bevel 80 is effectively transferred to the base layer 56 to thereby provide the multi-step negative bevel edge termination 46.
• Figures 8 through 17 illustrate additional, non-limiting, examples of other types of SiC devices that can utilize the negative bevel edge termination described above with respect to the thyristor 44. More specifically, Figure 8 illustrates a SiC Bipolar Junction Transistor (BJT) 82 including a negative bevel edge termination 84 according to one embodiment of the present disclosure.
• BJT SiC Bipolar Junction Transistor
• the BJT 82 includes an N+ substrate 86, an N-type drift layer 88 on a surface of the substrate 86, a P-type base layer 90 on a surface of the drift layer 88 opposite the substrate 86, a P+ base region 92 formed in the base layer 90, an N++ emitter mesa 94 on the surface of the base layer 90 opposite the drift layer 88, a base contact 96 on the base region 92, an emitter contact 98 on the emitter mesa 94, and a collector contact 100 on a surface of the substrate 86 opposite the drift layer 88.
• the negative bevel edge termination 84 is a multi-step negative bevel edge termination like that of Figure 3. As a result of the negative bevel edge termination 84, a blocking voltage of the BJT 82 approaches the blocking voltage of the ideal parallel-plane device.
• FIG. 9 illustrates the BJT 82 including the negative bevel edge termination 84 according to another embodiment of the present disclosure.
• the negative bevel edge termination 84 is formed by counter- doping the P-type base layer 90 in an edge region 102 adjacent to the P+ base region 92 opposite the emitter mesa 94 with an N-type ion that compensates the P-type conductivity of the base layer 90 in the edge region 102 to provide a neutral, or intrinsic, region 106 having a desired negative bevel characteristic.
• the N-type ion may be, for example, Nitrogen (N), Phosphorous (P), or the like.
• the negative bevel edge termination 84 is thereby formed at an interface of the neutral region 106 and a remainder of the base layer 90.
• ions are implanted to varying depths that increase step-wise starting at the end of the edge region 102 adjacent to the P+ base region 92 and proceeding outwardly to provide the desired number of steps and slope (a) for the negative bevel edge termination 84.
• FIG. 10 illustrates a P-type SiC Insulated Gate Bipolar Transistor (IGBT) 108 including a negative bevel edge termination 1 10 according to one embodiment of the present disclosure.
• the IGBT 108 includes a P+ substrate or epilayer 1 12, an N-type drift layer 1 14 on a surface of the substrate 1 12, a base layer 1 1 6 on a surface of the drift layer 1 14 opposite the substrate 1 12, P+ regions 1 18 and 120 on the surface of the base layer 1 1 6 opposite the drift layer 1 14, and emitter regions 122 and 124.
• a gate contact 126 is formed in a trench as shown and is insulated by a gate insulator 128.
• the negative bevel edge termination 1 10 is a multi-step negative bevel edge termination like that of Figure 3. As a result of the negative bevel edge termination 1 10, a blocking voltage of the IGBT 108 approaches the blocking voltage of the ideal parallel-plane device.
• Figure 1 1 illustrates the IGBT 108 including the negative bevel edge termination 1 10 according to another embodiment of the present disclosure.
• the negative bevel edge termination 1 10 is formed by counter- doping the P-type base layer 1 1 6 in an edge region 136 adjacent to the P+ region 1 18 and the N+ emitter region 122 opposite the gate contact 126 with an N-type ion that compensates the P-type conductivity of the base layer 1 1 6 in the edge region 136 to provide a neutral, or intrinsic, region 140 having a desired negative bevel characteristic.
• the N-type ion may be, for example, Nitrogen (N), Phosphorous (P), or the like.
• the negative bevel edge termination 1 10 is thereby formed at an interface of the neutral region 140 and a remainder of the base layer 1 1 6. More specifically, in one embodiment, ions are implanted to varying depths that increase step-wise starting at the end of the edge region 136 adjacent to the P+ region 1 18 and proceeding outwardly to provide the desired number of steps and slope (a) for the negative bevel edge termination 1 10.
• FIG. 12 illustrates an n-type SiC IGBT 142 including a negative bevel edge termination 144 according to one embodiment of the present disclosure.
• the IGBT 142 includes a substrate 146, a drift layer 148 on a surface of the substrate 146, a base layer 150 on a surface of the drift layer 148 opposite the substrate 146, N+ regions 152 and 154 on the surface of the base layer 150 opposite the drift layer 148, and emitter regions 156 and 158.
• a gate contact 1 60 is formed in a trench as shown and is insulated by a gate insulator 1 62.
• Emitter contacts 1 64 and 1 66 are on the emitter regions 156 and 158, respectively, and a collector contact 1 68 is on a surface of the substrate 146 opposite the drift layer 148.
• the negative bevel edge termination 144 is a multi-step negative bevel edge termination like that of Figure 3. As a result of the negative bevel edge termination 144, a blocking voltage of the IGBT 142 approaches the blocking voltage of the ideal parallel-plane device.
• Figure 13 illustrates the IGBT 142 including the negative bevel edge termination 144 according to another embodiment of the present disclosure.
• the negative bevel edge termination 144 is formed by counter- doping the N-type base layer 150 in an edge region 170 adjacent to the N+ region 152 and the P+ emitter region 156 opposite the gate contact 1 60 with a P- type ion that compensates the N-type conductivity of the base layer 150 in the edge region 170 to provide a neutral, or intrinsic, region 174 having a desired negative bevel characteristic.
• the P-type ion may be, for example, Aluminum (Al), Boron (B), or the like.
• FIG. 14 illustrates a SiC PIN diode 176 including a negative bevel edge termination 178 according to one embodiment of the present disclosure.
• the PIN diode 176 includes an N+ substrate 180, a N- drift layer 182, a P-type layer 184, and P++ layer 186 arranged as shown.
• the N- drift layer 182 may also be referred to herein as an intrinsic layer between the N+ substrate 180 and the P-type layer 184 forming the PIN diode 176.
• the P++ layer 186 may also be referred to herein as an anode mesa.
• An anode contact 188 is on the surface of the P++ layer 186 opposite the P-type layer 184.
• a cathode contact 190 is on a surface of the N+ substrate 180 opposite the N- drift layer 182.
• the negative bevel edge termination 178 is a multi-step negative bevel edge termination like that of Figure 3. As a result of the negative bevel edge termination 178, a blocking voltage, which is more
• Figure 15 illustrates the PIN diode 176 including the negative bevel edge termination 178 according to another embodiment of the present
• the negative bevel edge termination 178 is formed by counter-doping the P-type layer 184 in an edge region 192 adjacent to the P++ layer 186 with an N-type ion that compensates the P-type conductivity of the P-type layer 184 in the edge region 192 to provide a neutral, or intrinsic, region 196 having a desired negative bevel characteristic.
• the N-type ion may be, for example, Nitrogen (N), Phosphorous (P), or the like.
• the negative bevel edge termination 178 is thereby formed at an interface of the neutral region 196 and a remainder of the P-type layer 184.
• ions are implanted to varying depths that increase step-wise starting at the end of the edge region 192 adjacent to the P++ layer 186 and proceeding outwardly to provide the desired number of steps and slope (a) for the negative bevel edge termination 178.
• FIG. 1 6 illustrates a SiC U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET) 198 including a negative bevel edge termination 200 according to one embodiment of the present disclosure.
• the UMOSFET 198 includes an N+ substrate 202, an N-type drift layer 204 on a surface of the substrate 202, a P-type base layer 206 on a surface of the drift layer 204 opposite the substrate 202, P+ regions 208 and 210 on the surface of the base layer 206 opposite the drift layer 204, and N+ source regions 212 and 214.
• a gate contact 21 6 is formed in a trench as shown and is insulated by a gate insulator 218.
• Source contacts 220 and 222 are on the source regions 212 and 214, respectively, and a drain contact 224 is on a surface of the substrate 202 opposite the drift layer 204.
• the negative bevel edge termination 200 is a multi-step negative bevel edge termination like that of Figure 3. As a result of the negative bevel edge termination 200, a blocking voltage of the UMOSFET 198 approaches the blocking voltage of the ideal parallel-plane device.
• FIG 17 illustrates the UMOSFET 198 including the negative bevel edge termination 200 according to another embodiment of the present disclosure.
• the negative bevel edge termination 200 is formed by counter-doping the P-type base layer 206 in an edge region 226 adjacent to the P+ region 208 and the N+ source region 212 opposite the gate contact 21 6 with an N-type ion that compensates the P-type conductivity of the base layer 206 in the edge region 226 to provide a neutral, or intrinsic, region 230 having a desired negative bevel characteristic.
• the N-type ion may be, for example, Nitrogen (N), Phosphorous (P), or the like.
• the negative bevel edge termination 200 is thereby formed at an interface of the neutral region 230 and a remainder of the base layer 206. More specifically, in one embodiment, ions are implanted to varying depths that increase step-wise starting at the end of the edge region 226 adjacent to the P+ region 208 and the N+ source region 212 and proceeding outwardly to provide the desired number of steps and slope (a) for the negative bevel edge termination 200.
• the number of steps in the multi-step negative bevel edge termination 46, 84, 1 10, 144, 178, and 200 of the various devices described herein may vary depending on the particular implementation.
• Some exemplary embodiments of the multi-step negative bevel edge termination 46, 84, 1 10, 144, 178, and 200 include at least 5 steps, at least 7 steps, at least 10 steps, at least 12 steps, at least 15 steps, at least 17 steps, at least 20 steps, a number of steps in a range of and including 5 to 20 steps, a number of steps in a range of and including 10 to 20 steps, a number of steps in a range of and including 15 to 20 steps, and a number of steps in a range of and including 10 to 15 steps.
• the blocking voltages of the various devices may also vary depending on the particular implementation.
• Some exemplary embodiments include a blocking voltage of at least 10 kV, a blocking voltage of at least 12 kV, a blocking voltage of at least 15 kV, a blocking voltage of at least 17 kV, a blocking voltage of at least 20 kV, a blocking voltage of at least 22 kV, a blocking voltage of at least 25 kV, a blocking voltage in a range of and including 10 kV to 25 kV, a blocking voltage in a range of and including 12 kV to 25 kV, a blocking voltage in a range of and including 15 kV to 25 kV, a blocking voltage in a range of and including 12 kV to 20 kV, and a blocking voltage in a range of and including 12 kV to 15 kV.
• the forward conduction characteristic of the high blocking voltage (e.g., > 10 kV) thyristor 44, and thus an on-resistance of the thyristor 44 is a function of the carrier lifetime of the drift layer 54.
• the drift layer 54 is relatively thick (e.g., as much at 1 60 microns or more for a blocking voltage up to 20 kV) and highly resistive.
• the carrier lifetime of the drift layer 54 is normally relatively low, which results in a less than optimal on-resistance for the thyristor 44.
• the following discussion describes a number of carrier lifetime enhancement techniques that can be used to provide a low on-resistance while maintaining the high blocking voltage.
• the thyristor 44 can be treated as a P-i-N rectifier.
• the electron and hole concentrations within the N-base and P-base regions of the conventional thyristor (PNPN) take a catenary distribution in accordance with the analysis for the P-i-N rectifier, which is shown in Figure 19.
• Equation (3) Rearranging Equation (1 ) and then substituting it into Equation (2) gives the specific resistance of the drift la er 54 in Equation (3):
• V JM J T - R diSP (V) . (4)
• Equations (3) and (4) It is clearly illustrated in Equations (3) and (4) that both specific resistance and voltage drop of the drift layer 54 reduce with increasing the carrier lifetime, which is also evidenced in Figure 20 where higher lifetime results in higher carrier density in the drift region.
• the conductivity modulation phenomenon at high injection levels enables maintaining a low voltage drop across the drift layer 54, which is beneficial for getting a low on-state voltage drop in bipolar diodes and transistors.
• Figures 21 A through 21 D illustrate a process for fabricating the thyristor 44 of Figure 2 using a number of carrier lifetime enhancement techniques that result in the thyristor 44 having a low on-resistance according to one embodiment of the present disclosure.
• the process begins with an epitaxial structure including the substrate 48, the injection layer 50, the field stop layer 52, the drift layer 54, the base layer 56, and a layer 62' to be etched to form the anode mesa 62.
• the layer 62' is etched to form the anode mesa 62.
• the oxidation process is preferably a dry-oxidation process where the structure of Figure 21 B is heated at a temperature in a range of and including 1200°C to 1450°C for a duration of 1 hour to 15 hours.
• the dry-oxidation process is performed by heating the structure of Figure 21 B at a temperature of 1300°C for 5 hours.
• the oxide on the surface of the structure resulting from the dry-oxidation process is then removed. This dry- oxidation process increases the carrier lifetime, and in particular the minority carrier lifetime, of the drift layer 54.
• the negative bevel edge termination 46 is etched or otherwise formed, and the dopants (e.g., N+ dopants) are implanted into the base layer 56 to form the gate regions 58 and 60 as illustrated in Figure 21 C.
• the implanted dopants are activated by then annealing.
• This annealing may be performed, for example, at a temperature of 1 650°C for 30 minutes. Note, however, that the annealing temperature and duration may be varied. In particular, the annealing may be at a temperature in a range of and including 1500°C to 2000°C for a duration of 1 minute to 60 minutes.
• the annealing is performed at a temperature in the range of and including 1 600°C to 1800°C for a duration of 10 to 30 minutes.
• a sacrificial oxidation process followed by an oxide removal process are then performed to remove damage at the surface of the structure in Figure 21 C resulting from the implantation process. More
• the structure of Figure 21 C is heated at a temperature of 1200°C for 2 hours, rinsed, heated at a temperature of 950°C for 2 hours, and then rinsed again.
• the temperature and duration of the heating for this oxidation process may vary.
• the sacrificial oxidation is performed at a temperature of 1 150°C to 1450°C for a duration of 1 hour to 15 hours.
• the sacrificial oxidation process is performed at a temperature in the range of and including 1200°C to 1300°C for a duration of 1 hour to 5 hours.
• the carrier lifetime of the drift layer 54 is further enhanced.
• the anode, cathode, and gate contacts 64, 66, 68, and 70 are formed, as illustrated in Figure 21 D.
• the thyristor 44 has both a high blocking voltage and a low on-resistance.
• the thyristor 44 has a blocking voltage of at least 10 kV and a differential on-resistance of less than 10 mQ-cm 2 , more preferably less than 7 mQ-cm 2 , and even more preferably of less than 5 mQ-cm 2 .
• the thyristor 44 has a blocking voltage in a range of and including 10 kV to 15 kV and a differential on-resistance of less than 10 mQ-cm 2 , more preferably less than 7 mQ-cm 2 , and even more preferably of less than 5 mQ-cm 2 .
• the thyristor 44 has a blocking voltage of at least 10 kV or in the range of 10 kV to 15 kV and a differential on-resistance in the range of 1 to 10 mQ-cm 2 , in the range of 3 to 10 mQ-cm 2 , in the range of 1 to 7 mQ-cm 2 , in the range of 3 to 7 mQ-cm 2 , in the range of 1 to 5 mQ-cm 2 , or in the range of 3 to 5 mQ-cm 2 .
• the thyristor 44 has a blocking voltage of at least 15 kV and a differential on-resistance of less than 15 mQ-cm 2 , more preferably less than 10 mQ-cm 2 , and even more preferably of less than 7 mQ-cm 2 . In another embodiment, the thyristor 44 has a blocking voltage in a range of and including 15 kV to 20 kV and a differential on-resistance of less than 15 mQ-cm 2 , more preferably less than 10 mQ-cm 2 , and even more preferably of less than 7 mQ-cm 2 .
• the thyristor 44 has a blocking voltage of at least 15 kV or in the range of 15 kV to 20 kV and a differential on- resistance in the range of 1 to 15 mQ-cm 2 , in the range of 3 to 15 mQ-cm 2 , in the range of 1 to 10 mQ-cm 2 , in the range of 3 to 10 mQ-cm 2 , in the range of 1 to 7 mQ-cm 2 , or in the range of 3 to 7 mQ-cm 2 .
• the thyristor 44 has a blocking voltage of at least 20 kV and a differential on-resistance of less than 20 mQ-cm 2 , more preferably less than 15 mQ-cm 2 , and even more preferably of less than 10 mQ-cm 2 . In another embodiment, the thyristor 44 has a blocking voltage in a range of and including 20 kV to 25 kV and a differential on-resistance of less than 20 mQ-cm 2 , more preferably less than 15 mQ-cm 2 , and even more preferably of less than 10 mQ-cm 2 .
• the thyristor 44 has a blocking voltage of at least 20 kV or in the range of 20 kV to 25 kV and a differential on-resistance in the range of 1 to 20 mQ-cm 2 , in the range of 3 to 20 mQ-cm 2 , in the range of 7 to 20 mQ-cm 2 , in the range of 1 to 15 mQ-cm 2 , in the range of 3 to 15 mQ-cm 2 , in the range of 7 to 20 mQ-cm 2 , in the range of 1 to 10 mQ-cm 2 , in the range of 3 to 10 mQ-cm 2 , or in the range of 7 to 10 mQ-cm 2 .
• the drift layer 54 of the thyristor 44 can be thicker, and thus provide a higher blocking voltage, while maintaining a suitable on-resistance.
• the drift layer 54 may have a thickness greater than 80 ⁇ , a thickness greater than 100 ⁇ , a thickness greater than 120 ⁇ , a thickness greater than 140 ⁇ , a thickness greater than 1 60 ⁇ , a thickness in the range of and including 80 ⁇ to 200 ⁇ , a thickness in the range of and including 80 ⁇ to 1 60 ⁇ , a thickness in the range of and including 100 ⁇ to 200 ⁇ , a thickness in the range of and including 100 ⁇ to 1 60 ⁇ , a thickness in the range of and including 140 ⁇ to 200 ⁇ , or a thickness in the range of and including 140 ⁇ to 1 60 ⁇ , or a thickness in the range of and including 1 60 ⁇ to 200 ⁇ .
• other thicknesses may be used depending on the desired blocking voltage and the particular
• Figure 22A illustrates an average carrier lifetime measure, a median carrier lifetime measurement, a minimum carrier lifetime measurement, a maximum carrier lifetime measure, and a deviation of the carrier lifetime measures for a number of structures such as that of Figure 21 A.
• the drift layer 54 is a 90 ⁇ thick p-type SiC material layer and has a doping level of less than 2x10 14 cm "3 .
• Figure 22B illustrates similar carrier lifetime measurements after etching the anode mesa 62 and performing a dry-oxidation process at a temperature of 1300°C for 5 hours. As shown, after performing the dry-oxidation process, the carrier lifetime is significantly increased.
• Figure 22C illustrates carrier lifetime
• the sacrificial oxidation process included heating at a temperature of 1200°C for 2 hours, rinsing, heating at a temperature of 950°C for 2 hours, and then rinsing again.
• the implant anneal followed by the sacrificial oxidation process further increased the carrier lifetime for the drift layer 54.
• Figure 23 graphically illustrates the on-resistance of one example of the thyristor 44 having a blocking voltage of at least 10 kV that was formed using the carrier lifetime enhancement techniques described above.
• the differential on-resistance is less than 5 mQ-cm 2 at a current density of 100 A/cm 2 (i.e., high-level injection condition) due to improved carrier lifetime.
• the differential on- resistance is about 4 mQ-cm 2 .
• the carrier lifetime enhancement techniques above have been described with respect to the thyristor 44, the carrier lifetime enhancement techniques may be utilized for any semiconductor device, and in particular any type of SiC semiconductor device, that is bipolar (i.e., uses both electrons and holes for conduction).
• the carrier lifetime enhancement techniques may be utilized when fabricating the BJT 82 of Figures 8 and 9, the IGBTs 108 and 142 of Figures 10, 1 1 , 12, and 13, and the PIN diode 176 of Figures 14 and 15 to provide similar on-resistance improvements.
• the oxidation process described above as being performed after etching the anode mesa 62 of the thyristor 44 may be performed after etching the emitter mesa 94.
• the implant anneal and sacrificial oxidation process may be performed after etching or otherwise forming the negative bevel edge termination 84 and implanting the base region 92. In this manner, the carrier lifetime of the drift layer 88 is improved, which in turn decreases the on-resistance of the BJT 82.
• the oxidation process described above as being performed after etching the anode mesa 62 of the thyristor 44 may be performed after etching the gate trench.
• the implant anneal and sacrificial oxidation process may be performed after etching or otherwise forming the negative bevel edge termination 1 10 and implanting the P+ regions 1 18 and 120 and the emitter regions 122 and 124.
• the carrier lifetime of the drift layer 1 14 is improved, which in turn decreases the on-resistance of the IGBT 108.
• the carrier lifetime techniques can be used for the IGBT 142 of Figures 12 and 13.
• the oxidation process described above as being performed after etching the anode mesa 62 of the thyristor 44 may be performed after etching the P-type layer 184 and the P++ layer 186.
• the implant anneal and sacrificial oxidation process may be performed after implanting the P-type layer 184 to form the negative bevel edge termination 178 in the embodiment of Figure 15. In this manner, the carrier lifetime of the N- drift layer 182 is improved, which in turn decreases the on-resistance of the PIN diode 176.

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