WO2013108335A1 - Procédé de production d'une tranche épitaxiale - Google Patents

Procédé de production d'une tranche épitaxiale Download PDF

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Publication number
WO2013108335A1
WO2013108335A1 PCT/JP2012/008043 JP2012008043W WO2013108335A1 WO 2013108335 A1 WO2013108335 A1 WO 2013108335A1 JP 2012008043 W JP2012008043 W JP 2012008043W WO 2013108335 A1 WO2013108335 A1 WO 2013108335A1
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WO
WIPO (PCT)
Prior art keywords
oxide film
silicon substrate
epitaxial
back surface
epitaxial wafer
Prior art date
Application number
PCT/JP2012/008043
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English (en)
Japanese (ja)
Inventor
祐司 新井
雅典 黛
晃一 山野
Original Assignee
信越半導体株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 信越半導体株式会社 filed Critical 信越半導体株式会社
Priority to DE112012005302.8T priority Critical patent/DE112012005302T5/de
Publication of WO2013108335A1 publication Critical patent/WO2013108335A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile

Definitions

  • the present invention relates to a method for manufacturing a silicon epitaxial wafer.
  • an epitaxial wafer is a silicon substrate that forms an epitaxial layer with a high concentration of impurities (dopant) and is configured to have either a p-type or n-type conductivity type.
  • a resistive substrate is used.
  • the conductivity type is p-type
  • boron (B) or the like is added as a dopant.
  • phosphorus (P), antimony (Sb), arsenic (As), or the like is used as the dopant. To be added.
  • an epitaxial wafer manufacturing method including a step of forming an oxide film for preventing auto-doping on the back surface of the silicon substrate is used prior to the growth of the epitaxial layer. Yes. Since the formed back surface oxide film can prevent the dopant from jumping out, generation of autodope can be effectively suppressed. In addition, since the epitaxial layer is grown on the surface side of the silicon substrate, the above-described impurity jumping is suppressed.
  • an epitaxial wafer that suppresses the growth of the polysilicon product described above, for example, as disclosed in Patent Document 1 and Patent Document 2, a part of an oxide film formed on the back side of the silicon substrate.
  • a method of growing an epitaxial layer after removing According to these manufacturing methods, the peripheral portion of the silicon substrate, and further, the back surface oxide film is removed in a wide range within the range where the influence of auto-doping can be tolerated, no polysilicon product is generated, and the LPD density is suppressed.
  • An epitaxial wafer can be obtained.
  • Patent Document 1 and Patent Document 2 have a certain effect on the suppression of the polysilicon product, but it is difficult to control the removal amount of the backside oxide film in consideration of the influence of auto-doping.
  • the removal amount of the back surface oxide film is excessively large, autodoping cannot be sufficiently suppressed, and there is a problem that the uniformity of resistivity within the wafer surface is deteriorated.
  • the present invention has been made in view of the above problems, and by optimizing the removal amount of the back surface oxide film, the generation of auto-dope and polysilicon products is surely suppressed, and the wafer surface of resistivity is achieved. It is an object of the present invention to provide a method for manufacturing an epitaxial wafer having a high internal uniformity and suppressing the generation of nodules.
  • an oxide film forming step of forming an oxide film on the back side of a silicon substrate containing a dopant an oxide film removing step of partially removing the formed oxide film, and thereafter
  • a method for producing an epitaxial wafer having an epitaxial growth step of vapor-phase growing an epitaxial layer on a silicon substrate In the oxide film removing step, at least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer periphery of the back surface of the silicon substrate is moved inward from the outermost periphery of the back surface of the silicon substrate to 0 ⁇ m or more and 30 ⁇ m.
  • the present invention provides a method for producing an epitaxial wafer, which is performed by removing with a width of less than.
  • an epitaxial wafer having an oxide film formed on the back side of a silicon substrate containing a dopant and an epitaxial layer grown on the silicon substrate by vapor phase, wherein the oxide film is At least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer peripheral portion of the back surface of the silicon substrate is removed inward from the outermost peripheral portion of the back surface of the silicon substrate with a width of 0 ⁇ m or more and less than 30 ⁇ m.
  • An epitaxial wafer is provided that is characterized by
  • Such an epitaxial wafer according to the present invention reliably suppresses auto-dope and polysilicon product generation, has high uniformity of resistivity within the wafer surface, and suppresses nodule generation.
  • an epitaxial wafer by suppressing the generation of a polysilicon product while suppressing auto-doping, and the uniformity of resistivity in the wafer surface is high. It becomes possible to manufacture an epitaxial wafer in which the generation of nodules is suppressed.
  • the process flowchart which showed an example of the manufacturing method of the epitaxial wafer of this invention is shown. It is explanatory drawing explaining the range of the oxide film removed by the oxide film removal process in this invention. The relationship between the resistivity in-plane distribution of an epitaxial layer and a back surface oxide film removal width in Examples and Comparative Examples is shown. It is explanatory drawing explaining the oxide film removal method using the sheet style back surface oxide film removal apparatus in this invention.
  • the present inventors have formed an oxide film forming step for forming an oxide film on the back side of a silicon substrate containing a dopant, an oxide film removing step for removing a part of the formed oxide film, and then on the silicon substrate.
  • the oxide film removing step at least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer peripheral portion of the back surface of the silicon substrate is moved inward from the outermost peripheral portion of the back surface of the silicon substrate to 0 ⁇ m or more and 30 ⁇ m.
  • the present invention provides a method for producing an epitaxial wafer, which is performed by removing with a width of less than. The present invention will be described in detail below.
  • FIG. 1 is a process flow diagram showing an example of the epitaxial wafer manufacturing method of the present invention.
  • a dopant for example, boron (B) when the conductivity type is p-type, phosphorus (P), antimony when the conductivity type is n-type.
  • Such a low-resistivity silicon substrate is liable to cause autodoping, and therefore is preferable because it has a large improvement effect when used in the present invention.
  • an oxide film forming step for forming an oxide film on the back side of the silicon substrate containing the dopant is performed (FIG. 1B).
  • the oxide film is preferably formed by a CVD method.
  • a CVD silicon oxide film can be easily formed by depositing and forming a silicon oxide film on the back side of the silicon substrate by the CVD method.
  • an oxide film removing step for removing a part of the formed oxide film is performed (FIG. 1C).
  • the present invention removes at least the oxide film 3 of the chamfered portion 2 of the silicon substrate 1 and removes the oxide film 3 on the outer peripheral portion of the back surface of the silicon substrate 1 as shown in FIG.
  • the silicon substrate is removed by removing it from the outermost peripheral portion 5 of the back surface 4 with a width of 0 ⁇ m or more and less than 30 ⁇ m (back surface oxide film removal width).
  • nodule may be generated, but the oxide film extends to the end of the wafer chamfered portion 2 (that is, the outermost peripheral portion 5 of the silicon substrate back surface 4). It was confirmed that no nodules were generated when 3 was removed.
  • the removal of the oxide film 3 on the outer peripheral portion of the back surface of the silicon substrate 1 is performed with a width of 0 ⁇ m or more and less than 30 ⁇ m (back surface oxide film removing width) inward from the outermost peripheral portion 5 of the silicon substrate back surface 4.
  • production is suppressed and it is possible to fully suppress auto dope.
  • Such an oxide film removing method is not particularly limited.
  • the silicon substrate 1 is set in a sheet-type back surface oxide film removing apparatus 7 as shown in FIG. 4, and the oxide film is etched with an aqueous solution containing HF or the like. It can be done by doing.
  • the oxide film 3 on the chamfered portion 2 of the silicon substrate 1 is removed, and at the same time, the back surface oxide film removal width is increased.
  • the width can be set to 0 ⁇ m or more and less than 30 ⁇ m. Then, it is preferable to perform rinsing and drying continuously by using this sheet style back surface oxide film removing apparatus 7.
  • an epitaxial growth process is performed in which an epitaxial layer is vapor-phase grown on the silicon substrate (FIG. 1D).
  • the epitaxial growth step can be performed by a conventionally known method.
  • An epitaxial growth apparatus is used to deposit an epitaxial layer on the surface 6 (surface on which the epitaxial layer is grown) of the silicon substrate with a predetermined thickness ( For example, it can be grown to 10 ⁇ m to 100 ⁇ m).
  • the epitaxial growth apparatus to be used is not particularly limited, and generally, a vertical type, a cylinder type and a single wafer type are widely used, and any apparatus can be used in the present invention.
  • the epitaxial wafer of the present invention is manufactured by the above-described epitaxial wafer manufacturing method of the present invention, and is vapor-phase grown on the silicon substrate containing an oxide film formed on the back side of the silicon substrate containing the dopant.
  • An epitaxial layer At least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer periphery of the back surface of the silicon substrate has a width of 0 ⁇ m or more and less than 30 ⁇ m inward from the outermost periphery of the back surface of the silicon substrate. It has been removed.
  • An oxide film for preventing auto-doping is formed on the back side of a silicon substrate having a resistivity of 1 m ⁇ ⁇ cm containing phosphorus as an impurity (dopant) by CVD, and then suppressing the generation of polysilicon products (nodules) Therefore, a silicon substrate was prepared in which the oxide film formed on the chamfered portion and the oxide film on the outer peripheral portion of the back surface were removed from the outermost peripheral portion on the back surface of the silicon substrate by the width of 0 ⁇ m and 28 ⁇ m.
  • An epitaxial layer having an epi resistivity of 1.5 ⁇ ⁇ cm and an epi film thickness of 10 ⁇ m is grown on the silicon substrate using a growth temperature of 1130 ° C., a dopant gas of PH 3 , and a film forming gas of trichlorosilane (TCS).
  • An epitaxial wafer to be a sample was manufactured by performing epitaxial growth (CVD method). The epi-resistivity measurement of the epitaxial wafer manufactured at this time was implemented.
  • FIG. 3 shows the relationship between the epitaxial resistivity in-plane distribution (%) and the removal width ( ⁇ m) of the back oxide film.
  • An oxide film for preventing auto-doping is formed on the back side of a silicon substrate having a resistivity of 1 m ⁇ ⁇ cm containing phosphorus as an impurity (dopant) by CVD, and then suppressing the generation of polysilicon products (nodules) Therefore, a silicon substrate was prepared in which the oxide film formed on the chamfered portion and the oxide film on the outer peripheral portion of the back surface were removed from the outermost peripheral portion on the back surface of the silicon substrate by 40 to 300 ⁇ m.
  • An epitaxial layer having an epi resistivity of 1.5 ⁇ ⁇ cm and an epi film thickness of 10 ⁇ m is grown on the silicon substrate using a growth temperature of 1130 ° C., a dopant gas of PH 3 , and a film forming gas of trichlorosilane (TCS).
  • An epitaxial wafer as a sample was manufactured by performing epitaxial growth (CVD method). The epi-resistivity measurement of the epitaxial wafer manufactured at this time was implemented.
  • FIG. 3 shows the relationship between the epitaxial resistivity in-plane distribution (%) and the removal width ( ⁇ m) of the back oxide film.
  • the present invention is not limited to the above embodiment.
  • the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
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Abstract

La présente invention concerne un procédé de production d'une tranche épitaxiale, comportant une étape de formation de film d'oxyde consistant à former un film d'oxyde du côté face inférieure d'un substrat en silicium comprenant un dopant, une étape d'élimination de film d'oxyde consistant à éliminer une partie du film d'oxyde formé et une étape subséquente de croissance épitaxiale consistant à faire croître une couche épitaxiale sur le substrat en silicium par épitaxie en phase vapeur. Le procédé de production d'une tranche épitaxiale est caractérisé en ce que l'étape d'élimination de film d'oxyde est réalisée en éliminant au moins le film d'oxyde sur une partie chanfreinée du substrat en silicium et en éliminant le film d'oxyde sur la partie circonférentielle extérieure de la face inférieure du substrat en silicium sur une largeur d'au moins 0 μm mais inférieure à 30 μm en-deçà de la partie circonférentielle extérieure extrême de la face inférieure du substrat en silicium. Ainsi, le procédé décrit de production d'une tranche épitaxiale est caractérisé en ce qu'en optimisant la quantité de film d'oxyde éliminée de la face inférieure, l'auto-dopage et la survenue d'une nucléation de polysilicium sont contrecarrés de façon fiable, l'uniformité de résistivité de la surface de la tranche est élevée et la génération de nodules est contrecarrée.
PCT/JP2012/008043 2012-01-19 2012-12-17 Procédé de production d'une tranche épitaxiale WO2013108335A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112012005302.8T DE112012005302T5 (de) 2012-01-19 2012-12-17 Verfahren zur Fertigung eines Epitaxialwafers

Applications Claiming Priority (2)

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JP2012009408 2012-01-19
JP2012-009408 2012-01-19

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WO2013108335A1 true WO2013108335A1 (fr) 2013-07-25

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000021778A (ja) * 1998-06-29 2000-01-21 Tokin Corp エピタキシャル成長方法
JP2009224594A (ja) * 2008-03-17 2009-10-01 Shin Etsu Handotai Co Ltd シリコンエピタキシャルウェーハ及びその製造方法
JP2011023550A (ja) * 2009-07-16 2011-02-03 Shin Etsu Handotai Co Ltd 半導体エピタキシャルウエーハの製造方法及び半導体エピタキシャルウエーハ
JP2011114210A (ja) * 2009-11-27 2011-06-09 Sumco Corp エピタキシャルウェーハの製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2546986B2 (ja) * 1985-11-29 1996-10-23 九州電子金属 株式会社 半導体ウエ−ハ及びその製造方法
JP2827885B2 (ja) * 1994-02-12 1998-11-25 信越半導体株式会社 半導体単結晶基板およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000021778A (ja) * 1998-06-29 2000-01-21 Tokin Corp エピタキシャル成長方法
JP2009224594A (ja) * 2008-03-17 2009-10-01 Shin Etsu Handotai Co Ltd シリコンエピタキシャルウェーハ及びその製造方法
JP2011023550A (ja) * 2009-07-16 2011-02-03 Shin Etsu Handotai Co Ltd 半導体エピタキシャルウエーハの製造方法及び半導体エピタキシャルウエーハ
JP2011114210A (ja) * 2009-11-27 2011-06-09 Sumco Corp エピタキシャルウェーハの製造方法

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DE112012005302T5 (de) 2014-09-11

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