WO2013108335A1 - Production method for epitaxial wafer - Google Patents

Production method for epitaxial wafer Download PDF

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Publication number
WO2013108335A1
WO2013108335A1 PCT/JP2012/008043 JP2012008043W WO2013108335A1 WO 2013108335 A1 WO2013108335 A1 WO 2013108335A1 JP 2012008043 W JP2012008043 W JP 2012008043W WO 2013108335 A1 WO2013108335 A1 WO 2013108335A1
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oxide film
silicon substrate
epitaxial
back surface
epitaxial wafer
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PCT/JP2012/008043
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French (fr)
Japanese (ja)
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祐司 新井
雅典 黛
晃一 山野
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信越半導体株式会社
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Priority to DE112012005302.8T priority Critical patent/DE112012005302T5/en
Publication of WO2013108335A1 publication Critical patent/WO2013108335A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile

Definitions

  • the present invention relates to a method for manufacturing a silicon epitaxial wafer.
  • an epitaxial wafer is a silicon substrate that forms an epitaxial layer with a high concentration of impurities (dopant) and is configured to have either a p-type or n-type conductivity type.
  • a resistive substrate is used.
  • the conductivity type is p-type
  • boron (B) or the like is added as a dopant.
  • phosphorus (P), antimony (Sb), arsenic (As), or the like is used as the dopant. To be added.
  • an epitaxial wafer manufacturing method including a step of forming an oxide film for preventing auto-doping on the back surface of the silicon substrate is used prior to the growth of the epitaxial layer. Yes. Since the formed back surface oxide film can prevent the dopant from jumping out, generation of autodope can be effectively suppressed. In addition, since the epitaxial layer is grown on the surface side of the silicon substrate, the above-described impurity jumping is suppressed.
  • an epitaxial wafer that suppresses the growth of the polysilicon product described above, for example, as disclosed in Patent Document 1 and Patent Document 2, a part of an oxide film formed on the back side of the silicon substrate.
  • a method of growing an epitaxial layer after removing According to these manufacturing methods, the peripheral portion of the silicon substrate, and further, the back surface oxide film is removed in a wide range within the range where the influence of auto-doping can be tolerated, no polysilicon product is generated, and the LPD density is suppressed.
  • An epitaxial wafer can be obtained.
  • Patent Document 1 and Patent Document 2 have a certain effect on the suppression of the polysilicon product, but it is difficult to control the removal amount of the backside oxide film in consideration of the influence of auto-doping.
  • the removal amount of the back surface oxide film is excessively large, autodoping cannot be sufficiently suppressed, and there is a problem that the uniformity of resistivity within the wafer surface is deteriorated.
  • the present invention has been made in view of the above problems, and by optimizing the removal amount of the back surface oxide film, the generation of auto-dope and polysilicon products is surely suppressed, and the wafer surface of resistivity is achieved. It is an object of the present invention to provide a method for manufacturing an epitaxial wafer having a high internal uniformity and suppressing the generation of nodules.
  • an oxide film forming step of forming an oxide film on the back side of a silicon substrate containing a dopant an oxide film removing step of partially removing the formed oxide film, and thereafter
  • a method for producing an epitaxial wafer having an epitaxial growth step of vapor-phase growing an epitaxial layer on a silicon substrate In the oxide film removing step, at least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer periphery of the back surface of the silicon substrate is moved inward from the outermost periphery of the back surface of the silicon substrate to 0 ⁇ m or more and 30 ⁇ m.
  • the present invention provides a method for producing an epitaxial wafer, which is performed by removing with a width of less than.
  • an epitaxial wafer having an oxide film formed on the back side of a silicon substrate containing a dopant and an epitaxial layer grown on the silicon substrate by vapor phase, wherein the oxide film is At least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer peripheral portion of the back surface of the silicon substrate is removed inward from the outermost peripheral portion of the back surface of the silicon substrate with a width of 0 ⁇ m or more and less than 30 ⁇ m.
  • An epitaxial wafer is provided that is characterized by
  • Such an epitaxial wafer according to the present invention reliably suppresses auto-dope and polysilicon product generation, has high uniformity of resistivity within the wafer surface, and suppresses nodule generation.
  • an epitaxial wafer by suppressing the generation of a polysilicon product while suppressing auto-doping, and the uniformity of resistivity in the wafer surface is high. It becomes possible to manufacture an epitaxial wafer in which the generation of nodules is suppressed.
  • the process flowchart which showed an example of the manufacturing method of the epitaxial wafer of this invention is shown. It is explanatory drawing explaining the range of the oxide film removed by the oxide film removal process in this invention. The relationship between the resistivity in-plane distribution of an epitaxial layer and a back surface oxide film removal width in Examples and Comparative Examples is shown. It is explanatory drawing explaining the oxide film removal method using the sheet style back surface oxide film removal apparatus in this invention.
  • the present inventors have formed an oxide film forming step for forming an oxide film on the back side of a silicon substrate containing a dopant, an oxide film removing step for removing a part of the formed oxide film, and then on the silicon substrate.
  • the oxide film removing step at least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer peripheral portion of the back surface of the silicon substrate is moved inward from the outermost peripheral portion of the back surface of the silicon substrate to 0 ⁇ m or more and 30 ⁇ m.
  • the present invention provides a method for producing an epitaxial wafer, which is performed by removing with a width of less than. The present invention will be described in detail below.
  • FIG. 1 is a process flow diagram showing an example of the epitaxial wafer manufacturing method of the present invention.
  • a dopant for example, boron (B) when the conductivity type is p-type, phosphorus (P), antimony when the conductivity type is n-type.
  • Such a low-resistivity silicon substrate is liable to cause autodoping, and therefore is preferable because it has a large improvement effect when used in the present invention.
  • an oxide film forming step for forming an oxide film on the back side of the silicon substrate containing the dopant is performed (FIG. 1B).
  • the oxide film is preferably formed by a CVD method.
  • a CVD silicon oxide film can be easily formed by depositing and forming a silicon oxide film on the back side of the silicon substrate by the CVD method.
  • an oxide film removing step for removing a part of the formed oxide film is performed (FIG. 1C).
  • the present invention removes at least the oxide film 3 of the chamfered portion 2 of the silicon substrate 1 and removes the oxide film 3 on the outer peripheral portion of the back surface of the silicon substrate 1 as shown in FIG.
  • the silicon substrate is removed by removing it from the outermost peripheral portion 5 of the back surface 4 with a width of 0 ⁇ m or more and less than 30 ⁇ m (back surface oxide film removal width).
  • nodule may be generated, but the oxide film extends to the end of the wafer chamfered portion 2 (that is, the outermost peripheral portion 5 of the silicon substrate back surface 4). It was confirmed that no nodules were generated when 3 was removed.
  • the removal of the oxide film 3 on the outer peripheral portion of the back surface of the silicon substrate 1 is performed with a width of 0 ⁇ m or more and less than 30 ⁇ m (back surface oxide film removing width) inward from the outermost peripheral portion 5 of the silicon substrate back surface 4.
  • production is suppressed and it is possible to fully suppress auto dope.
  • Such an oxide film removing method is not particularly limited.
  • the silicon substrate 1 is set in a sheet-type back surface oxide film removing apparatus 7 as shown in FIG. 4, and the oxide film is etched with an aqueous solution containing HF or the like. It can be done by doing.
  • the oxide film 3 on the chamfered portion 2 of the silicon substrate 1 is removed, and at the same time, the back surface oxide film removal width is increased.
  • the width can be set to 0 ⁇ m or more and less than 30 ⁇ m. Then, it is preferable to perform rinsing and drying continuously by using this sheet style back surface oxide film removing apparatus 7.
  • an epitaxial growth process is performed in which an epitaxial layer is vapor-phase grown on the silicon substrate (FIG. 1D).
  • the epitaxial growth step can be performed by a conventionally known method.
  • An epitaxial growth apparatus is used to deposit an epitaxial layer on the surface 6 (surface on which the epitaxial layer is grown) of the silicon substrate with a predetermined thickness ( For example, it can be grown to 10 ⁇ m to 100 ⁇ m).
  • the epitaxial growth apparatus to be used is not particularly limited, and generally, a vertical type, a cylinder type and a single wafer type are widely used, and any apparatus can be used in the present invention.
  • the epitaxial wafer of the present invention is manufactured by the above-described epitaxial wafer manufacturing method of the present invention, and is vapor-phase grown on the silicon substrate containing an oxide film formed on the back side of the silicon substrate containing the dopant.
  • An epitaxial layer At least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer periphery of the back surface of the silicon substrate has a width of 0 ⁇ m or more and less than 30 ⁇ m inward from the outermost periphery of the back surface of the silicon substrate. It has been removed.
  • An oxide film for preventing auto-doping is formed on the back side of a silicon substrate having a resistivity of 1 m ⁇ ⁇ cm containing phosphorus as an impurity (dopant) by CVD, and then suppressing the generation of polysilicon products (nodules) Therefore, a silicon substrate was prepared in which the oxide film formed on the chamfered portion and the oxide film on the outer peripheral portion of the back surface were removed from the outermost peripheral portion on the back surface of the silicon substrate by the width of 0 ⁇ m and 28 ⁇ m.
  • An epitaxial layer having an epi resistivity of 1.5 ⁇ ⁇ cm and an epi film thickness of 10 ⁇ m is grown on the silicon substrate using a growth temperature of 1130 ° C., a dopant gas of PH 3 , and a film forming gas of trichlorosilane (TCS).
  • An epitaxial wafer to be a sample was manufactured by performing epitaxial growth (CVD method). The epi-resistivity measurement of the epitaxial wafer manufactured at this time was implemented.
  • FIG. 3 shows the relationship between the epitaxial resistivity in-plane distribution (%) and the removal width ( ⁇ m) of the back oxide film.
  • An oxide film for preventing auto-doping is formed on the back side of a silicon substrate having a resistivity of 1 m ⁇ ⁇ cm containing phosphorus as an impurity (dopant) by CVD, and then suppressing the generation of polysilicon products (nodules) Therefore, a silicon substrate was prepared in which the oxide film formed on the chamfered portion and the oxide film on the outer peripheral portion of the back surface were removed from the outermost peripheral portion on the back surface of the silicon substrate by 40 to 300 ⁇ m.
  • An epitaxial layer having an epi resistivity of 1.5 ⁇ ⁇ cm and an epi film thickness of 10 ⁇ m is grown on the silicon substrate using a growth temperature of 1130 ° C., a dopant gas of PH 3 , and a film forming gas of trichlorosilane (TCS).
  • An epitaxial wafer as a sample was manufactured by performing epitaxial growth (CVD method). The epi-resistivity measurement of the epitaxial wafer manufactured at this time was implemented.
  • FIG. 3 shows the relationship between the epitaxial resistivity in-plane distribution (%) and the removal width ( ⁇ m) of the back oxide film.
  • the present invention is not limited to the above embodiment.
  • the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

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Abstract

In the present invention, a production method for an epitaxial wafer has an oxide film forming step for forming an oxide film on the bottom face side of a silicon substrate that includes a dopant, an oxide film removing step for removing a portion of the formed oxide film, and a subsequent epitaxial growth step for growing an epitaxial layer on the silicon substrate by vapor phase epitaxy. The production method for an epitaxial wafer is characterized in that the oxide film removing step is carried out by removing at least the oxide film on a chamfered portion of the silicon substrate and removing the oxide film on the outer circumferential portion of the bottom face of the silicon substrate at a width of at least 0μm but less than 30μm inwards from the outermost circumferential portion of the bottom face of the silicon substrate. Thus, provided is the production method for an epitaxial wafer in which by optimizing the amount of oxide film removed from the bottom face, auto-doping and the occurrence of polysilicon nucleation is reliably suppressed, the uniformity of resistivity of the wafer surface is high, and the generation of nodules is suppressed.

Description

エピタキシャルウェーハの製造方法Epitaxial wafer manufacturing method
　本発明はシリコンエピタキシャルウェーハの製造方法に関する。 The present invention relates to a method for manufacturing a silicon epitaxial wafer.
　エピタキシャルウェーハは、パワーデバイス等の用途の場合、エピタキシャル層を形成するシリコン基板として、不純物（ドーパント）を高濃度に添加し、ｐ型又はｎ型のいずれかの導電型を備えるよう構成された低抵抗基板が用いられる。
　導電型をｐ型とする場合には、ドーパントとしてボロン（Ｂ）等が添加され、ｎ型とする場合には、ドーパントとしてリン（Ｐ）、アンチモン（Ｓｂ）、ヒ素（Ａｓ）等がシリコン基板に添加される。ただし、このようなドーパントが添加されたシリコン基板上に、エピタキシャル層を成長させるべく前記基板を高温（１０００～１２００℃）に加熱する場合、上述したドーパントがシリコン基板から飛び出し、成長したエピタキシャル層中に取り込まれる現象（オートドープ）が発生するという問題がある。このオートドープの発生は、抵抗率のウェーハ面内均一性の悪化等を引き起こすことから、できる限り抑制する必要がある。 In the case of applications such as power devices, an epitaxial wafer is a silicon substrate that forms an epitaxial layer with a high concentration of impurities (dopant) and is configured to have either a p-type or n-type conductivity type. A resistive substrate is used.
When the conductivity type is p-type, boron (B) or the like is added as a dopant. When the conductivity type is n-type, phosphorus (P), antimony (Sb), arsenic (As), or the like is used as the dopant. To be added. However, when the substrate is heated to a high temperature (1000 to 1200 ° C.) to grow an epitaxial layer on a silicon substrate to which such a dopant is added, the above-mentioned dopant jumps out of the silicon substrate and grows in the grown epitaxial layer. There is a problem that a phenomenon (auto-doping) is taken in. The occurrence of this auto-doping causes a deterioration in the uniformity of the in-wafer surface of the resistivity and the like, and therefore needs to be suppressed as much as possible.
　上述のオートドープを抑制するため、エピタキシャル層の成長に先立って、前記シリコン基板の裏面に対して、オートドープを防止するための酸化膜を形成する工程を有するエピタキシャルウェーハの製造方法が用いられている。形成された裏面酸化膜によって、前記ドーパントの飛び出しを防ぐことができるため、オートドープの発生を有効に抑制できる。なお、シリコン基板の表面側については、エピタキシャル層を成長させるため、上述の不純物の飛び出しは抑制されている。 In order to suppress the above-mentioned auto-doping, an epitaxial wafer manufacturing method including a step of forming an oxide film for preventing auto-doping on the back surface of the silicon substrate is used prior to the growth of the epitaxial layer. Yes. Since the formed back surface oxide film can prevent the dopant from jumping out, generation of autodope can be effectively suppressed. In addition, since the epitaxial layer is grown on the surface side of the silicon substrate, the above-described impurity jumping is suppressed.
　しかしながら、上述の裏面酸化膜を形成した状態で、エピタキシャル層の成長を行った場合、ウェーハ周縁部の前記裏面酸化膜上には、いわゆる「ノジュール」と呼ばれる、ポリシリコンの異常成長による微小な突起状の生成物が発生し、このポリシリコン生成物がエピタキシャル成長処理中に脱落してエピタキシャル層の表面に付着するという問題がある。その場合、エピタキシャルウェーハ表面で観察されるＬＰＤ（Ｌｉｇｈｔ　Ｐｏｉｎｔ　Ｄｅｆｅｃｔ）密度の増加や、半導体デバイス製造工程で脱落してウェーハ表面に付着し、酸化膜のパターニング不良を始めとする様々なトラブルを引き起こす恐れがある。 However, when the epitaxial layer is grown in a state where the above-described back surface oxide film is formed, on the back surface oxide film at the peripheral edge portion of the wafer, so-called “nodules”, minute projections due to abnormal growth of polysilicon. There is a problem that a product of a shape is generated, and this polysilicon product drops off during the epitaxial growth process and adheres to the surface of the epitaxial layer. In that case, there is a risk of increasing the LPD (Light Point Defect) density observed on the epitaxial wafer surface, dropping off in the semiconductor device manufacturing process and adhering to the wafer surface, causing various troubles such as defective oxide film patterning. There is.
　そのため、上述のポリシリコン生成物の成長を抑制するエピタキシャルウェーハの製造方法として、例えば特許文献１及び特許文献２に開示されているように、前記シリコン基板の裏面側に形成した酸化膜の一部を除去した上で、エピタキシャル層の成長を行う方法が挙げられる。これらの製造方法によれば、前記シリコン基板の周縁部、さらにはオートドープの影響が許容できる範囲内で裏面酸化膜を広範囲に除去し、ポリシリコン生成物の発生がなく、ＬＰＤ密度が抑制されたエピタキシャルウェーハを得ることができるとしている。 Therefore, as a method for manufacturing an epitaxial wafer that suppresses the growth of the polysilicon product described above, for example, as disclosed in Patent Document 1 and Patent Document 2, a part of an oxide film formed on the back side of the silicon substrate. There is a method of growing an epitaxial layer after removing. According to these manufacturing methods, the peripheral portion of the silicon substrate, and further, the back surface oxide film is removed in a wide range within the range where the influence of auto-doping can be tolerated, no polysilicon product is generated, and the LPD density is suppressed. An epitaxial wafer can be obtained.
　しかしながら、特許文献１及び特許文献２の発明では、ポリシリコン生成物の抑制については一定の効果を有するものの、オートドープの影響を考慮した上での前記裏面酸化膜の除去量の制御が困難であり、裏面酸化膜の除去量が大きくなりすぎた場合には、オートドープを十分に抑制することができず、抵抗率のウェーハ面内均一性が悪化するという問題があった。 However, the inventions of Patent Document 1 and Patent Document 2 have a certain effect on the suppression of the polysilicon product, but it is difficult to control the removal amount of the backside oxide film in consideration of the influence of auto-doping. In addition, when the removal amount of the back surface oxide film is excessively large, autodoping cannot be sufficiently suppressed, and there is a problem that the uniformity of resistivity within the wafer surface is deteriorated.
特開昭６２－１２８５２０号公報JP-A-62-128520 特開２０００－２１７７８号公報JP 2000-21778 A
　本発明は、上記問題に鑑みてなされたものであって、裏面酸化膜の除去量の適正化を図ることによって、確実にオートドープ及びポリシリコン生成物の発生を抑制し、抵抗率のウェーハ面内均一性が高く、ノジュール発生の抑制が図られたエピタキシャルウェーハの製造方法を提供することを目的とする。 The present invention has been made in view of the above problems, and by optimizing the removal amount of the back surface oxide film, the generation of auto-dope and polysilicon products is surely suppressed, and the wafer surface of resistivity is achieved. It is an object of the present invention to provide a method for manufacturing an epitaxial wafer having a high internal uniformity and suppressing the generation of nodules.
　上記課題を解決するため、本発明では、ドーパントを含有するシリコン基板の裏面側に酸化膜を形成する酸化膜形成工程と、該形成された酸化膜を一部除去する酸化膜除去工程と、その後シリコン基板上にエピタキシャル層を気相成長させるエピタキシャル成長工程を有するエピタキシャルウェーハの製造方法であって、
　前記酸化膜除去工程を、少なくとも、前記シリコン基板の面取り部の酸化膜を除去するとともに、前記シリコン基板の裏面外周部の酸化膜を、前記シリコン基板裏面の最外周部から内側に０μｍ以上かつ３０μｍ未満の幅で除去することにより行うことを特徴とするエピタキシャルウェーハの製造方法を提供する。 In order to solve the above problems, in the present invention, an oxide film forming step of forming an oxide film on the back side of a silicon substrate containing a dopant, an oxide film removing step of partially removing the formed oxide film, and thereafter A method for producing an epitaxial wafer having an epitaxial growth step of vapor-phase growing an epitaxial layer on a silicon substrate,
In the oxide film removing step, at least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer periphery of the back surface of the silicon substrate is moved inward from the outermost periphery of the back surface of the silicon substrate to 0 μm or more and 30 μm. The present invention provides a method for producing an epitaxial wafer, which is performed by removing with a width of less than.
　このような本発明のエピタキシャルウェーハの製造方法であれば、シリコン基板の裏面外周部の酸化膜除去を狭い幅（即ち、０μｍ以上かつ３０μｍ未満の幅）で行うことにより、確実にオートドープ及びポリシリコン生成物の発生を抑制し、抵抗率のウェーハ面内均一性が高く、ノジュール発生の抑制が図られたエピタキシャルウェーハを製造することができる。 With such a method for producing an epitaxial wafer of the present invention, by removing the oxide film on the outer periphery of the back surface of the silicon substrate with a narrow width (that is, a width of 0 μm or more and less than 30 μm), the autodope and poly It is possible to manufacture an epitaxial wafer in which the generation of silicon products is suppressed, the resistivity is highly uniform in the wafer surface, and the generation of nodules is suppressed.
　また、本発明によれば、ドーパントを含有するシリコン基板の裏面側に形成された酸化膜と、前記シリコン基板上に気相成長されたエピタキシャル層を有するエピタキシャルウェーハであって、前記酸化膜は、少なくとも、前記シリコン基板の面取り部の酸化膜が除去されるとともに、前記シリコン基板の裏面外周部の酸化膜が、前記シリコン基板裏面の最外周部から内側に０μｍ以上かつ３０μｍ未満の幅で除去されたものであることを特徴とするエピタキシャルウェーハが提供される。 Further, according to the present invention, there is provided an epitaxial wafer having an oxide film formed on the back side of a silicon substrate containing a dopant and an epitaxial layer grown on the silicon substrate by vapor phase, wherein the oxide film is At least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer peripheral portion of the back surface of the silicon substrate is removed inward from the outermost peripheral portion of the back surface of the silicon substrate with a width of 0 μm or more and less than 30 μm. An epitaxial wafer is provided that is characterized by
　このような本発明のエピタキシャルウェーハであれば、確実にオートドープ及びポリシリコン生成物の発生を抑制し、抵抗率のウェーハ面内均一性が高く、ノジュール発生の抑制が図られたものとなる。 Such an epitaxial wafer according to the present invention reliably suppresses auto-dope and polysilicon product generation, has high uniformity of resistivity within the wafer surface, and suppresses nodule generation.
　以上説明したように、本発明によれば、オートドープを抑制しつつ、ポリシリコン生成物の発生を抑制してエピタキシャルウェーハを製造することが可能であり、抵抗率のウェーハ面内均一性が高く、ノジュールの発生が抑制されたエピタキシャルウェーハを製造することが可能となる。 As described above, according to the present invention, it is possible to manufacture an epitaxial wafer by suppressing the generation of a polysilicon product while suppressing auto-doping, and the uniformity of resistivity in the wafer surface is high. It becomes possible to manufacture an epitaxial wafer in which the generation of nodules is suppressed.
本発明のエピタキシャルウェーハの製造方法の一例を示した工程フロー図を示す。The process flowchart which showed an example of the manufacturing method of the epitaxial wafer of this invention is shown. 本発明における酸化膜除去工程で除去する酸化膜の範囲を説明した説明図である。It is explanatory drawing explaining the range of the oxide film removed by the oxide film removal process in this invention. 実施例、比較例におけるエピタキシャル層の抵抗率面内分布と裏面酸化膜除去幅との関係を示す。The relationship between the resistivity in-plane distribution of an epitaxial layer and a back surface oxide film removal width in Examples and Comparative Examples is shown. 本発明における、枚様式裏面酸化膜除去装置を用いた酸化膜除去方法を説明した説明図である。It is explanatory drawing explaining the oxide film removal method using the sheet style back surface oxide film removal apparatus in this invention.
　上記のように、オートドープを抑制しつつ、ノジュールの発生を抑制可能なエピタキシャルウェーハの製造方法が求められていた。 As described above, there has been a demand for an epitaxial wafer manufacturing method capable of suppressing the generation of nodules while suppressing autodoping.
　特開２０１１－１１４２１０号公報では裏面酸化膜除去幅が３０μｍ未満ではノジュール発生があるため３０μｍ以上の裏面酸化膜の除去が必要とされているが、本発明者らは、シリコン基板の裏面外周部の酸化膜を、前記シリコン基板裏面の最外周部から内側に０μｍ以上かつ３０μｍ未満の幅で除去する場合には、実際には、基板とサセプタがほぼ密着するためにエピタキシャル層を成長させる際に用いる成膜ガス（例えばトリクロロシラン等）の回り込みがないため、ノジュールが発生しないことを見出した。 In Japanese Patent Application Laid-Open No. 2011-114210, when the back oxide film removal width is less than 30 μm, nodule is generated, and therefore it is necessary to remove the back oxide film having a thickness of 30 μm or more. When the oxide film is removed with a width of 0 μm or more and less than 30 μm inward from the outermost peripheral portion of the back surface of the silicon substrate, in actuality, the epitaxial layer is grown because the substrate and the susceptor are almost in close contact with each other. It has been found that no nodules are generated because there is no wraparound of the film forming gas used (for example, trichlorosilane).
　即ち、本発明者らは、ドーパントを含有するシリコン基板の裏面側に酸化膜を形成する酸化膜形成工程と、該形成された酸化膜を一部除去する酸化膜除去工程と、その後シリコン基板上にエピタキシャル層を気相成長させるエピタキシャル成長工程を有するエピタキシャルウェーハの製造方法であって、
　前記酸化膜除去工程を、少なくとも、前記シリコン基板の面取り部の酸化膜を除去するとともに、前記シリコン基板の裏面外周部の酸化膜を、前記シリコン基板裏面の最外周部から内側に０μｍ以上かつ３０μｍ未満の幅で除去することにより行うことを特徴とするエピタキシャルウェーハの製造方法を提供する。以下、本発明について更に詳述する。 That is, the present inventors have formed an oxide film forming step for forming an oxide film on the back side of a silicon substrate containing a dopant, an oxide film removing step for removing a part of the formed oxide film, and then on the silicon substrate. A method for producing an epitaxial wafer having an epitaxial growth step of vapor-phase-growing an epitaxial layer.
In the oxide film removing step, at least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer peripheral portion of the back surface of the silicon substrate is moved inward from the outermost peripheral portion of the back surface of the silicon substrate to 0 μm or more and 30 μm. The present invention provides a method for producing an epitaxial wafer, which is performed by removing with a width of less than. The present invention will be described in detail below.
　図１に本発明のエピタキシャルウェーハの製造方法の一例を示した工程フロー図を示す。
　図１（Ａ）で準備するシリコン基板は、ドーパントとして、例えば、導電型をｐ型とする場合には、ボロン（Ｂ）、導電型をｎ型とする場合には、リン（Ｐ）、アンチモン（Ｓｂ）、ヒ素（Ａｓ）等が添加された、例えば、抵抗率が１ｍΩ・ｃｍ以上２０ｍΩ・ｃｍ以下のシリコン基板が好ましい。
　このような抵抗率の低いシリコン基板はオートドープを引き起こし易いので、本発明に用いた場合、得られる改善効果も大きいために好ましい。 FIG. 1 is a process flow diagram showing an example of the epitaxial wafer manufacturing method of the present invention.
In the silicon substrate prepared in FIG. 1A, as a dopant, for example, boron (B) when the conductivity type is p-type, phosphorus (P), antimony when the conductivity type is n-type. A silicon substrate to which (Sb), arsenic (As), or the like is added, for example, having a resistivity of 1 mΩ · cm to 20 mΩ · cm is preferable.
Such a low-resistivity silicon substrate is liable to cause autodoping, and therefore is preferable because it has a large improvement effect when used in the present invention.
　次いで、ドーパントを含有するシリコン基板の裏面側に酸化膜を形成する酸化膜形成工程を行う（図１（Ｂ））。
　前記酸化膜の形成は、ＣＶＤ法により行うことが好ましい。ＣＶＤ法によりシリコン基板の裏面側にシリコン酸化膜を堆積して形成することにより、簡単にＣＶＤシリコン酸化膜を形成することができる。 Next, an oxide film forming step for forming an oxide film on the back side of the silicon substrate containing the dopant is performed (FIG. 1B).
The oxide film is preferably formed by a CVD method. A CVD silicon oxide film can be easily formed by depositing and forming a silicon oxide film on the back side of the silicon substrate by the CVD method.
　次いで、形成された酸化膜を一部除去する酸化膜除去工程を行う（図１（Ｃ））。
　ここで、本発明は、図２に示すように、酸化膜除去工程を、少なくともシリコン基板１の面取り部２の酸化膜３を除去するとともに、前記シリコン基板１の裏面外周部の酸化膜３を、前記シリコン基板裏面４の最外周部５から内側に０μｍ以上かつ３０μｍ未満の幅（裏面酸化膜除去幅）で除去することにより行うことを特徴とする。 Next, an oxide film removing step for removing a part of the formed oxide film is performed (FIG. 1C).
Here, as shown in FIG. 2, the present invention removes at least the oxide film 3 of the chamfered portion 2 of the silicon substrate 1 and removes the oxide film 3 on the outer peripheral portion of the back surface of the silicon substrate 1 as shown in FIG. The silicon substrate is removed by removing it from the outermost peripheral portion 5 of the back surface 4 with a width of 0 μm or more and less than 30 μm (back surface oxide film removal width).
　本発明者らにより、ウェーハ面取り部２に酸化膜３が残っているとノジュール発生の可能性があるが、ウェーハ面取り部２の端（即ち、シリコン基板裏面４の最外周部５）まで酸化膜３が除去されている場合には、ノジュールが発生しないことが確認できた。 If the oxide film 3 remains on the wafer chamfered portion 2 by the present inventors, nodule may be generated, but the oxide film extends to the end of the wafer chamfered portion 2 (that is, the outermost peripheral portion 5 of the silicon substrate back surface 4). It was confirmed that no nodules were generated when 3 was removed.
　また、シリコン基板１の裏面外周部の酸化膜３の除去は、シリコン基板裏面４の最外周部５から内側に０μｍ以上かつ３０μｍ未満の幅（裏面酸化膜除去幅）で行うことで、ノジュールの発生が抑制され、かつ、オートドープを十分に抑制することが可能である。 Further, the removal of the oxide film 3 on the outer peripheral portion of the back surface of the silicon substrate 1 is performed with a width of 0 μm or more and less than 30 μm (back surface oxide film removing width) inward from the outermost peripheral portion 5 of the silicon substrate back surface 4. Generation | occurrence | production is suppressed and it is possible to fully suppress auto dope.
　シリコン基板１の裏面外周部の酸化膜３の除去を、シリコン基板裏面４の最外周部５から内側に３０μｍ以上の幅（裏面酸化膜除去幅）で酸化膜を除去した場合には、ノジュールの発生は抑制されるものの、オートドープを十分に抑制することができず、エピタキシャル層の抵抗率面内均一性が悪化する。 When the oxide film 3 on the outer periphery of the back surface of the silicon substrate 1 is removed by removing the oxide film with a width of 30 μm or more (back surface oxide film removal width) from the outermost periphery 5 of the back surface 4 of the silicon substrate, Although generation | occurrence | production is suppressed, auto dope cannot fully be suppressed and the resistivity in-plane uniformity of an epitaxial layer deteriorates.
　このような酸化膜除去方法としては、特に限定されないが、例えば、図４に示すような枚様式裏面酸化膜除去装置７にシリコン基板１をセットし、ＨＦを含有する水溶液等で酸化膜のエッチングをすることで行うことができる。
　この際、シリコン基板１の裏面外周部に設置されたＨＦエッチングブロック用パッキン８の位置を調整することで、シリコン基板１の面取り部２の酸化膜３を除去すると同時に、裏面酸化膜除去幅を０μｍ以上かつ３０μｍ未満の幅に設定することが可能となる。その後、この枚様式裏面酸化膜除去装置７を用いてリンス、乾燥を連続で行うことが好ましい。 Such an oxide film removing method is not particularly limited. For example, the silicon substrate 1 is set in a sheet-type back surface oxide film removing apparatus 7 as shown in FIG. 4, and the oxide film is etched with an aqueous solution containing HF or the like. It can be done by doing.
At this time, by adjusting the position of the HF etching block packing 8 provided on the outer peripheral portion of the back surface of the silicon substrate 1, the oxide film 3 on the chamfered portion 2 of the silicon substrate 1 is removed, and at the same time, the back surface oxide film removal width is increased. The width can be set to 0 μm or more and less than 30 μm. Then, it is preferable to perform rinsing and drying continuously by using this sheet style back surface oxide film removing apparatus 7.
　その後、シリコン基板上にエピタキシャル層を気相成長させるエピタキシャル成長工程を行う（図１（Ｄ））。 Thereafter, an epitaxial growth process is performed in which an epitaxial layer is vapor-phase grown on the silicon substrate (FIG. 1D).
　エピタキシャル成長工程は、従来行われている公知の方法で行うことが可能であり、エピタキシャル成長装置を用い、シリコン基板の表面６（エピタキシャル層を成長させる側の面）上にエピタキシャル層を所定の厚さ（例えば１０μｍ～１００μｍ）まで成長させることができる。用いるエピタキシャル成長装置は特に限定されず、一般的に、縦型、シリンダー型、枚葉型が広く使われており、本発明ではいずれの装置も用いることができる。 The epitaxial growth step can be performed by a conventionally known method. An epitaxial growth apparatus is used to deposit an epitaxial layer on the surface 6 (surface on which the epitaxial layer is grown) of the silicon substrate with a predetermined thickness ( For example, it can be grown to 10 μm to 100 μm). The epitaxial growth apparatus to be used is not particularly limited, and generally, a vertical type, a cylinder type and a single wafer type are widely used, and any apparatus can be used in the present invention.
　本発明のエピタキシャルウェーハは、上記した本発明のエピタキシャルウェーハの製造方法により製造されたものであり、ドーパントを含有するシリコン基板の裏面側に形成された酸化膜と、シリコン基板上に気相成長されたエピタキシャル層を有する。この酸化膜は、少なくとも、シリコン基板の面取り部の酸化膜が除去されるとともに、シリコン基板の裏面外周部の酸化膜が、シリコン基板裏面の最外周部から内側に０μｍ以上かつ３０μｍ未満の幅で除去されたものである。
　このような本発明のエピタキシャルウェーハであれば、確実にオートドープ及びポリシリコン生成物の発生を抑制し、抵抗率のウェーハ面内均一性が高く、ノジュール発生の抑制が図られたものとなる。 The epitaxial wafer of the present invention is manufactured by the above-described epitaxial wafer manufacturing method of the present invention, and is vapor-phase grown on the silicon substrate containing an oxide film formed on the back side of the silicon substrate containing the dopant. An epitaxial layer. At least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer periphery of the back surface of the silicon substrate has a width of 0 μm or more and less than 30 μm inward from the outermost periphery of the back surface of the silicon substrate. It has been removed.
With such an epitaxial wafer of the present invention, generation of autodope and polysilicon product is surely suppressed, the uniformity of resistivity in the wafer surface is high, and nodule generation is suppressed.
　以下に本発明の実施例及び比較例を挙げて、本発明をより詳細に説明するが、これらは本発明を限定するものではない。 Hereinafter, the present invention will be described in more detail with reference to Examples and Comparative Examples of the present invention, but these do not limit the present invention.
（実施例）
　不純物（ドーパント）としてリンを含有した抵抗率が１ｍΩ・ｃｍのシリコン基板の裏面側にオートドープ防止のための酸化膜をＣＶＤ法により形成し、その後、ポリシリコン生成物（ノジュール）の発生を抑制するため、面取り部に形成されている酸化膜及び裏面外周部の酸化膜をシリコン基板裏面の最外周部から内側に０μｍ、及び２８μｍの幅だけ除去したシリコン基板を用意した。
　そのシリコン基板上に、成長温度１１３０度、ドーパントガスにＰＨ３、成膜ガスにトリクロロシラン（ＴＣＳ）を用いてエピ抵抗率１．５Ω・ｃｍ、エピ膜厚１０μｍとなるようなエピタキシャル層を成長させるエピタキシャル成長（ＣＶＤ法）を行うことによって、サンプルとなるエピタキシャルウェーハを製造した。
　このとき製造されたエピタキシャルウェーハのエピ抵抗率測定を実施した。図３にエピ抵抗率面内分布（％）と裏面酸化膜の除去幅（μｍ）との関係結果を示す。 (Example)
An oxide film for preventing auto-doping is formed on the back side of a silicon substrate having a resistivity of 1 mΩ · cm containing phosphorus as an impurity (dopant) by CVD, and then suppressing the generation of polysilicon products (nodules) Therefore, a silicon substrate was prepared in which the oxide film formed on the chamfered portion and the oxide film on the outer peripheral portion of the back surface were removed from the outermost peripheral portion on the back surface of the silicon substrate by the width of 0 μm and 28 μm.
An epitaxial layer having an epi resistivity of 1.5 Ω · cm and an epi film thickness of 10 μm is grown on the silicon substrate using a growth temperature of 1130 ° C., a dopant gas of PH 3 , and a film forming gas of trichlorosilane (TCS). An epitaxial wafer to be a sample was manufactured by performing epitaxial growth (CVD method).
The epi-resistivity measurement of the epitaxial wafer manufactured at this time was implemented. FIG. 3 shows the relationship between the epitaxial resistivity in-plane distribution (%) and the removal width (μm) of the back oxide film.
（比較例）
　不純物（ドーパント）としてリンを含有した抵抗率が１ｍΩ・ｃｍのシリコン基板の裏面側にオートドープ防止のための酸化膜をＣＶＤ法により形成し、その後、ポリシリコン生成物（ノジュール）の発生を抑制するため、面取り部に形成されている酸化膜及び裏面外周部の酸化膜をシリコン基板裏面の最外周部から内側に４０～３００μｍだけ除去したシリコン基板を用意した。
　そのシリコン基板上に、成長温度１１３０度、ドーパントガスにＰＨ３、成膜ガスにトリクロロシラン（ＴＣＳ）を用いてエピ抵抗率１．５Ω・ｃｍ、エピ膜厚１０μｍとなるようなエピタキシャル層を成長させるエピタキシャル成長（ＣＶＤ法）を行うことによってサンプルとなるエピタキシャルウェーハを製造した。
　このとき製造されたエピタキシャルウェーハのエピ抵抗率測定を実施した。図３にエピ抵抗率面内分布（％）と裏面酸化膜の除去幅（μｍ）との関係結果を示す。 (Comparative example)
An oxide film for preventing auto-doping is formed on the back side of a silicon substrate having a resistivity of 1 mΩ · cm containing phosphorus as an impurity (dopant) by CVD, and then suppressing the generation of polysilicon products (nodules) Therefore, a silicon substrate was prepared in which the oxide film formed on the chamfered portion and the oxide film on the outer peripheral portion of the back surface were removed from the outermost peripheral portion on the back surface of the silicon substrate by 40 to 300 μm.
An epitaxial layer having an epi resistivity of 1.5 Ω · cm and an epi film thickness of 10 μm is grown on the silicon substrate using a growth temperature of 1130 ° C., a dopant gas of PH 3 , and a film forming gas of trichlorosilane (TCS). An epitaxial wafer as a sample was manufactured by performing epitaxial growth (CVD method).
The epi-resistivity measurement of the epitaxial wafer manufactured at this time was implemented. FIG. 3 shows the relationship between the epitaxial resistivity in-plane distribution (%) and the removal width (μm) of the back oxide film.
　図３より、裏面酸化膜除去幅が４０～３００μｍの間では裏面酸化膜除去幅が狭くなるに伴いエピ抵抗率面内分布は徐々に改善されていく傾向があるが、抵抗率のウェーハ面内均一性が不十分であった（比較例）。一方、裏面酸化膜除去幅が３０μｍ未満になるとエピ抵抗率面内分布が急激に改善されることが確認できた（実施例）。
　このとき、全てのサンプルにおいてノジュールは発生していないことが確認された。 From FIG. 3, when the back surface oxide film removal width is between 40 and 300 μm, the epi-resistivity in-plane distribution tends to be gradually improved as the back surface oxide film removal width becomes narrow. Uniformity was insufficient (comparative example). On the other hand, it was confirmed that the epi-resistivity in-plane distribution was drastically improved when the back oxide film removal width was less than 30 μm (Example).
At this time, it was confirmed that no nodules were generated in all the samples.
　以上の結果より、裏面酸化膜除去幅を３０μｍ未満かつ０μｍ以上としたシリコン基板を用いることで、オートドープ及びポリシリコン生成物の発生を抑制し、抵抗率のウェーハ面内均一性が大きく改善し、ノジュール発生が抑制されたエピタキシャルウェーハを製造することができることが示された。同様の結果は、エピタキシャル成長装置をバッチ式、枚葉式のいずれのタイプの装置を用いた場合も得られ、また、ドーパントをｐ型とした場合も同様の結果になった。 From the above results, by using a silicon substrate with a back oxide film removal width of less than 30 μm and 0 μm or more, the generation of auto-dope and polysilicon products is suppressed, and the uniformity of resistivity in the wafer surface is greatly improved. It has been shown that an epitaxial wafer in which generation of nodules is suppressed can be manufactured. Similar results were obtained when the batch growth type or single wafer type epitaxial growth apparatus was used, and the same result was obtained when the dopant was p-type.
　なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。 Note that the present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

Claims (2)

  1. 　ドーパントを含有するシリコン基板の裏面側に酸化膜を形成する酸化膜形成工程と、該形成された酸化膜を一部除去する酸化膜除去工程と、その後シリコン基板上にエピタキシャル層を気相成長させるエピタキシャル成長工程を有するエピタキシャルウェーハの製造方法であって、
    　前記酸化膜除去工程を、少なくとも、前記シリコン基板の面取り部の酸化膜を除去するとともに、前記シリコン基板の裏面外周部の酸化膜を、前記シリコン基板裏面の最外周部から内側に０μｍ以上かつ３０μｍ未満の幅で除去することにより行うことを特徴とするエピタキシャルウェーハの製造方法。     An oxide film forming step for forming an oxide film on the back side of the silicon substrate containing the dopant, an oxide film removing step for removing a part of the formed oxide film, and then epitaxially growing an epitaxial layer on the silicon substrate. An epitaxial wafer manufacturing method having an epitaxial growth step,
    In the oxide film removing step, at least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer periphery of the back surface of the silicon substrate is moved inward from the outermost periphery of the back surface of the silicon substrate to 0 μm or more and 30 μm. A method for producing an epitaxial wafer, which is performed by removing with a width of less than.
  2. 　ドーパントを含有するシリコン基板の裏面側に形成された酸化膜と、前記シリコン基板上に気相成長されたエピタキシャル層を有するエピタキシャルウェーハであって、
    　前記酸化膜は、少なくとも、前記シリコン基板の面取り部の酸化膜が除去されるとともに、前記シリコン基板の裏面外周部の酸化膜が、前記シリコン基板裏面の最外周部から内側に０μｍ以上かつ３０μｍ未満の幅で除去されたものであることを特徴とするエピタキシャルウェーハ。
     
     
          An epitaxial wafer having an oxide film formed on the back side of a silicon substrate containing a dopant and an epitaxial layer vapor-phase grown on the silicon substrate,
    As for the oxide film, at least the oxide film on the chamfered portion of the silicon substrate is removed, and the oxide film on the outer periphery of the back surface of the silicon substrate is not less than 0 μm and less than 30 μm inward from the outermost periphery of the back surface of the silicon substrate. An epitaxial wafer characterized by being removed at a width of


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JP2011023550A (en) * 2009-07-16 2011-02-03 Shin Etsu Handotai Co Ltd Method for manufacturing semiconductor epitaxial wafer, and semiconductor epitaxial wafer
JP2011114210A (en) * 2009-11-27 2011-06-09 Sumco Corp Method of manufacturing epitaxial wafer

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JP2546986B2 (en) * 1985-11-29 1996-10-23 九州電子金属 株式会社 Semiconductor wafer and method of manufacturing the same
JP2827885B2 (en) * 1994-02-12 1998-11-25 信越半導体株式会社 Semiconductor single crystal substrate and method of manufacturing the same

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JP2000021778A (en) * 1998-06-29 2000-01-21 Tokin Corp Method for epitaxial growth
JP2009224594A (en) * 2008-03-17 2009-10-01 Shin Etsu Handotai Co Ltd Silicon epitaxial wafer and method for manufacturing the same
JP2011023550A (en) * 2009-07-16 2011-02-03 Shin Etsu Handotai Co Ltd Method for manufacturing semiconductor epitaxial wafer, and semiconductor epitaxial wafer
JP2011114210A (en) * 2009-11-27 2011-06-09 Sumco Corp Method of manufacturing epitaxial wafer

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