JP5273150B2 - Manufacturing method of silicon epitaxial wafer - Google Patents

Manufacturing method of silicon epitaxial wafer Download PDF

Info

Publication number
JP5273150B2
JP5273150B2 JP2010530704A JP2010530704A JP5273150B2 JP 5273150 B2 JP5273150 B2 JP 5273150B2 JP 2010530704 A JP2010530704 A JP 2010530704A JP 2010530704 A JP2010530704 A JP 2010530704A JP 5273150 B2 JP5273150 B2 JP 5273150B2
Authority
JP
Japan
Prior art keywords
single crystal
silicon single
silicon
film
vapor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010530704A
Other languages
Japanese (ja)
Other versions
JPWO2010035409A1 (en
Inventor
知佐 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to JP2010530704A priority Critical patent/JP5273150B2/en
Publication of JPWO2010035409A1 publication Critical patent/JPWO2010035409A1/en
Application granted granted Critical
Publication of JP5273150B2 publication Critical patent/JP5273150B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02634Homoepitaxy

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Vapour Deposition (AREA)

Description

本発明は、シリコン単結晶基板にシリコン単結晶膜を気相成長させるシリコンエピタキシャルウェーハの製造方法に関する。
The present invention relates to a method for manufacturing a silicon epitaxial wafer in which a silicon single crystal film is vapor-phase grown on a silicon single crystal substrate.

パワーMOSFET、IGBT等のパワー素子の素材として、シリコン単結晶基板の表面にエピタキシャル膜を形成したシリコンエピタキシャルウェーハが使用されている。シリコンエピタキシャルウェーハの製造工程、特にエピタキシャル処理工程における重大な問題の一つとしてオートドープがある。オートドープは、シリコン単結晶基板の表面にエピタキシャル膜を形成する過程で、基板中のドーパント物質が裏面から拡散により表面側のエピタキシャル膜中に混入する現象であり、この混入によりエピタキシャル膜の抵抗分布が半径方向で不均一化するという問題を生じる。   A silicon epitaxial wafer in which an epitaxial film is formed on the surface of a silicon single crystal substrate is used as a material for power elements such as power MOSFETs and IGBTs. One of the serious problems in the manufacturing process of a silicon epitaxial wafer, particularly the epitaxial processing process, is autodoping. Auto-doping is a phenomenon in which the dopant substance in the substrate is mixed into the epitaxial film on the front side by diffusion from the back side in the process of forming the epitaxial film on the surface of the silicon single crystal substrate. This causes the problem of non-uniformity in the radial direction.

この問題を解決するために、シリコンエピタキシャルウェーハの製造では、エピタキシャル処理に先立って、シリコン単結晶基板の裏面に保護膜を形成することが行われている。この保護膜として、例えばシリコン酸化膜が形成され、この膜をシリコン単結晶基板の裏面に形成することにより、ウェーハの裏面からドーパントが放出されてエピタキシャル膜へオートドープすることが防止される。通常、図5のように、この保護膜22はシリコン単結晶基板20の裏面側の主表面21のみに形成され、ウェーハの面取り部23(テーパ面)には形成されない。   In order to solve this problem, in the manufacture of a silicon epitaxial wafer, a protective film is formed on the back surface of the silicon single crystal substrate prior to the epitaxial process. As this protective film, for example, a silicon oxide film is formed, and by forming this film on the back surface of the silicon single crystal substrate, it is possible to prevent dopant from being released from the back surface of the wafer and autodoping into the epitaxial film. Normally, as shown in FIG. 5, the protective film 22 is formed only on the main surface 21 on the back surface side of the silicon single crystal substrate 20, and is not formed on the chamfered portion 23 (tapered surface) of the wafer.

これは、仮にシリコン単結晶基板の裏面の主表面と共に、面取り部もシリコン酸化膜で被覆した場合に、裏面の平面部(主表面)はサセプターに接触しているため問題は発生しないが、面取り部のシリコン酸化膜上には、シリコンの多結晶からなる塊状の突起(以後ノジュールという)が発生し、これが半導体素子製造工程で脱落し、その微小破片がシリコンエピタキシャルウェーハの表面に付着してしまい、露光用マスクを傷つけたり、酸化膜のピンホールの原因となったり、酸化膜のパターニング不良、蒸着金属配線の断線など様々なトラブルの原因となる。   This is because if the chamfered portion is covered with a silicon oxide film together with the main surface on the back surface of the silicon single crystal substrate, the flat surface portion (main surface) on the back surface is in contact with the susceptor. On the silicon oxide film, a massive projection (hereinafter referred to as a nodule) made of polycrystal of silicon is generated, which is dropped off in the semiconductor element manufacturing process, and the minute fragments adhere to the surface of the silicon epitaxial wafer. This may cause various troubles such as damage to the exposure mask, pinholes in the oxide film, poor patterning of the oxide film, and disconnection of the deposited metal wiring.

このノジュールは、上述のように面取り部に保護膜を形成しない、或いはそこに形成された保護膜をエピタキシャル処理に先立って除去することにより、発生が防止される。このため、面取り部に保護膜が存在しない状態でエピタキシャル処理が行われる。
しかし、エピタキシャル成長時に、この保護膜が形成されていない面取り部から、オートドープが生じてしまうというが問題があった。
The nodule is prevented from being generated by not forming the protective film on the chamfered portion as described above, or by removing the protective film formed thereon prior to the epitaxial process. For this reason, the epitaxial process is performed in a state where the protective film is not present in the chamfered portion.
However, there is a problem that autodoping occurs from the chamfered portion where the protective film is not formed during epitaxial growth.

これに対して、特許文献1では、面取りの角度を調整することによって、面取り部上に形成した保護膜に生じるノジュールを抑制する方法が記載されているが、この場合でもノジュール防止には十分ではなく、また、面取りの角度が、要求される基板の規格に合わない場合があるという問題があった。
On the other hand, Patent Document 1 describes a method of suppressing nodules generated in the protective film formed on the chamfered portion by adjusting the chamfering angle. In addition, there is a problem that the chamfering angle may not meet the required substrate standard.

特許第4078831号公報Japanese Patent No. 4078831

そこで、本発明は、このような問題点に鑑みてなされたもので、シリコン単結晶膜を気相成長させる際に、簡易な方法で、ノジュールとオートドープを同時に防止することができるシリコンエピタキシャルウェーハの製造方法を提供することを目的とする。   Therefore, the present invention has been made in view of such problems, and a silicon epitaxial wafer capable of simultaneously preventing nodules and autodoping by a simple method when vapor-phase-growing a silicon single crystal film. It aims at providing the manufacturing method of.

上記目的を達成するために、本発明は、シリコン単結晶基板の主表面上にシリコン単結晶膜を気相成長させるシリコンエピタキシャルウェーハの製造方法であって、シリコン単結晶基板のシリコン単結晶膜を気相成長させる主表面以外の表面に保護膜を形成する工程の後、気相成長原料ガスとHClガスを(0.6〜5):1の流量比で同時に流しながら前記シリコン単結晶基板の主表面上に前記シリコン単結晶膜を気相成長させる工程を有することを特徴とするシリコンエピタキシャルウェーハの製造方法を提供する。   In order to achieve the above object, the present invention provides a method for manufacturing a silicon epitaxial wafer, in which a silicon single crystal film is vapor-phase grown on a main surface of a silicon single crystal substrate, After the step of forming the protective film on the surface other than the main surface to be vapor-phase grown, the vapor-phase growth source gas and the HCl gas are simultaneously flowed at a flow rate ratio of (0.6 to 5): 1. There is provided a method for producing a silicon epitaxial wafer, comprising a step of vapor-phase-growing the silicon single crystal film on a main surface.

このように、保護膜をシリコン単結晶基板の裏面のみならず面取り部にも形成して、シリコン単結晶膜を気相成長させることで、オートドープを効果的に防止することができる。また、シリコン単結晶膜を気相成長させる際に、気相成長原料ガスとHClガスを同時に流しながら行うことで、基板の面取り部上の保護膜にノジュールが発生することを防止することができる。
これにより、簡易な方法で、オートドープとノジュールが同時に抑制された良質なシリコンエピタキシャルウェーハを製造することができる。
Thus, autodoping can be effectively prevented by forming the protective film not only on the back surface of the silicon single crystal substrate but also on the chamfered portion and vapor-depositing the silicon single crystal film. Further, when vapor-phase-growing a silicon single crystal film, it is possible to prevent the generation of nodules in the protective film on the chamfered portion of the substrate by simultaneously flowing the vapor-phase growth source gas and HCl gas. .
Thereby, a high-quality silicon epitaxial wafer in which auto-doping and nodules are simultaneously suppressed can be manufactured by a simple method.

このように、本発明において、反応炉内のクリーニングに用いられているHClガスを用いることで、特別な配管設備や除外設備を付加することなく、より簡便かつ低コストで本発明の製造方法を実施することができる。   Thus, in the present invention, by using the HCl gas used for cleaning the inside of the reactor, the production method of the present invention can be performed more easily and at low cost without adding special piping equipment or exclusion equipment. Can be implemented.

このような流量比で気相成長原料ガスとHClガスを流しながら気相成長させることで、ノジュールのより確実な防止と、良質なシリコン単結晶膜の成長の両方を、効率的に行うことができる。なお、前記気相成長原料ガスはキャリアガスによって希釈されていてもよいが、その場合はキャリアガスを除外した気相成長原料成分のみの流量比を用いればよい。   By performing vapor phase growth while flowing the vapor phase growth source gas and HCl gas at such a flow rate ratio, it is possible to efficiently perform both more reliable prevention of nodules and growth of a good quality silicon single crystal film. it can. The vapor phase growth source gas may be diluted with a carrier gas. In that case, the flow rate ratio of only the vapor phase growth source component excluding the carrier gas may be used.

本発明であれば、簡易な方法で、オートドープとノジュールが同時に防止された良質なシリコンエピタキシャルウェーハを製造することができる。
According to the present invention, a high-quality silicon epitaxial wafer in which auto-doping and nodules are simultaneously prevented can be manufactured by a simple method.

本発明におけるシリコン単結晶膜を気相成長させる際の反応炉内の温度、時間、ガス供給のタイミングの一例を示すグラフである。It is a graph which shows an example of the temperature in reactor, the time, and the timing of gas supply at the time of carrying out vapor phase growth of the silicon single crystal film in this invention. 比較例におけるシリコン単結晶膜を気相成長させる際の反応炉内の温度、時間、ガス供給のタイミングを示すグラフである。It is a graph which shows the temperature in reactor, the time, and the timing of gas supply at the time of carrying out vapor phase growth of the silicon single crystal film in a comparative example. 本発明の製造方法の実施態様の一例を示すフロー図である。It is a flowchart which shows an example of the embodiment of the manufacturing method of this invention. 実施例1及び比較例1で製造されたシリコンエピタキシャルウェーハの面取り部周辺を走査型電子顕微鏡で観察した図である。It is the figure which observed the chamfering part periphery of the silicon epitaxial wafer manufactured by Example 1 and Comparative Example 1 with the scanning electron microscope. 従来のシリコン単結晶膜を気相成長させる基板の断面概略図である。It is the cross-sectional schematic of the board | substrate which carries out the vapor phase growth of the conventional silicon single crystal film.

従来、シリコンエピタキシャルウェーハの製造において、シリコン単結晶膜を気相成長させる際のオートドープ防止のための保護膜は、ノジュールが発生しないようにウェーハの面取り部には形成されなかった(図5参照)。
しかし、本発明者らは、オートドープを抑えるには、基板の面取り部にも保護膜を形成することが不可欠であると考え、面取り部に保護膜を形成した場合に問題となるノジュールの防止策について検討を行った。その結果、気相成長時に気相成長原料ガスとHClガスを共に(0.6〜5):1の流量比で反応炉内に供給することで、面取り部でのシリコンの成長を阻害してノジュールの発生を抑制できることを見出して、本発明を完成させた。
Conventionally, in the manufacture of a silicon epitaxial wafer, a protective film for preventing autodoping when vapor-depositing a silicon single crystal film has not been formed on the chamfered portion of the wafer so that nodules are generated (see FIG. 5). ).
However, the present inventors consider that it is indispensable to form a protective film on the chamfered portion of the substrate in order to suppress auto-doping, and prevent nodules that are problematic when a protective film is formed on the chamfered portion. We examined the measures. As a result, during the vapor phase growth, both the vapor phase growth source gas and the HCl gas are supplied into the reactor at a flow rate ratio of (0.6 to 5): 1, thereby inhibiting silicon growth in the chamfered portion. The present invention has been completed by finding that the generation of nodules can be suppressed.

以下、図を参照して、本発明の実施の形態について具体的に説明するが、本発明はこれらに限定されるものではない。
図1は、本発明においてシリコン単結晶膜を気相成長させる際の反応炉内の温度、時間、ガス供給のタイミングの一例を示すグラフである。図3は、本発明の製造方法の実施態様の一例を示すフロー図である。
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. However, the present invention is not limited to these embodiments.
FIG. 1 is a graph showing an example of temperature, time, and gas supply timing in a reactor when vapor-phase-growing a silicon single crystal film in the present invention. FIG. 3 is a flowchart showing an example of an embodiment of the production method of the present invention.

本発明の製造方法では、まず、図3の工程(a)に示すように、シリコン単結晶基板10を準備する。
このとき用意されるシリコン単結晶基板10としては、例えば、チョクラルスキー法によってシリコン単結晶棒を育成し、育成したシリコン単結晶棒を内周刃スライサあるいはワイヤソー等の切断装置によってスライスした後、面取り、ラッピング、エッチング、研磨等の工程を経て作製されたシリコン単結晶基板を用意する。
このように用意されたシリコン単結晶基板10は、後工程でシリコン単結晶膜13が形成される主表面11を有し、その外縁は面取り加工により、例えば、ウェーハ表面側の主表面に続くテーパ面、最外周面、ウェーハ裏面側のテーパ面をへて裏面側の主表面に達するラウンド形状となっている。そして、本発明であれば、例えば、面取りテーパ面の角度が20°未満であるようなノジュールの発生しやすいシリコン単結晶基板についても、ノジュールを効果的に防止することができるため、好適である。
In the manufacturing method of the present invention, first, a silicon single crystal substrate 10 is prepared as shown in step (a) of FIG.
As the silicon single crystal substrate 10 prepared at this time, for example, a silicon single crystal rod is grown by the Czochralski method, and the grown silicon single crystal rod is sliced by a cutting device such as an inner peripheral slicer or a wire saw, A silicon single crystal substrate manufactured through processes such as chamfering, lapping, etching, and polishing is prepared.
The silicon single crystal substrate 10 thus prepared has a main surface 11 on which a silicon single crystal film 13 is formed in a later step, and the outer edge thereof is chamfered by, for example, a taper that continues to the main surface on the wafer surface side. It has a round shape that reaches the main surface on the back side through the surface, the outermost peripheral surface, and the tapered surface on the back side of the wafer. According to the present invention, for example, a nodule can be effectively prevented even for a silicon single crystal substrate in which a nodule is easily generated, for example, the angle of the chamfered tapered surface is less than 20 °. .

次に、図3の工程(b)に示すように、シリコン単結晶基板10のシリコン単結晶膜13を気相成長させる主表面11以外の表面に保護膜12を形成する。
保護膜としては、例えばシリコン酸化膜を形成することができる。
また、形成方法としては、例えば、シリコン単結晶基板を裏返して平板状の板に載せて、表面側の主表面を除く面、即ち裏面側の主表面、面取り部の表面(表面側の面取りテーパ面、裏面側の面取りテーパ面及び最外周面)にシリコン酸化膜からなる保護膜をCVD法により形成する。
即ち、シリコン単結晶基板を裏返して平板状の板に載せて保護膜形成のためのCVDを行うことにより、CVDガスが表面側の面取りテーパ面にまで回り込んで保護膜が形成され、表面側の主表面は、板と接しているため保護膜が形成されない。
Next, as shown in step (b) of FIG. 3, a protective film 12 is formed on a surface other than the main surface 11 on which the silicon single crystal film 13 of the silicon single crystal substrate 10 is vapor-phase grown.
For example, a silicon oxide film can be formed as the protective film.
As a forming method, for example, the silicon single crystal substrate is turned over and placed on a flat plate, and the surface excluding the main surface on the front side, that is, the main surface on the back side, the surface of the chamfered portion (the chamfer taper on the front side) A protective film made of a silicon oxide film is formed by a CVD method on the front surface, the chamfered tapered surface on the back surface side, and the outermost peripheral surface.
That is, the silicon single crystal substrate is turned over and placed on a flat plate to perform CVD for forming a protective film, so that the protective film is formed by the CVD gas wrapping around the chamfered tapered surface on the surface side. Since the main surface is in contact with the plate, a protective film is not formed.

また、このような本発明の保護膜12の形成方法としては、上記の方法以外にも、例えば、シリコン単結晶基板の表裏全面にシリコン酸化膜を形成して、その後基板表面側の主表面上のシリコン酸化膜のみをフッ酸等で除去することができる。
そして、上記のように保護膜12を形成した後に、後工程でシリコン単結晶膜13が形成される基板表面側の主表面11に仕上げ加工を施してもよい。
As a method of forming the protective film 12 of the present invention, in addition to the above method, for example, a silicon oxide film is formed on the entire front and back surfaces of a silicon single crystal substrate, and then the main surface on the substrate surface side is formed. Only the silicon oxide film can be removed with hydrofluoric acid or the like.
Then, after forming the protective film 12 as described above, finishing may be applied to the main surface 11 on the substrate surface side where the silicon single crystal film 13 is formed in a later step.

次に、図3の工程(c)に示すように、気相成長原料ガスとHClガスを同時に流しながら、シリコン単結晶基板10の主表面11上にシリコン単結晶膜13を気相成長させて、シリコンエピタキシャルウェーハ14を製造する。
本発明の気相成長工程において、ガスを流すタイミングとしては、例えば、図1に示すように、まず反応炉内にHガスを流しながら昇温し、成長温度に達してから、キャリアガスで希釈されたTCS(SiHCl)ガス等の気相成長原料ガス及びドープガスを流すと共に、HClガスを同時に流すようにする。この場合、気相成長を開始する前に、シリコン単結晶基板10を反応炉内に載置しない状態で該反応炉内にHClガスを流し、炉内をクリーニングするようにするのが好ましい。
Next, as shown in step (c) of FIG. 3, the silicon single crystal film 13 is vapor grown on the main surface 11 of the silicon single crystal substrate 10 while flowing the vapor growth source gas and the HCl gas simultaneously. A silicon epitaxial wafer 14 is manufactured.
In the vapor phase growth process of the present invention, for example, as shown in FIG. 1, the gas is flowed by first raising the temperature while flowing H 2 gas into the reactor, reaching the growth temperature, and then using the carrier gas. A gas phase growth source gas such as a diluted TCS (SiHCl 3 ) gas and a dope gas are allowed to flow, and an HCl gas is allowed to flow simultaneously. In this case, before starting the vapor phase growth, it is preferable to flow the HCl gas into the reaction furnace without cleaning the silicon single crystal substrate 10 in the reaction furnace to clean the inside of the furnace.

このような、表面側の主表面以外の全面に保護膜が形成された状態の基板上にシリコン単結晶膜を気相成長させることで、基板の裏面のみならず面取り部からのオートドープを効果的に防止することができる。
また、このシリコン単結晶膜の気相成長の際に気相成長原料ガスと共に成長阻害ガスであるHClガスを同時に流すことで、基板の面取り部の保護膜上でのノジュールの核となる微小シリコン粒の形成が抑制されて、ノジュールの発生を簡易な方法で防止することができる。
By vapor-depositing a silicon single crystal film on a substrate in which a protective film is formed on the entire surface other than the main surface on the front side, autodoping is effective not only from the back surface of the substrate but also from the chamfered portion. Can be prevented.
In addition, during the vapor phase growth of the silicon single crystal film, HCl gas, which is a growth inhibition gas, is simultaneously flowed together with the vapor phase growth source gas, so that the minute silicon that becomes the nucleus of nodules on the protective film on the chamfered portion of the substrate The formation of grains can be suppressed and the generation of nodules can be prevented by a simple method.

このように、本発明において、反応炉内のクリーニングに用いられているHClガスを用いることで、特別な配管設備や除外設備を付加することなく、比較的簡便かつ低コストで本発明の製造方法を実施することができる。   Thus, in the present invention, by using the HCl gas used for cleaning in the reactor, the production method of the present invention is relatively simple and low-cost without adding special piping equipment or exclusion equipment. Can be implemented.

このとき、反応炉内に流すHClガスの流量としては、気相成長原料ガスとHClガスを(0.6〜5):1の流量比で同時に流しながら、シリコン単結晶膜13を気相成長させる。
上記のような流量比で気相成長原料ガスとHClガスを流しながら気相成長させることで、確実なノジュールの防止と、良質なシリコン単結晶膜の成長の両方を、効率的に行うことができる。
At this time, the flow rate of HCl gas flowing into the reaction furnace is the vapor growth of the silicon single crystal film 13 while simultaneously flowing the vapor growth source gas and the HCl gas at a flow rate ratio of (0.6 to 5): 1. Let
By performing vapor phase growth while flowing the vapor phase growth source gas and HCl gas at the flow rate ratio as described above, both reliable prevention of nodules and the growth of a good quality silicon single crystal film can be efficiently performed. it can.

このような本発明の製造方法によれば、簡易な方法で、後工程のデバイス製造工程等での不良の原因となるノジュールとオートドープの両方が効果的に防止された、良質なシリコンエピタキシャルウェーハを製造することができる。   According to such a manufacturing method of the present invention, a high-quality silicon epitaxial wafer in which both nodules and auto-doping that cause defects in a subsequent device manufacturing process and the like are effectively prevented by a simple method. Can be manufactured.

また、本発明の製造方法は、シリコン単結晶基板としてSOIウェーハを用いて、そのSOI層上にシリコン単結晶膜を気相成長させて、厚膜SOIウェーハを製造する際にも適用することができる。
SOIウェーハの場合には、表面の外周面にテラスと呼ばれるBOX酸化膜が露出した領域が存在する場合がある。このため、本発明の製造方法によれば、当該テラス部分に露出したBOX酸化膜に発生するノジュールについても防止することができる。
The manufacturing method of the present invention can also be applied to manufacturing a thick film SOI wafer by using a SOI wafer as a silicon single crystal substrate and vapor-depositing a silicon single crystal film on the SOI layer. it can.
In the case of an SOI wafer, there may be a region where a BOX oxide film called a terrace is exposed on the outer peripheral surface of the surface. Therefore, according to the manufacturing method of the present invention, nodules generated in the BOX oxide film exposed at the terrace portion can be prevented.

以下、実施例及び比較例を示して本発明をより具体的に説明するが、本発明はこれらに限定されるものではない。
EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.

(実施例1)
まず、直径150mm、厚さ625μm、面取り部の幅が250μmのシリコン単結晶基板を用意した。
次に、保護膜としてシリコン酸化膜をCVD法により、基板の表面側の主表面以外に形成した。このシリコン酸化膜の膜厚は、基板の裏面側の主表面部分が0.5μmであった。
Example 1
First, a silicon single crystal substrate having a diameter of 150 mm, a thickness of 625 μm, and a chamfered portion having a width of 250 μm was prepared.
Next, a silicon oxide film as a protective film was formed on the surface other than the main surface by the CVD method. The thickness of this silicon oxide film was 0.5 μm on the main surface portion on the back side of the substrate.

次に、エピタキシャル成膜工程では、図1に示すように、反応炉内に基板を載置して、水素雰囲気で1100℃〜1150℃程度にまで昇温し、その後ドープガスと共に、キャリアガスで20%の濃度に希釈した気相成長原料ガスであるTCSを15〜25(l/min)すなわち気相成長原料成分では3〜5(l/min)を、さらにHClガスを1〜5(l/min)同時に流しながら、所定の厚さまでシリコン単結晶膜を気相成長させた後、水素雰囲気にて冷却してシリコンエピタキシャルウェーハを取り出した。
Next, in the epitaxial film forming step, as shown in FIG. 1, the substrate is placed in a reaction furnace, and the temperature is raised to about 1100 ° C. to 1150 ° C. in a hydrogen atmosphere. 15 to 25 (l / min) for the vapor phase growth source gas diluted to a concentration of 3 to 5 (l / min) for the vapor phase growth source component, and 1 to 5 (l / min) for HCl gas. The silicon single crystal film was vapor-phase grown to a predetermined thickness while flowing simultaneously, and then cooled in a hydrogen atmosphere to take out the silicon epitaxial wafer.

(比較例1)
実施例1と同様に、ただし、エピタキシャル成膜工程では、図2に示すように、HClガスを流さないでシリコン単結晶膜を気相成長させて、シリコンエピタキシャルウェーハを製造した。
(Comparative Example 1)
As in Example 1, however, in the epitaxial film forming step, as shown in FIG. 2, a silicon epitaxial wafer was manufactured by vapor-phase growth of a silicon single crystal film without flowing HCl gas.

実施例1及び比較例1で製造したシリコンエピタキシャルウェーハの面取り部(表面側の面取りテーパ面及び最外周縁面)におけるノジュールの有無を走査型電子顕微鏡により観察した。
図4(A)に示すように、実施例1で製造したシリコンエピタキシャルウェーハにはノジュールの発生は見られなかった。一方、図4(B)に示すように、比較例1で製造したシリコンエピタキシャルウェーハにはノジュールの発生が見られた。
以上より、本発明の製造方法であれば、面取り部等に保護膜を形成してシリコン単結晶膜を気相成長させてもノジュールの発生が防止できることがわかる。
The presence or absence of nodules in the chamfered portions (the chamfered tapered surface and the outermost peripheral surface of the surface side) of the silicon epitaxial wafer manufactured in Example 1 and Comparative Example 1 was observed with a scanning electron microscope.
As shown in FIG. 4A, no nodules were observed in the silicon epitaxial wafer manufactured in Example 1. On the other hand, as shown in FIG. 4B, generation of nodules was observed in the silicon epitaxial wafer manufactured in Comparative Example 1.
From the above, it can be seen that the production method of the present invention can prevent the generation of nodules even if a silicon single crystal film is vapor-phase grown by forming a protective film on a chamfered portion or the like.

(実施例2、比較例2)
まず、直径150mm、厚さ625μm、面取り部の幅が250μmのシリコン単結晶基板を用意した。
次に、保護膜としてシリコン酸化膜をCVD法により、基板の表面側の主表面以外に形成した。このシリコン酸化膜の膜厚は、基板の裏面側の主表面部分が0.5μmであった。
(Example 2, comparative example 2)
First, a silicon single crystal substrate having a diameter of 150 mm, a thickness of 625 μm, and a chamfered portion having a width of 250 μm was prepared.
Next, a silicon oxide film as a protective film was formed on the surface other than the main surface by the CVD method. The thickness of this silicon oxide film was 0.5 μm on the main surface portion on the back side of the substrate.

次に、エピタキシャル成膜工程では、図1に示すように、反応炉内に基板を載置して、水素雰囲気で1100℃〜1150℃程度にまで昇温し、その後ドープガスと共に、キャリアガスで20%の濃度に希釈した気相成長原料ガスであるTCSを15(l/min)すなわち気相成長原料成分では3(l/min)を流し、さらに同時に流すHClガスを0〜6(l/min)の間で変更して気相成長原料ガスとHClガスの流量比を変えて、それぞれの流量比で所定の厚さまでシリコン単結晶膜を気相成長させた後、水素雰囲気にて冷却してシリコンエピタキシャルウェーハを取り出した。このシリコンエピタキシャルウェーハのノジュールの発生の有無を表1に示す。   Next, in the epitaxial film forming step, as shown in FIG. 1, the substrate is placed in a reaction furnace, and the temperature is raised to about 1100 ° C. to 1150 ° C. in a hydrogen atmosphere. 15 (l / min) for the vapor phase growth source gas diluted to a concentration of 1 (min / min), that is, 3 (l / min) for the vapor phase growth source component, and 0 to 6 (l / min) for the HCl gas to flow simultaneously. After changing the flow rate ratio between the vapor phase growth source gas and the HCl gas, the silicon single crystal film is vapor grown to a predetermined thickness at each flow rate ratio, and then cooled in a hydrogen atmosphere to form silicon. The epitaxial wafer was taken out. Table 1 shows whether or not nodules are generated in the silicon epitaxial wafer.

Figure 0005273150
Figure 0005273150

表1に示すように、HClガスの流量が6(l/min)(流量比0.5:1)の場合には、HClガス流量が多すぎるため、HClガスによるエッチング作用の方がTCSによる成膜作用より大きくなり、シリコン単結晶膜を成長させることができなかった。また、HClガスの流量が0.5(l/min)(流量比6:1)以下の場合には、HClガス流量が少なすぎてノジュールが発生してしまった。HClガスの流量が0.6〜5(l/min)(流量比0.6〜5:1)の場合には、ノジュールは発生せず、良好なシリコン単結晶膜を成長させることができた。   As shown in Table 1, when the flow rate of HCl gas is 6 (l / min) (flow rate ratio: 0.5: 1), the HCl gas flow rate is too high, so the etching action by HCl gas is due to TCS. It became larger than the film forming action, and the silicon single crystal film could not be grown. Further, when the flow rate of HCl gas was 0.5 (l / min) (flow rate ratio 6: 1) or less, the HCl gas flow rate was too small and nodules were generated. When the flow rate of HCl gas was 0.6 to 5 (l / min) (flow rate ratio 0.6 to 5: 1), nodule was not generated and a good silicon single crystal film could be grown. .

なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は単なる例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。   The present invention is not limited to the above embodiment. The above embodiment is merely an example, and the present invention has the same configuration as that of the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

Claims (1)

シリコン単結晶基板の主表面上にシリコン単結晶膜を気相成長させるシリコンエピタキシャルウェーハの製造方法であって、シリコン単結晶基板のウェーハ表面側の主表面に続くテーパ面、最外周面、ウェーハ裏面側のテーパ面、及びウェーハ裏面に保護膜を形成する工程の後、気相成長原料ガスとHClガスを(0.6〜5):1の流量比で同時に流しながら前記シリコン単結晶基板の主表面上に前記シリコン単結晶膜を気相成長させる工程を有することを特徴とするシリコンエピタキシャルウェーハの製造方法。


A method for producing a silicon epitaxial wafer by vapor-depositing a silicon single crystal film on a main surface of a silicon single crystal substrate , the taper surface following the main surface on the wafer front side of the silicon single crystal substrate , the outermost peripheral surface, and the wafer back surface After the step of forming a protective film on the side taper surface and the back surface of the wafer , the vapor phase growth source gas and HCl gas are simultaneously flown at a flow rate ratio of (0.6 to 5): 1. A method for producing a silicon epitaxial wafer, comprising the step of vapor-phase-growing the silicon single crystal film on a surface.


JP2010530704A 2008-09-26 2009-09-02 Manufacturing method of silicon epitaxial wafer Active JP5273150B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010530704A JP5273150B2 (en) 2008-09-26 2009-09-02 Manufacturing method of silicon epitaxial wafer

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008248302 2008-09-26
JP2008248302 2008-09-26
PCT/JP2009/004325 WO2010035409A1 (en) 2008-09-26 2009-09-02 Process for producing silicon epitaxial wafer
JP2010530704A JP5273150B2 (en) 2008-09-26 2009-09-02 Manufacturing method of silicon epitaxial wafer

Publications (2)

Publication Number Publication Date
JPWO2010035409A1 JPWO2010035409A1 (en) 2012-02-16
JP5273150B2 true JP5273150B2 (en) 2013-08-28

Family

ID=42059423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010530704A Active JP5273150B2 (en) 2008-09-26 2009-09-02 Manufacturing method of silicon epitaxial wafer

Country Status (2)

Country Link
JP (1) JP5273150B2 (en)
WO (1) WO2010035409A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5445075B2 (en) * 2009-11-27 2014-03-19 株式会社Sumco Epitaxial wafer manufacturing method
JP5839343B2 (en) * 2012-11-21 2016-01-06 信越半導体株式会社 Contamination detection method for vapor phase growth apparatus and epitaxial wafer manufacturing method
JP6381229B2 (en) * 2014-02-26 2018-08-29 三菱電機株式会社 Method for manufacturing silicon carbide epitaxial wafer
JP6924593B2 (en) * 2017-03-21 2021-08-25 信越半導体株式会社 Manufacturing method of epitaxial wafer
JP6881283B2 (en) * 2017-12-27 2021-06-02 株式会社Sumco Manufacturing method of epitaxial silicon wafer and epitaxial silicon wafer
CN108428630B (en) * 2018-03-23 2021-01-01 南京国盛电子有限公司 Preparation method of phosphorus-doped silicon epitaxial wafer for 200mm Schottky tube

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248527A (en) * 1988-03-29 1989-10-04 Shin Etsu Handotai Co Ltd Treatment of semiconductor wafer
JPH04245431A (en) * 1991-01-30 1992-09-02 Kyushu Electron Metal Co Ltd Method and apparatus for removal of oxide film from semiconductor substrate
JP2004349405A (en) * 2003-05-21 2004-12-09 Shin Etsu Handotai Co Ltd Surface treatment method, silicon epitaxial wafer and method of manufacturing the same
JP2006120865A (en) * 2004-10-21 2006-05-11 Sumco Corp Method of manufacturing semiconductor substrate, and semiconductor substrate
JP2008522442A (en) * 2004-12-01 2008-06-26 アプライド マテリアルズ インコーポレイテッド Use of Cl2 and / or HCl when forming a silicon epitaxial film

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002231645A (en) * 2001-02-02 2002-08-16 Ngk Insulators Ltd Method of manufacturing nitride semiconductor film

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248527A (en) * 1988-03-29 1989-10-04 Shin Etsu Handotai Co Ltd Treatment of semiconductor wafer
JPH04245431A (en) * 1991-01-30 1992-09-02 Kyushu Electron Metal Co Ltd Method and apparatus for removal of oxide film from semiconductor substrate
JP2004349405A (en) * 2003-05-21 2004-12-09 Shin Etsu Handotai Co Ltd Surface treatment method, silicon epitaxial wafer and method of manufacturing the same
JP2006120865A (en) * 2004-10-21 2006-05-11 Sumco Corp Method of manufacturing semiconductor substrate, and semiconductor substrate
JP2008522442A (en) * 2004-12-01 2008-06-26 アプライド マテリアルズ インコーポレイテッド Use of Cl2 and / or HCl when forming a silicon epitaxial film

Also Published As

Publication number Publication date
WO2010035409A1 (en) 2010-04-01
JPWO2010035409A1 (en) 2012-02-16

Similar Documents

Publication Publication Date Title
JP5719815B2 (en) Manufacturing method of epitaxy coated silicon wafer
US7659207B2 (en) Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafer
KR101968381B1 (en) Method for manufacturing sic single- crystal substrate for epitaxial sic wafer
JP5273150B2 (en) Manufacturing method of silicon epitaxial wafer
JP2007084428A (en) Epitaxial silicon wafer and method for producing epitaxial silicon wafer
US8287649B2 (en) Vertical boat for heat treatment and method for heat treatment of silicon wafer using the same
TWI604094B (en) Semiconductor epitaxial wafer manufacturing method and semiconductor epitaxial wafer
JP5757088B2 (en) Epitaxial wafer manufacturing method, epitaxial wafer
KR101559977B1 (en) Silicon epitaxial wafer and method for manufacturing the same
JP5786759B2 (en) Method for manufacturing epitaxial silicon carbide wafer
JP2006120865A (en) Method of manufacturing semiconductor substrate, and semiconductor substrate
JP2008187020A (en) Susceptor for vapor phase epitaxy and vapor epitaxy growth system, and vapor phase epitaxy method
JP5347791B2 (en) Manufacturing method of semiconductor epitaxial wafer
JP2005064336A (en) Method for manufacturing group iii nitride compound semiconductor substrate
JP2013051348A (en) Epitaxial wafer and method for producing the same
JPH09266212A (en) Silicon wafer
JPH0782997B2 (en) Method for manufacturing semiconductor wafer
JP2013191889A (en) Silicon epitaxial wafer
JP2011187887A (en) Method of manufacturing epitaxial wafer
JP2010021441A (en) Epitaxial substrate wafer
JP2003168636A (en) Method of manufacturing epitaxial wafer
JP2003197547A (en) Method of manufacturing silicon epitaxial wafer
JP6347330B2 (en) Epitaxial wafer manufacturing method
KR101063908B1 (en) Epitaxial wafer manufacturing apparatus and method
JP2023108951A (en) Method for producing silicon epitaxial wafer

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121002

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130115

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130306

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130416

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130429

R150 Certificate of patent or registration of utility model

Ref document number: 5273150

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250