JP2023108951A - Method for producing silicon epitaxial wafer - Google Patents

Abstract

To provide a method for efficiently producing a high quality silicon epitaxial wafer by an improvement in haze (surface roughness) achieved by devising conditions of an epitaxial process for the vapor-phase growth of an epitaxial layer on a main face of a silicon single crystal wafer that uses roughly a (110) plane as the main face.SOLUTION: Provided is a method for producing a silicon epitaxial wafer for the vapor-phase growth of an epitaxial layer on a main face of a silicon single crystal wafer that uses, as the main face, a (110) plane or a plane slanted by an off angle from the (110) plane. When the epitaxial layer is subjected to vapor-phase growth, the temperature of the silicon single crystal wafer is set to 1,095-1,115°C and the growth rate of the epitaxial layer is set to 0.5-1.5 μm/min, or the temperature of the silicon single crystal wafer is set to 1,135-1,155°C and the growth rate of the epitaxial layer is set to 3.0-4.0 μm/min.SELECTED DRAWING: Figure 1

Description

The present invention relates to a method for manufacturing a silicon epitaxial wafer.

At present, most silicon wafers used for semiconductor devices have a {100} plane as a main surface. However, silicon wafers having the {110} plane as the main surface, which has better hole mobility, have recently attracted attention. It is known that a silicon wafer having a {110} plane as a main surface has high carrier mobility and therefore can speed up a pMOS transistor. On the other hand, epitaxial wafers are used for high-performance devices because they have very few surface defects. Therefore, a silicon epitaxial wafer having a {110} plane as a main surface is expected as a material for high-performance devices such as MPU.

However, the silicon epitaxial wafer having the {110} plane as the main surface has the problem that the surface quality such as haze and surface roughness is significantly worse than the silicon wafer having the {100} plane as the main surface. . In addition, due to the deterioration of haze, the background noise on the main surface of the silicon wafer by a particle counter increases, so that it becomes difficult to measure LPD (Light Point Defect), and foreign substances, scratches, etc. on the silicon wafer surface There are some cases where quality assurance cannot be performed. Furthermore, there is a concern that surface roughness (unevenness) on the surface of a silicon wafer may reduce carrier mobility during device fabrication.

As a countermeasure against these problems, it is known to reduce the haze level by homoepitaxially growing on a silicon single crystal substrate having an off-angle tilted in various axial directions (Patent Documents 1 to 8). A method of doping a substrate with a high concentration of carriers to reduce LPD and haze has also been proposed. However, with these methods, the surface haze level is not sufficient.

In addition, there is a proposal to improve the surface roughness by removing unevenness generated on the surface on which the silicon epitaxial layer is formed by polishing. There are drawbacks such as a decrease in productivity and an increase in cost due to deterioration and addition of processes.

JP-A-2001-253797 JP 2007-070131 A JP 2008-091887 A Japanese Patent Application Laid-Open No. 2010-001210 JP 2020-107729 A Japanese Patent Application Laid-Open No. 2020-107730 JP 2012-043892 A JP 2011-243845 A

The present invention has been made to solve the above problems, and the main surface of a silicon single crystal wafer whose main surface is the {110} plane or a plane inclined from the {110} plane by an off angle Another object of the present invention is to provide a method for efficiently manufacturing high-quality silicon epitaxial wafers by improving haze (surface roughness) by devising epitaxial process conditions for vapor phase epitaxial growth of epitaxial layers.

To achieve the above object, the present invention provides a silicon single crystal wafer whose main surface is a {110} plane or a plane inclined from the {110} plane by an off angle, and an epitaxial layer is formed in a vapor phase on the main surface of the silicon single crystal wafer. A method for producing a grown silicon epitaxial wafer, comprising:
When vapor-phase epitaxially growing the epitaxial layer,
The temperature of the silicon single crystal wafer is set to 1095 to 1115° C., and the growth rate of the epitaxial layer is set to 0.5 to 1.5 μm/min, or
A method for producing a silicon epitaxial wafer is provided, characterized in that the temperature of the silicon single crystal wafer is set to 1135 to 1155° C. and the growth rate of the epitaxial layer is set to 3.0 to 4.0 μm/min.

In the method for producing a silicon epitaxial wafer of the present invention, the main surface is the {110} plane or a plane inclined from the {110} plane by an off angle (hereinafter, these planes are collectively referred to as the approximately {110} plane. It is possible to obtain a silicon epitaxial wafer with a reduced haze level in the above method with high efficiency and high productivity. As a result, it is possible to provide high-quality silicon epitaxial wafers with high yield, which retain better carrier mobility than silicon epitaxial wafers having, for example, the {100} plane as the main surface. In addition, an increase in background noise on the main surface of the wafer is suppressed, and wafer quality can be guaranteed without problems. In addition, it is simple and advantageous in terms of cost since it is only necessary to adjust the temperature and growth rate during epitaxial growth.

At this time, as the silicon single crystal wafer, a wafer having a main surface whose off angle from the {110} plane is more than 0 degrees and less than 0.5 degrees can be used.

By doing so, it is possible to obtain a wafer with a lower haze level while suppressing a decrease in carrier mobility as compared with the case of using a wafer having a {110} plane as a principal surface.

By the method for manufacturing a silicon epitaxial wafer of the present invention, an epitaxial layer is vapor-grown on the main surface of a silicon single crystal wafer whose main surface is the {110} plane or a plane inclined from the {110} plane by an off angle. A high-quality silicon epitaxial wafer having a high carrier mobility and a reduced haze level can be manufactured with high productivity.

1 is a flowchart showing an example of a method for manufacturing a silicon epitaxial wafer of the present invention; FIG. 1 is a schematic diagram showing an example of the configuration of a single-wafer vapor phase growth apparatus; FIG. FIG. 4 is a correlation diagram showing the relationship among the growth temperature, growth rate, and haze level in Examples and Comparative Examples.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.
As described above, there has been a demand for a method of manufacturing a silicon epitaxial wafer with a reduced haze level by vapor-phase growing an epitaxial layer on the main surface of a silicon single crystal wafer having a substantially {110} plane as the main surface. . As a result of intensive research conducted by the present inventors, when vapor-phase growth of an epitaxial layer is performed on a silicon single crystal wafer whose main surface is approximately the {110} plane, a predetermined temperature (growth temperature) and growth rate during vapor-phase growth (1095 to 1115° C. and 0.5 to 1.5 μm/min, or 1135 to 1155° C. and 3.0 to 4.0 μm/min), the carrier mobility is high and the haze level is low and good The inventors have found that a silicon epitaxial wafer can be obtained, and completed the present invention.

First, the configuration of a single wafer type vapor phase growth apparatus will be described as a preferred example of the vapor phase growth apparatus used in the method for producing a silicon epitaxial wafer of the present invention. FIG. 2 is an example of a schematic of a single wafer type vapor phase growth apparatus.
As shown in FIG. 2, the vapor phase growth apparatus 1 includes a reaction vessel 2 and a susceptor 3 provided inside the reaction vessel 2 and supporting a silicon single crystal substrate W on its upper surface.
Then, in the reaction vessel 2, a vapor phase growth gas containing a raw material gas (for example, trichlorosilane) and a carrier gas (for example, hydrogen) is introduced into the reaction vessel 2 into the region above the susceptor 3, and the susceptor 3 is A vapor phase growth gas introduction pipe 4 is provided to supply the main surface of the upper silicon single crystal substrate W. As shown in FIG. In addition, a purge gas (for example, hydrogen) is introduced into the reaction vessel 2 into the region below the susceptor 3 on the same side of the reaction vessel 2 where the gas introduction pipe 4 for vapor phase growth is provided. A purge gas introduction pipe 5 is provided.
Further, the gas (vapor-phase growth gas and purge gas) in the reaction vessel 2 is exhausted from the side of the reaction vessel 2 opposite to the side on which the vapor-phase growth gas introduction pipe 4 and the purge gas introduction pipe 5 are provided. An exhaust pipe 6 is provided.

Heating devices 7a and 7b are provided outside the reaction vessel 2 to heat the reaction vessel 2 from above and below. Examples of the heating devices 7a and 7b include halogen lamps.
The susceptor 3 is made of graphite coated with silicon carbide, for example. The susceptor 3 is formed, for example, in the shape of a substantially disk, and has a counterbore 3a, which is a substantially circular recess in plan view, formed on the upper surface thereof for positioning the silicon single crystal substrate W on the upper surface. There is.
A susceptor support member 8 is provided on the lower surface of the susceptor 3 to support the susceptor 3 from the rear surface. The susceptor support member 8 is movable in the vertical direction indicated by arrow A and rotatable in the direction indicated by arrow B. As shown in FIG.

Next, a method for producing a silicon epitaxial wafer according to the present invention will be described. Figure 1 shows the process flow.
<Step 1: Preparation of Silicon Single Crystal Substrate>
First, a silicon single crystal substrate on which an epitaxial layer is to be vapor-grown is prepared.
A silicon single crystal ingot having a <110> principal axis orientation is manufactured by a known method such as the Floating Zone (FZ) method or the Czochralski (CZ) method. Then, the obtained silicon single crystal ingot is cut off at the head and the tail, and then the peripheral portion of the ingot is cut by rotation to accurately obtain the diameter and make the ingot into a complete cylindrical block.
The cylindrical block finished in this way is cut by a slicer such as an inner peripheral cutting machine so that the main surface is either the {110} plane just or a plane inclined by an off angle with respect to the {110} plane (for example, the off angle Slice so that the angle is greater than 0 degrees and less than 0.5 degrees).

After slicing, the outer edges of both surfaces of the silicon single crystal substrate are chamfered by beveling.
The chamfered silicon single crystal substrate is subjected to double-sided lapping using free abrasive grains to obtain a lapped wafer. Alternatively, both sides are ground using a fixed abrasive to obtain a ground wafer.
Both surfaces are then chemically etched by immersing the lapped or ground wafer in an etchant. A chemical etching process is performed to remove a damaged layer generated on the surface of the silicon single crystal substrate by lapping or grinding.
After this chemical etching treatment, the front surface or front and back surfaces are mirror-polished by mechanochemical polishing, and then subjected to final cleaning.

In this way, the main surface is approximately the {110} plane (that is, the {110} plane, or an off-angle from the {110} plane), which has higher carrier mobility than the silicon single crystal substrate having the {100} plane. A silicon single crystal substrate having a surface inclined only
Note that when preparing a silicon single crystal substrate having a main surface inclined by an off angle from the {110} plane, the off angle is not limited, but is particularly prepared to be greater than 0 degrees and less than 0.5 degrees. is preferred. This is because a silicon epitaxial wafer having a further reduced haze level while maintaining high carrier mobility can be obtained in step 3 described later.

<Step 2: Removal of Natural Oxide Film>
Next, a silicon single crystal is grown on the main surface of the silicon single crystal substrate whose main surface is approximately the {110} plane obtained by the above step 1 using, for example, a vapor phase growth apparatus 1 as shown in FIG. The epitaxial layer is vapor deposited.
Specifically, a silicon single crystal substrate W whose main surface is approximately the {110} plane is put into the reaction vessel 2 and placed in the counterbore 3a on the upper surface of the susceptor 3 so that the main surface faces upward. place. Here, hydrogen gas is introduced into the reaction vessel 2 through the vapor phase growth gas introduction pipe 4 and the purge gas introduction pipe 5 from a stage before the silicon single crystal substrate W is introduced.
Next, the silicon single crystal substrate W on the susceptor 3 is heated by the heating devices 7a and 7b, and vapor-phase etching is performed to remove the natural oxide film formed on the main surface of the silicon single crystal substrate W. As shown in FIG. As this temperature, for example, a range of 1050 to 1190° C. is suitable.

<Step 3: Vapor growth of epitaxial layer>
After the vapor phase etching of the natural oxide film in step 2, a silicon single crystal epitaxial layer is grown on the main surface of the silicon single crystal substrate W by vapor phase growth.
At this time, the temperature (growth temperature) of the silicon single crystal substrate W is set to 1095 to 1115° C. (more preferably 1100 to 1110° C.), and the growth rate of the epitaxial layer is set to 0.5 to 1.5 μm/min.
The growth temperature can be adjusted by controlling the heating devices 7a and 7b. In addition, the raw material gas and carrier gas are supplied through the vapor phase growth gas introduction pipe 4, and the purge gas is supplied through the purge gas introduction pipe 5 to the main surface of the silicon single crystal substrate W and the lower side of the susceptor 3 substantially horizontally. do. The growth rate in the above growth temperature range can be adjusted by adjusting the flow rate of the raw material gas or the concentration of the raw material gas in the vapor phase growth gas (including the raw material gas and the carrier gas).
Alternatively, the growth temperature may be 1135 to 1155° C. (more preferably 1140 to 1150° C.) and the epitaxial layer growth rate may be 3.0 to 4.0 μm/min. The method of adjusting the growth temperature and growth rate in this case is also the same as described above.

By performing vapor phase epitaxy while controlling the growth temperature and growth rate within such ranges, silicon epitaxial wafers with a good haze level and small surface roughness can be produced simply and efficiently at low cost. . For example, when the main surface is evaluated in DWO mode (DarkFieldWideOblique) (low angle incidence/low angle detection) using a surface foreign matter inspection device (model Surfscan SP-3) manufactured by KLA, 1.4 ppm , or even lower haze levels can be obtained. Since such a good haze level can be obtained, there is no difficulty in measurement due to an increase in background noise in measurement with a particle counter due to a poor haze level as in the conventional art. Therefore, it is possible to ensure the quality of the wafer more reliably.

The thickness of the silicon single crystal epitaxial layer and the electrical property values such as conductivity type and specific resistivity are not particularly limited, and may be set to desired physical property values. In the vapor phase growth of step 3, a doping gas can be included in the vapor phase growth gas and supplied as necessary.

EXAMPLES The present invention will be described in more detail below with reference to Examples and Comparative Examples of the present invention, but the present invention is not limited to these.
(Examples and Comparative Examples)
As a silicon single crystal substrate for epitaxial growth, a silicon single crystal having a diameter of 300 mm, a resistivity of 8 to 12 Ω·cm, and a thickness of 775 μm, is of P ⁻ type, and has an off-angle of less than 0.5 degrees from the {110} plane. A plurality of substrates (specifically, substrates whose main surfaces are inclined by 0.3 degrees from the (110) plane toward the (001) plane) were prepared. As an epitaxial growth apparatus, a single-wafer type epitaxial growth apparatus for 300 mm diameter (Applied Materials Co.: Centura) having the same configuration as the vapor phase growth apparatus 1 shown in FIG. 2 was prepared.

Trichlorosilane was used as a source gas, and hydrogen was used as a carrier gas. As will be described later, the supply amount of the raw material gas was set to various amounts required for a desired growth rate, and the supply amount of the carrier gas was set to 90 slm. Hydrogen was also selected as the purge gas, and the supply amount was 25 slm. Under these conditions, a silicon single crystal substrate with a thickness of about 2.0 μm was grown at a temperature of 1090 to 1160° C. and a growth rate of 0.5 to 4.5 μm/min. A crystal epitaxial layer was vapor-phase grown on the main surface of the prepared silicon single crystal substrate.
The combinations of the growth temperature and the growth rate in the examples embodying the present invention are 1095 to 1115° C. and 0.5 to 1.5 μm/min, and 1135 to 1155° C. and 3.0 to 4.0 μm/min. It is a combination of min. In this example, the supply amount of the raw material gas was about 1 to 20 slm for both the former and the latter combinations.
Moreover, a comparative example is a combination other than these.

After that, the haze level on the surface of the grown epitaxial layer was evaluated in DWO mode (low angle incidence/low angle detection) using a surface foreign matter inspection device (model Surfscan SP-3) manufactured by KLA ( Unit: ppm). FIG. 3 shows the results (relationship between growth temperature, growth rate, and haze level). The range surrounded by a thick frame is an example.
As shown in FIG. 3, the haze level of all the examples is 1.4 ppm or less compared to the comparative example of 1.5 ppm or more, and it was confirmed that a good haze level can be obtained within the range of the examples.

When the growth temperature is 1095 to 1115° C. and the growth rate is less than 0.5 μm/min, the growth rate is slow and the efficiency is low, which is not effective in terms of productivity.

It should be noted that the present invention is not limited to the above embodiments. The above embodiment is an example, and any device that has substantially the same configuration as the technical idea described in the claims of the present invention and produces similar effects is the present invention. It is included in the technical scope of the invention.

DESCRIPTION OF SYMBOLS 1... Single wafer type vapor phase growth apparatus, 2... Reaction container, 3... Susceptor,
3a... spot facing, 4... gas phase growth gas introduction pipe, 5... purge gas introduction pipe,
6 Exhaust pipe 7a, 7b Heating device 8 Susceptor support member
W: Silicon single crystal substrate.

Claims (2)

A method for producing a silicon epitaxial wafer, wherein an epitaxial layer is vapor-grown on the main surface of a silicon single crystal wafer whose main surface is the {110} plane or a plane inclined from the {110} plane by an off angle, the method comprising:
When vapor-phase epitaxially growing the epitaxial layer,
The temperature of the silicon single crystal wafer is set to 1095 to 1115° C., and the growth rate of the epitaxial layer is set to 0.5 to 1.5 μm/min, or
A method for producing a silicon epitaxial wafer, wherein the temperature of the silicon single crystal wafer is set to 1135 to 1155° C., and the growth rate of the epitaxial layer is set to 3.0 to 4.0 μm/min. 2. The silicon epitaxial wafer according to claim 1, wherein the silicon single crystal wafer is a wafer having a main surface whose off angle from the {110} plane is more than 0 degrees and less than 0.5 degrees. manufacturing method.

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