Classifications

• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/004—Photosensitive materials
  • G03F7/027—Non-macromolecular photopolymerisable compounds having carbon-to-carbon double bonds, e.g. ethylenic compounds
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3157—Partial encapsulation or coating
  • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
  • H01L23/49894—Materials of the insulating layers or coatings
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/5329—Insulating materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/562—Protection against mechanical damage
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to the electrical packaging technology, and more particularly to the thick photosensitive BCB and the wafer level packaging reliability in high-density interconnection packaging.
• BCB Benzocyclobutene
• MCM multi-chip modules
• SiP system in package
• BCB Benzocyclobutene
• BCB is a commonly used polymer resin applied in high-density integration, such as multi-chip modules (MCM) and system in package (SiP). It is characterized by low permittivity, dielectric loss, moisture absorption and cure temperature, high thermal and chemical stability as well as high planarization. Among them, its low permittivity and dielectric loss properties make BCB an excellent multilayer dielectric material. Meanwhile, its great characters such as low cure temperature, low moisture absorption, high corrosion-resistance and good flatness make BCB a commonly used bonding material during wafer bonding process. Furthermore, BCB can also be used in surface passivation process.
• BCB can be divided into two types: dry-etch BCB and photosensitive BCB.
• High aspect- ratio through vias are easy to fabricate using dry-etch BCB. But its respectively high process cost and process complexity are barriers for its further industrial applications.
• the photo-BCB process has advantages like simplified procedure, compatibility to IC process and cost-effective integration.
• BCB is honored by its extraordinary performances in microwave MCM packaging, its thermal coefficient of expansion is too large (42ppm/ ° C) to match with the substrate (e.g. silicon: 3.2ppm/ ° C , lamination: 15-17ppm/ ° C) so that large thermal tensile stress occurs in heating and cooling processes such as baking, bonding and curing. And accordingly, some reliability problems e.g. wafer warpage, film adhesion and cracks can be observed after conventional thick BCB (beyond 20 ⁇ ) process, especially in multiple BCB layer integration. Moreover, BCB layer may drop off in dicing if there are reliability problems, resulting in failures to the multiple integrated modules.
• this invention provides a method for improving or solving the reliability problems such as high thermal tensile stress and BCB stripping.
• thick BCB layering and lithography is conducted.
• the present invention provides a method for improving the reliability in the thick BCB application utilizing BCB lithography by a sequential fabrication process including steps of:
• the process steps are included as follows:
• the first layer of thick photo-BCB is coated on the adhesion film as mentioned. And then the BCB layer is exposed and developed to transfer the patterns to BCB so as to form multiple BCB cells on the first layer of BCB according to the functional modules; and
• the second layer or above layers of thick photo-BCB are deposited on the first layer of BCB as dielectric layers.
• the nth BCB layer includes several separate nth-layer BCB cells, the nth-layer BCB cells is stacked on the (n-l)th-layer BCB cells and the horizontal size of the nth-layer BCB cells is smaller than those of the (n-l)th-layer BCB cells underneath to enable that only the first- layer BCB cells are attached to the substrate.
• the BCB cells on each layer are in the shape of polygon with round edges.
• the substrate includes, but not limited to silicon substrate, ceramic substrate, glass substrate and so on.
• the BCB lithography process as mentioned above is based on single layer module. And the exposed substrate surface after lithography, without being coated by BCB, between the adjacent BCB cells on the same layer can form a trench without BCB which could be used as dicing track during the subsequent dicing process.
• devices could be fabricated on the BCB layers.
• the vias used for inter-layer connection are also formed simultaneously in BCB process.
• the method of BCB fabrication as stated in this invention is to provide the subsequent advantages: the thick BCB layer is divided into separate pieces or cells according to the modules by BCB lithography, which not only reduces the thermal tensile stress in the process of heating and cooling thus reducing wafer warpage, but also reduces or even avoids the influences such as cracks on the adjacent BCB cells.
• the trench without BCB coating after lithography can be used as dicing track in the dicing process to prevent BCB stripping off.
• the method of the present invention improves the reliability effectively without increasing the costs.
• Fig. 1 is the schematic diagram representing the top view of the pattern of the first layer of
• Fig. 2 is the schematic diagram representing the top view of the pattern after the second layer of BCB is coated.
• Fig. 3 is the schematic diagram representing the cross-sectional view of three layers of BCB stacked on the substrate.
• the exemplary processes to be described involve a sequential fabrication to achieve the BCB structure.
• the structure is formed by sequentially adhesion layer deposition, BCB coating, BCB lithography, BCB curing and deep reactive ion etching.
• Fig.1 to Fig 3 illustrates the top-sectional and cross-sectional views, respectively, of an exemplary of BCB multilayer structure.
• a substrate 100 is covered by a layer of adhesion film (not shown).
• the substrate could be made of Si, ceramics, glass and so on.
• the substrate 100 is made of silicon.
• the adhesive film is covered by a photosensitive BCB layer.
• the thickness of the BCB layer could be determined according to the actual requirement. In this embodiment, the thickness of BCB monolayer is 25 um.
• lithography process is conducted on the BCB layer to divide the BCB layer into several separate BCB cells used as dielectric layers in the shape of polygon with round edges by exposure and development until the exposed BCB is removed from the surface of substrate 100.
• the polygon with round edges are round rectangles made by photo- BCB which include the target cell 111 and the peripheral cells 112.
• photo- BCB which include the target cell 111 and the peripheral cells 112.
• a trench is formed by the exposed substrate surface after lithography, without being coated by BCB, located between the target cell 111 and the peripheral cells 112 through photo-BCB lithography and can be used as dicing tracks. Furthermore, vias used for interlay er connection between the devices on BCB cell 111 and the substrate 100 are formed simultaneously with the trenches followed by redistribution.
• the BCB cells including the target cell 111 and the peripheral cells 112 are polygons with round edges without right-angled corners in order to prevent the stress from being concentrated in the corners, which may lead to cracks on BCB films.
• Example 2 BCB multilayer structure as the dielectric layer
• the first photosensitive BCB layer is deposited on the adhesive film and several separate first-layer BCB cells are formed by photolithography process, e.g. the target cell 111 and the peripheral cells 112.
• a second BCB layer is deposited on the surface of the first-layer BCB cell, e.g. the target cell 111 and the peripheral cells 112.
• lithography process is conducted on the second BCB layer to form a second-layer BCB cells, e.g.
• second-layer BCB cells 121 and 122 respectively on the surfaces of the first-layer BCB cells 111 and 112 by exposure and development until the exposed BCB is removed from the surface of substrate 100 (trenches) or the edges of the first-layer BCB cells including the target cell 111 and the peripheral cells 112within a certain distance.
• the second BCB layer could be deposited on the whole substrate surface, or just on the upper surface of the first-layer BCB cells (e.g. cells 111 and 112).
• the second BCB layer is deposited on the whole substrate surface including not only the surface of the first-layer BCB cells, but also the trenches between the first-layer BCB cells.
• the thickness of the second BCB layer is determined by the actual requirement.
• the second BCB layer has a thickness of 20 ⁇ .
• the second-layer BCB cells in the shape of polygon with round edges are formed by exposure and development until the exposed BCB is removed. And specifically, the mentioned polygon with round edges is round rectangles made by photo-BCB.
• the second-layer BCB cells e.g. 121 and 122 are respectively stacked on the first-layer BCB cells (e.g. Ill and 112) where the horizontal size of the second-layer BCB cells is smaller than those of the respective first layer cells.
• the horizontal size of the BCB cell 121 is smaller than that of the BCB cell 111, and the horizontal size of the BCB cell 122 is smaller than that of the BCB cell 112.
• the dielectric layer is composed of the first-layer cells and the second-layer cells.
• the second-layer BCB cells (e.g. 121 and 122) is respectively stacked on the first-layer BCB cells (e.g. Ill and 112) where the horizontal size of the second-layer cell is smaller than those of the respective first-layer cell underneath after second BCB layer lithography to prevent the second-layer BCB cells from stacking on the edges of the first-layer BCB cells or contacting the substrate which could result in reliability issues due to thermal tensile stress.
• the trench without BCB is located between the first-layer target cell 111 and the first- layer peripheral cells 112 as well as between the second- layer BCB target cell 121 and the second- layer BCB peripheral cells 122.
• the horizontal size of the second-layer BCB cells is smaller than those of the first-layer BCB cells, there is no intersection between the trench and edges of the second-layer BCB cells, such as the target cell 121 and the peripheral cells 122.
• the trench without BCB which could be used as dicing track, is the same for the multiple BCB layers in this embodiment.
• the initial second BCB layer is deposited on the whole wafer substrate surface including the substrate 100, the target cell 111, the peripheral cells 112 and any other structure fabricated on the first layer of BCB, for example, the devices and redistributions are fabricated on the first-layer BCB cells.
• the second-layer BCB cells (such as the second-layer target cell 121 and the second-layer peripheral cells 122), which are not attached directly to the substrate 100, are formed by BCB lithography process.
• the trench located between the target cell 121 and the peripheral cells 122 is formed by photo-BCB lithography and can be used as dicing track. Furthermore, vias used for interlayer connection between the devices on the BCB cell 121 and the BCB cell 111 are formed simultaneously with the trenches followed by redistribution.
• the BCB cells including the target cell 121 and the peripheral cells 122 are polygons with round edges without right-angled corners in prevent the stress from being concentrated in the corners, which may lead to cracks on BCB films.
• the shape of the BCB cells on both the first and second layers are polygon with round edges and not limited to round rectangle shown in Fig.2.
• the horizontal size of the second-layer BCB cells is smaller than those of the first-layer BCB cells to prevent the second-layer BCB cells from contacting with the substrate surface
• the shape of each layer could be same or different.
• the first-layer BCB cells are in the shape of round rectangle, but the second-layer BCB cells are in the shape of other polygons with round edges rather than rectangle.
• the BCB thickness of the second layer are not determined by that of the first layer, i.e. it is adaptable that the BCB thickness of the second layer equals or doesn't equal to that of the first layer.
• the thickness of the second BCB layer is not limited to 20 ⁇ in the exemplary structure.
• the number of BCB layers is not limited to 2 in this exemplary structure. As shown in Fig.3, three or more than three layers of BCB can be fabricated using the same preparation methods in the first and second layers of BCB, which is determined by the maximum thickness of BCB deposited.
• the dielectric layer is composed of the first- layer cells, the second-layer cells and the third-layer cells.
• the number of BCB layers could be four or above.
• the maximum thickness varies from different types of BCB. In details, the maximum thickness of the thick photo-BCB in this exemplary structure is 50 ⁇ . If the thickness of the first and second layers of BCB is 20 ⁇ , a 20 ⁇ thick BCB cannot be fabricated as the third layer with standard and reliable process.
• each layer of BCB is reduced to 15 ⁇ , maximum three layers of BCB can be fabricated.
• the horizontal size of each upper layer of BCB cells is smaller than those on the underlying layers to guarantee that only the first layer of BCB is attached to the substrate directly and to prevent upper layer BCB cells from stacking on the edges of its underlying layer BCB cells or contacting the substrate which could result in reliability issues due to the thermal tensile stress.
• thick BCB on each layer is divided into pieces or cells according to the modules by BCB lithography, which not only reduces the thermal tensile stress in the process of heating and cooling so that the warpage of the wafer is improved, but also reduces or even avoids the influences such as cracks from the adjacent cells.
• the trench without BCB after lithography can be used as a dicing track in the dicing process in case of BCB stripping off. This invention improves the reliability effectively without raising the costs.

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Spectroscopy & Molecular Physics (AREA)
• Manufacturing & Machinery (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Materials For Photolithography (AREA)
• Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

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• 2012
  • 2012-01-17 CN CN201210013248.2A patent/CN103203925B/zh not_active Expired - Fee Related
  • 2012-06-14 WO PCT/CN2012/076873 patent/WO2013107148A1/en active Application Filing

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