WO2013082827A1 - Tft阵列基板的制作方法及tft阵列基板 - Google Patents

Tft阵列基板的制作方法及tft阵列基板 Download PDF

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WO2013082827A1
WO2013082827A1 PCT/CN2011/083871 CN2011083871W WO2013082827A1 WO 2013082827 A1 WO2013082827 A1 WO 2013082827A1 CN 2011083871 W CN2011083871 W CN 2011083871W WO 2013082827 A1 WO2013082827 A1 WO 2013082827A1
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storage capacitor
metal
layer
metal film
film layer
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French (fr)
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覃事建
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/380,900 priority Critical patent/US20130146876A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks

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  • the present invention relates to the field of liquid crystal display, and in particular to a method for fabricating a TFT array substrate and a TFT array substrate.
  • TFT liquid crystal displays have been widely used and received more and more attention, and the display quality requirements of TFT liquid crystal displays are also increasing.
  • TFT liquid crystal display array substrates are usually manufactured using 5Mask technology, including gate electrode lithography (Gate Mask), Active Mask, S/D Mask, Via Hole Mask, and Pixel Mask) 5Mask technology, and each of the Mask process steps include one or more thin film deposition processes and etching processes, respectively, forming five cycles of thin film deposition ⁇ photolithography ⁇ etching.
  • the conventional 5Mask technology is used to fabricate the TFT liquid crystal display array substrate, and during the exposure process, the TFT switching device is not protected, so that it is susceptible to strong light, thereby reducing the stability of the TFT switching device;
  • the capacitance value is to be increased, the area of the storage capacitor needs to be increased, which causes the aperture ratio of the corresponding pixel to decrease.
  • the main object of the present invention is to provide a method for fabricating a TFT array substrate, which is formed by forming a light-blocking metal on the substrate to protect the TFT switching device from being affected by strong light, thereby improving the stability of the TFT switching device.
  • the invention provides a method for fabricating a TFT array substrate, comprising:
  • the first metal film layer is subjected to a glue exposure and development process, and is etched and stripped to form a lower electrode of the first storage capacitor.
  • the method for fabricating the TFT array substrate further includes:
  • a first insulating layer is deposited on the substrate including the light blocking metal, and the first insulating layer is SiNx.
  • the method for fabricating the TFT array substrate further includes:
  • the method further includes:
  • an ohmic contact layer on the second metal film layer, and performing a glue exposure and development process on the ohmic contact layer, and etching and stripping to obtain source and drain metals of the signal line and the gate electrode.
  • An ohmic contact layer is attached over the signal line, the source drain metal, and the upper electrode of the first storage capacitor.
  • the method further includes:
  • the method further includes:
  • the ITO film is connected to the drain metal of the gate electrode through the via hole 1 to form a pixel electrode; and the ITO film is formed by the through hole 2 and the metal constituting the lower electrode of the first storage capacitor.
  • the upper electrode of the second storage capacitor is
  • the upper electrode of the first storage capacitor is used as a lower electrode of the second storage capacitor, and the first storage capacitor and the second storage capacitor are connected in parallel to form a storage capacitor of the pixel.
  • the invention also provides a method for fabricating a TFT array substrate, comprising:
  • the first metal film layer is subjected to a glue exposure and development process, and is etched and stripped to obtain a light blocking metal.
  • the method further comprises:
  • the first metal film layer is subjected to a glue exposure and development process, and is etched and stripped to form a lower electrode of the first storage capacitor.
  • the method for fabricating the TFT array substrate further includes:
  • the upper electrode of the first storage capacitor is used as a lower electrode of the second storage capacitor, and the first storage capacitor and the second storage capacitor are connected in parallel to form a storage capacitor of the pixel.
  • the method for fabricating the TFT array substrate further includes:
  • a first insulating layer is deposited on the substrate including the light blocking metal, and the first insulating layer is SiNx.
  • the present invention further provides a TFT array substrate comprising a glass substrate and a first insulating layer, further comprising a light blocking metal formed on the glass substrate, the light blocking metal passing through a first layer deposited on the glass substrate
  • the metal film layer is subjected to a glue exposure and development process, and is obtained by etching and degumming.
  • the method further includes: performing a glue exposure development process on the first metal film layer, and etching and de-gleasing to form a lower electrode of the first storage capacitor on the glass substrate.
  • the upper electrode of the first storage capacitor being formed by a second metal film layer deposited on the first insulating layer
  • the glue is exposed and developed, and is obtained by etching and degumming.
  • the upper electrode of the first storage capacitor serves as a lower electrode of the second storage capacitor, and the first storage capacitor and the second storage capacitor are connected in parallel to form a storage capacitor of the pixel.
  • the area of the metal constituting the upper electrode of the first storage capacitor is smaller than the area of the metal constituting the lower electrode of the first storage capacitor.
  • a TFT array substrate is fabricated by a 4Mask method, and first, a process of performing a glue exposure development on a first metal film layer deposited on a cleaned glass substrate is passed through A method of etching and removing glue can obtain a layer of light-blocking metal on the glass substrate. Through this layer of light-blocking metal, the TFT switching device can be well protected in the subsequent process, so that the problem of reduced stability due to exposure to strong light can be avoided.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a TFT array substrate according to the present invention
  • FIG. 2 is a schematic flow chart of a second embodiment of a method for fabricating a TFT array substrate according to the present invention
  • FIG. 3 is a schematic structural diagram of a process of forming a light-shielding metal and a lower electrode of a first storage capacitor on a glass substrate in an embodiment of a TFT array substrate according to the present invention
  • FIG. 4 is a schematic structural diagram of a process after forming an upper electrode of a first storage capacitor on the basis of FIG. 3;
  • FIG. 5 is a schematic view showing a process structure after etching an ohmic contact layer and forming a gate electrode on the basis of FIG. 4;
  • FIG. 6 is a schematic view showing the process structure after forming the upper electrode of the second storage capacitor on the basis of FIG. 5.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a TFT array substrate according to the present invention.
  • a method for fabricating a TFT array substrate includes:
  • Step S1 depositing a first metal film layer on the substrate
  • the glass substrate is first cleaned.
  • the first metal film layer may be deposited on the glass substrate by vacuum sputtering, and the deposited metal film layer may be Mo. Al or other opaque metal.
  • step S2 the first metal film layer is subjected to a glue exposure and development process, and after etching and degumming, a light blocking metal is obtained.
  • the formed light-blocking metal can be used to protect the TFT switching device. In the subsequent photolithography process, the TFT switching device is not exposed to strong light and affects the stability of the TFT switching device.
  • the method further includes:
  • Step S3 depositing a first insulating layer on the substrate including the light blocking metal, the first insulating layer being SiNx.
  • the first metal film layer is subjected to a step of coating exposure development and etching and de-glue, and a light-blocking metal is obtained, PECVD (Plasma) is used on the substrate containing the light-blocking metal.
  • PECVD Plasma enhanced chemical vapor deposition method
  • depositing a first insulating layer to facilitate the next photolithography step the first insulating layer may be SiNx.
  • the TFT array substrate is fabricated by a 4Mask method, and the first metal film layer deposited on the cleaned glass substrate is subjected to a process of coating and exposing and developing, and is formed on the glass substrate by etching and removing the glue.
  • Forming a layer of light-blocking metal, using this layer of light-blocking metal, can protect the TFT switching device in the subsequent process, so as to avoid the stability reduction caused by the exposure of strong light. The problem.
  • the method for fabricating the TFT array substrate further includes:
  • step S2.1 the lower electrode of the first storage capacitor is formed while forming the light-blocking metal on the substrate.
  • the same method can be used to perform the process of coating and exposing the first metal film deposited on the glass substrate, and also by wet etching to leave on the glass substrate.
  • the first metal film layer is etched and stripped so that the lower electrode of the first storage capacitor can be formed on the substrate.
  • FIG. 2 is a schematic flow chart of a second embodiment of a method for fabricating a TFT array substrate according to the present invention.
  • the method for fabricating the TFT array substrate may further include:
  • Step S4 depositing a second metal film layer on the substrate including the light-shielding metal and the lower electrode of the first storage capacitor, performing a glue exposure development process on the second metal film layer, and etching and removing the glue.
  • the upper electrode of the first storage capacitor is obtained.
  • a layer of a first insulating layer deposited on the substrate deposited on the substrate including the light-blocking metal and the first storage capacitor may be deposited by vacuum sputtering.
  • a second metal film layer, and then, an ohmic contact layer may be deposited on the second metal film layer by a PECVD method, and the second metal film layer and the ohmic contact layer are subjected to a process of coating exposure development, where The second metal film layer and the ohmic contact layer are directly etched without first removing the pattern left by the development.
  • the ohmic contact layer may be firstly dried by etching.
  • the etching is performed, and the second metal film layer is etched by wet etching, and then the step of removing the glue is performed.
  • the upper electrode of the first storage capacitor can be obtained; the source and drain metals of the signal line and the gate electrode can be simultaneously formed by the same method as the upper electrode for obtaining the first storage capacitor, and the signal line, the source drain metal An ohmic contact layer is attached to the upper electrode of the first storage capacitor.
  • a semiconductor layer is deposited by a PECVD method on the ohmic contact layer attached to the signal line, the source/drain metal, and the upper electrode of the first storage capacitor, and the semiconductor layer is deposited on the semiconductor layer A second insulating layer is deposited on the top.
  • the semiconductor layer may be a-Si
  • the second insulating layer may be SiNx.
  • a third metal film layer is deposited by vacuum sputtering on the second insulating layer; and the third metal film layer, the semiconductor layer and the second insulating layer are subjected to a coating exposure development process, in this embodiment.
  • the third metal film layer may be etched by wet etching, and then the semiconductor layer and the second insulating layer are etched by dry etching, and finally the step of removing the glue is performed. .
  • this step a portion of the ohmic contact layer attached to the drain metal of the gate electrode and the ohmic contact layer attached to the upper electrode of the first storage capacitor are simultaneously etched away.
  • a protective layer is deposited by PECVD and the protection is applied The layer is subjected to a process of coating and exposing and developing. In this step, the exposure used is a half exposure, and a semi-exposure cover is required, and after being subjected to the adhesive exposure and development, it is etched on the protective layer by dry etching.
  • the upper electrode of the first storage capacitor can be used as the lower electrode of the second storage capacitor, and the lower electrode of the second storage capacitor and the ITO film are formed by the metal connection of the through hole 2 and the lower electrode of the first storage capacitor.
  • the upper electrodes of the second storage capacitors together form a second storage capacitor. In this way, the first storage capacitor and the second storage capacitor can realize the parallel connection therebetween, thereby jointly forming the storage capacitance of the pixel.
  • the upper electrode of the first storage capacitor is used as the lower electrode of the second storage capacitor.
  • the ITO film is connected to the metal constituting the lower electrode of the first storage capacitor through the through hole 2, the upper electrode of the second storage capacitor is formed.
  • the first storage capacitor and the second storage capacitor can be connected in parallel.
  • FIG. 3 is a schematic structural view of a TFT array substrate according to an embodiment of the present invention, in which a light blocking metal and a lower electrode of a first storage capacitor are formed on a glass substrate.
  • the TFT array substrate including the glass substrate 10 and the first insulating layer 20, further includes a light blocking metal formed on the glass substrate 10, and the light blocking metal 70 may pass through the first deposited on the glass substrate 10.
  • a metal film layer is subjected to a glue exposure and development process, and is obtained by etching and degumming.
  • the first metal film layer deposited on the glass substrate 10 is subjected to a process of coating and exposing and developing, and the first metal film layer left on the glass substrate 10 after being subjected to the adhesive exposure and development by wet etching
  • a layer of light blocking metal 70 can be obtained by etching and stripping.
  • the formed light-blocking metal 70 can be used to protect the TFT switching device. In the subsequent photolithography process, the TFT switching device is not exposed to strong light to affect the stability of the TFT switching device.
  • the first insulating layer 20 is a step of performing the adhesive exposure development and etching and de-glue on the first metal film layer, and after the light-blocking metal 70 is obtained, the light-shielding metal 70 is included.
  • PECVD on the substrate Pasma Enhanced Chemical Vapor Deposition
  • the first insulating layer 20 is deposited by the method of plasma enhanced chemical vapor deposition, which facilitates the next photolithography step, and the first insulating layer used may be SiNx.
  • the TFT array substrate is fabricated by a 4Mask method, and the first metal film layer deposited on the cleaned glass substrate 10 is subjected to a process of coating and exposing and developing, and the glass substrate is etched and removed by a method.
  • Forming a layer of light-blocking metal 70, using this layer of light-blocking metal 70, can protect the TFT switching device in the subsequent process, thereby avoiding the exposure of the light due to strong light. The problem of reduced stability.
  • the TFT array substrate further includes a lower electrode 81 of the first storage capacitor formed on the glass substrate 10 when the light blocking metal 70 is formed, and the lower electrode 81 and the light blocking metal 70 of the first storage capacitor It can be obtained by the same method. While the light-blocking metal 70 is formed, the first metal film layer deposited on the glass substrate 10 can be subjected to a process of coating exposure development by the same method, and the same manner is applied to the glass substrate 10 by wet etching. The remaining first metal film layer is etched and de-glue, so that the lower electrode 81 of the first storage capacitor can be obtained.
  • FIG. 4 is a schematic structural diagram of a process after forming an upper electrode of a first storage capacitor on the basis of FIG.
  • the TFT array substrate further includes an upper electrode 82 of the first storage capacitor formed on the first insulating layer 20, and the upper electrode 82 of the first storage capacitor passes through the second layer deposited on the first insulating layer 20.
  • the metal film layer is subjected to a glue exposure and development process, and is obtained by etching and degumming.
  • the first insulating layer deposited on the substrate of the lower electrode 81 including the light-blocking metal 70 and the first storage capacitor may be vacuum-sputtered.
  • the process here, does not remove the pattern left by the development, but directly etches the second metal film layer and the ohmic contact layer 30.
  • dry etching can be used first.
  • the ohmic contact layer 30 is etched, and the second metal film layer is etched by wet etching, and then the step of removing the glue is performed.
  • the upper electrode 82 of the first storage capacitor can be obtained.
  • the area of the metal of the upper electrode 82 of the first storage capacitor obtained is smaller than the area of the metal constituting the lower electrode 81 of the first storage capacitor. .
  • the signal line, the source metal 41 and the drain metal 42 can be formed at the same time as in the same manner as the upper electrode 82 from which the first storage capacitor is obtained, and at the signal line, the source metal 41 and the drain metal 42, and the first An ohmic contact layer 30 is attached over the upper electrode 82 of the storage capacitor.
  • FIG. 5 is a structural schematic view of the ohmic contact layer and the shaped gate electrode after etching away on the basis of FIG.
  • a semiconductor layer 50 is deposited by the PECVD method on the ohmic contact layer 30 attached to the signal line, the source metal 41 and the drain metal 42, and the upper electrode 82 of the first storage capacitor.
  • a second insulating layer 60 is deposited over the semiconductor layer 50.
  • the semiconductor layer 50 may be a-Si
  • the second insulating layer 60 may be SiNx
  • a vacuum splash is applied over the second insulating layer 60.
  • a method of depositing a third metal film layer; and performing a process of coating and exposing the third metal film layer, the semiconductor layer 50 and the second insulating layer 60, in this embodiment, the wet etching may be performed first.
  • the third metal film layer is etched, and the semiconductor layer 50 and the second insulating layer 60 are etched by dry etching, and finally the step of removing the glue is performed.
  • the step of removing the glue is performed.
  • a portion of the ohmic contact layer 30 attached to the drain metal 42 and the ohmic contact layer 30 attached to the upper electrode 82 of the first storage capacitor are simultaneously etched away, and the gate electrode 40 is formed.
  • FIG. 6 is a schematic structural diagram of a process after forming an upper electrode of a second storage capacitor on the basis of FIG. 5.
  • a portion of the ohmic contact layer 30 attached to the drain metal 42 of the gate electrode 40 and the ohmic contact layer 30 attached to the upper electrode 82 of the first storage capacitor are etched away, and a gate is formed.
  • a protective layer is deposited on the glass substrate 10 by the PECVD method, and the protective layer is subjected to a coating exposure development process. In this step, the exposure is used. It is half exposure and requires a half exposure cover.
  • two through holes namely, the through holes 1 and the through holes 2 are etched on the protective layer by dry etching, and then the protective layers of the through holes 1 and the through holes 2 are etched.
  • An ITO film 90 is deposited by vacuum sputtering, and the upper electrode of the second storage capacitor and the pixel ITO electrode are finally formed.
  • the ITO film 90 is connected to the drain metal 42 of the gate electrode 40 through the via 1 to form the pixel electrode; and at the same time, the ITO film passes through the via 2
  • the upper electrode of the second storage capacitor can be formed by being connected to the metal constituting the first storage capacitor lower electrode 81.
  • the upper electrode 82 of the first storage capacitor can be used as the lower electrode of the second storage capacitor, and the lower electrode of the second storage capacitor and the metal of the ITO film 90 pass through the through hole 2 and the first storage capacitor lower electrode 81.
  • the upper electrodes connecting the formed second storage capacitors together constitute a second storage capacitor. In this way, the first storage capacitor and the second storage capacitor realize a parallel connection therebetween, thereby collectively constituting a storage capacitor of the pixel.
  • the upper electrode 82 of the first storage capacitor is used as the lower electrode of the second storage capacitor.
  • the ITO film 90 is connected to the metal constituting the first storage capacitor lower electrode 81 through the through hole 2, the second storage capacitor is formed.
  • the electrode in this way, the first storage capacitor and the second storage capacitor can be connected in parallel.

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Abstract

一种TFT阵列基板的制作方法及TFT阵列基板。该TFT阵列基板的制作方法包括：在基板（10）上沉积第一金属膜层；对第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到挡光金属（70）；对第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，成形第一存储电容的下电极（81）。该TFT阵列基板的制作方法通过在基板（10）上成形挡光金属（70）实现对TFT开关器件的保护，使其不受强光影响，提高TFT开关器件的稳定性；并且通过电容的并联来减小存储电容的面积，从而实现增大相应像素的开口率的目的。

Description

TFT阵列基板的制作方法及TFT阵列基板
技术领域
本发明涉及到液晶显示领域，特别涉及到一种TFT阵列基板的制作方法及TFT阵列基板。
背景技术
TFT液晶显示器在广泛应用并受到人们越来越多的关注的同时，对TFT液晶显示器的显示质量的要求也越来越高。目前，TFT液晶显示器阵列基板的制造通常采用5Mask技术，包括栅电极光刻（Gate Mask）、有源层光刻（Active Mask）、源漏极光刻（S/D Mask）、过孔光刻（Via Hole Mask）以及像素电极层光刻（Pixel Mask）的5Mask的技术，并且在每一个Mask工艺步骤中又分别包括一次或多次薄膜沉积工艺和刻蚀工艺，成形了5次薄膜沉积→光刻→刻蚀的循环过程。然而，采用这种传统的5Mask技术来制造TFT液晶显示器阵列基板，在曝光的过程中，没有对TFT开关器件进行保护，使其容易受到强光的影响，从而降低TFT开关器件的稳定性；并且，现有的存储电容，如要增大电容值时，需要增大存储电容的面积，这样便会导致相应像素的开口率减小。
发明内容
本发明的主要目的为提供一种TFT阵列基板的制作方法，通过在基板上成形挡光金属实现对TFT开关器件的保护，使其不受强光影响，提高TFT开关器件的稳定性。
本发明提供一种TFT阵列基板的制作方法，包括：
在基板上沉积第一金属膜层；
对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到挡光金属；
对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，成形第一存储电容的下电极。
优选地，TFT阵列基板的制作方法还包括：
在包含有所述挡光金属的基板上沉积第一绝缘层，该第一绝缘层为SiNx。
优选地，TFT阵列基板的制作方法还包括：
在包含有所述挡光金属和第一存储电容的下电极的基板上沉积第二金属膜层，对第二金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到第一存储电容的上电极。
优选地，在得到第一存储电容的上电极之后，还包括：
在所述第二金属膜层上沉积一层欧姆接触层，并对所述欧姆接触层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到信号线和栅电极的源、漏极金属；在所述信号线、源漏极金属和第一存储电容的上电极的上方都附有一层欧姆接触层。
优选地，在得到信号线和栅电极的源、漏极金属之后，还包括：
在附在所述信号线、源漏极金属和第一存储电容的上电极上方的欧姆接触层上，依次沉积半导体层、第二绝缘层和第三金属膜层；
对所述半导体层、第二绝缘层和第三金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，附在所述栅电极漏极金属上的一部分欧姆接触层和附在第一存储电容的上电极上的欧姆接触层同时被刻蚀掉。
优选地，当附在所述栅电极漏极金属上的一部分欧姆接触层和附在第一存储电容的上电极上的欧姆接触层同时被刻蚀掉之后，还包括：
沉积一层保护层，对保护层进行涂胶曝光显影的制程，并在所述保护层上蚀刻出通孔1和通孔2；
在所述保护层上沉积一层ITO膜，所述ITO膜通过通孔1与栅电极的漏极金属连接形成像素电极；ITO膜通过通孔2与构成第一存储电容下电极的金属连接形成第二存储电容的上电极。
优选地，将所述第一存储电容的上电极作为第二存储电容的下电极，并将所述第一存储电容和所述第二存储电容并联连接共同构成像素的存储电容。
本发明还提供一种TFT阵列基板的制作方法，包括：
在基板上沉积第一金属膜层；
对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到挡光金属。
优选地，在执行所述对第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到挡光金属之后还包括：
对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，成形第一存储电容的下电极。
优选地，TFT阵列基板的制作方法还包括：
在包含有所述挡光金属和第一存储电容的下电极的基板上沉积第二金属膜层，对第二金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到第一存储电容的上电极。
优选地，将所述第一存储电容的上电极作为第二存储电容的下电极，并将所述第一存储电容和所述第二存储电容并联连接共同构成像素的存储电容。
优选地，TFT阵列基板的制作方法还包括：
在包含有所述挡光金属的基板上沉积第一绝缘层，该第一绝缘层为SiNx。
本发明进一步提供一种TFT阵列基板，包括玻璃基板和第一绝缘层，还包括成形于所述玻璃基板上的挡光金属，所述挡光金属通过对沉积在所述玻璃基板上的第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶的方法得到。
优选地，还包括对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶而成形于所述玻璃基板上的第一存储电容的下电极。
优选地，还包括成形于所述第一绝缘层上的第一存储电容的上电极，所述第一存储电容的上电极通过对沉积在所述第一绝缘层上的第二金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶得到。
优选地，所述第一存储电容的上电极作为第二存储电容的下电极，所述第一存储电容和所述第二存储电容为并联连接，共同构成像素的存储电容。
优选地，构成所述第一存储电容上电极的金属的面积小于构成所述第一存储电容下电极的金属的面积。
本发明所提供的一种TFT阵列基板的制作方法，通过4Mask的方式来制作TFT阵列基板，首先对沉积在经过清洗的玻璃基板上的第一金属膜层进行涂胶曝光显影的制程，并通过蚀刻以及去胶的方法，可以在玻璃基板上得到一层挡光金属。通过这一层挡光金属，可以在之后的制程中，对TFT开关器件起到很好的保护作用，从而可以避免其由于受到强光的照射而导致的稳定性降低的问题。并且将第一存储电容和第二存储电容并联连接，采用这种连接的方式，在需要增大存储电容的电容值时，可以同时保证存储电容的面积的减小，这样，便可以在很大程度上提高相应像素的开口率。
附图说明
图1为本发明TFT阵列基板的制作方法第一实施例的流程示意图；
图2为本发明TFT阵列基板的制作方法第二实施例的流程示意图；
图3为本发明TFT阵列基板实施例中在玻璃基板上成形挡光金属和第一存储电容的下电极后的工艺结构示意图；
图4为在图3的基础上成形第一存储电容的上电极后的工艺结构示意图；
图5为在图4的基础上刻蚀掉欧姆接触层以及成形栅电极后的工艺结构示意图；
图6为在图5的基础上成形第二存储电容的上电极后的工艺结构示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
参照图1，图1为本发明TFT阵列基板的制作方法第一实施例的流程示意图。
在本实施例中，TFT阵列基板的制作方法，包括：
步骤S1，在基板上沉积第一金属膜层；
在沉积第一金属膜层前，首先要对玻璃基板进行清洗，本实施例中，可以采用真空溅射的方法在玻璃基板上沉积第一金属膜层，所沉积的金属膜层可以为Mo、Al或其他不透明的金属。
步骤S2，对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到挡光金属。
对沉积在玻璃基板上的第一金属膜层进行涂胶曝光显影的制程，并且采用湿法刻蚀的方式对经过涂胶曝光显影后，对玻璃基板上留下的第一金属膜层进行蚀刻及去胶，便可以得到一层挡光金属。所成形的挡光金属可以用于对TFT开关器件进行保护，在之后的光刻过程中，使TFT开关器件不会受到强光的照射而影响该TFT开关器件的稳定性。
在本实施例中，得到挡光金属后，还包括：
步骤S3，在包含有所述挡光金属的基板上沉积第一绝缘层，该第一绝缘层为SiNx。
在对第一金属膜层进行了涂胶曝光显影以及刻蚀和去胶的步骤，并得到挡光金属后，在包含有该挡光金属的基板上采用PECVD（Plasma Enhanced Chemical Vapor Deposition ，等离子体增强化学气相沉积法）的方法沉积一层第一绝缘层，以便于进行下一步的光刻步骤，该第一绝缘层可以为SiNx。
本发明实施例，通过4Mask的方式来制作TFT阵列基板，对沉积在经过清洗的玻璃基板上的第一金属膜层进行涂胶曝光显影的制程，并通过蚀刻以及去胶的方法在玻璃基板上成形一层挡光金属，采用这一层挡光金属，可以在之后的制程中，对TFT开关器件起到很好的保护作用，从而可以避免其由于受到强光的照射而导致的稳定性降低的问题。
在本实施例中，TFT阵列基板的制作方法，在执行步骤S2之后，还包括：
步骤S2.1，在基板上成形所述挡光金属的同时，成形第一存储电容的下电极。
在成形挡光金属的同时，可以采用同样的方法，对沉积在玻璃基板上的第一金属膜层进行涂胶曝光显影的制程，并且同样采用湿法刻蚀的方式对玻璃基板上所留下的第一金属膜层进行蚀刻及去胶，从而在基板上可以成形第一存储电容的下电极。
参照图2，图2为本发明TFT阵列基板的制作方法第二实施例的流程示意图。
相较于第一实施例，在本实施例中，TFT阵列基板的制作方法还可包括：
步骤S4，在包含有所述挡光金属和第一存储电容的下电极的基板上沉积第二金属膜层，对第二金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到第一存储电容的上电极。
当得到挡光金属和第一存储电容的下电极后，可以采用真空溅射的方法在沉积在包含有挡光金属和第一存储电容的下电极的基板上的第一绝缘层上沉积一层第二金属膜层，然后，可以采用PECVD的方法在该第二金属膜层上沉积一层欧姆接触层，并对第二金属膜层和欧姆接触层进行涂胶曝光显影的制程，此处，先不对经过显影所留下的图案进行去胶，而是直接对第二金属膜层和欧姆接触层进行刻蚀，在本实施例中，可以先采用干法刻蚀的方式，对欧姆接触层进行刻蚀，再用湿法刻蚀的方式，对第二金属膜层进行刻蚀，然后再进行去胶的步骤。这样，就可以得到第一存储电容的上电极；采用与得到第一存储电容的上电极同样的方法还可以同时成形信号线和栅电极的源漏极金属，并且在信号线、源漏极金属和第一存储电容的上电极的上方都附有一层欧姆接触层。
得到第一存储电容的上电极后，在附在信号线、源漏极金属和第一存储电容的上电极上方的欧姆接触层上，采用PECVD的方法沉积一层半导体层，并在该半导体层上方沉积一层第二绝缘层，本实施例中，半导体层可以为a-Si，第二绝缘层可以为SiNx。然后，在第二绝缘层上方采用真空溅射的方法沉积一层第三金属膜层；并对第三金属膜层、半导体层和第二绝缘层进行涂胶曝光显影的制程，在本实施例中，可以先用湿法刻蚀的方式，对第三金属膜层进行刻蚀，再用干法刻蚀的方式，对半导体层和第二绝缘层进行刻蚀，最后再进行去胶的步骤。在这个步骤中，附在栅电极的漏极金属上的一部分欧姆接触层和附在第一存储电容的上电极上的欧姆接触层同时被刻蚀掉。
当附在栅电极的漏极金属上的一部分欧姆接触层和附在第一存储电容的上电极上的欧姆接触层被刻蚀掉之后，采用PECVD的方法沉积一层保护层，并且对该保护层进行涂胶曝光显影的制程，在这个步骤中，所采用的曝光为半曝光，并且需要采用半曝光罩，经历了涂胶曝光显影后，用干法刻蚀的方式，在保护层上蚀刻出两个通孔，即通孔1和通孔2，然后在蚀刻了通孔1和通孔2的保护层上采用真空溅射的方法沉积一层ITO膜，并且最终成形第二存储电容的上电极和像素ITO电极。本实施例中，当在保护层上沉积了ITO膜后，该ITO膜通过通孔1与栅电极的漏极金属连接，便可成形像素电极；同时，ITO膜通过通孔2与构成第一存储电容下电极的金属连接，这样便成形了第二存储电容的上电极。这样，就完成了TFT阵列基板的制作方法的全部步骤。
在上述实施例中，第一存储电容的上电极可以作为第二存储电容的下电极使用，第二存储电容的下电极、ITO膜通过通孔2与第一存储电容下电极的金属连接所成形的第二存储电容的上电极共同构成第二存储电容。这样，第一存储电容和第二存储电容就可以实现其之间的并联连接，从而共同构成像素的存储电容。
将第一存储电容的上电极作为第二存储电容的下电极，当ITO膜通过通孔2和构成第一存储电容下电极的金属相连接后，就成形了第二存储电容的上电极，这样，第一存储电容和第二存储电容便可以实现并联连接，采用这种连接的方式，在需要增大存储电容的电容值时，可以同时保证存储电容的面积的减小，这样，便可以在很大程度上提高相应像素的开口率。
参照图3，图3为本发明TFT阵列基板实施例中在玻璃基板上成形挡光金属和第一存储电容的下电极后的结构示意图。
在本实施例中，TFT阵列基板，包括玻璃基板10和第一绝缘层20，还包括成形于玻璃基板10上的挡光金属，该挡光金属70可以通过对沉积在玻璃基板10上的第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶的方法得到。
对沉积在玻璃基板10上的第一金属膜层进行涂胶曝光显影的制程，并且采用湿法刻蚀的方式对经过涂胶曝光显影后，对玻璃基板10上留下的第一金属膜层进行蚀刻及去胶，便可以得到一层挡光金属70。所成形的挡光金属70可以用于对TFT开关器件进行保护，在之后的光刻过程中，使TFT开关器件不会受到强光的照射而影响该TFT开关器件的稳定性。
在本实施例中，第一绝缘层20为在对第一金属膜层进行了涂胶曝光显影以及刻蚀和去胶的步骤，并得到挡光金属70后，在包含有该挡光金属70的基板上采用PECVD（Plasma Enhanced Chemical Vapor Deposition ，等离子体增强化学气相沉积法）的方法所沉积的，采用第一绝缘层20，可以便于进行下一步的光刻步骤，所采用的第一绝缘层可以为SiNx。
本发明实施例，通过4Mask的方式来制作TFT阵列基板，对沉积在经过清洗的玻璃基板10上的第一金属膜层进行涂胶曝光显影的制程，并通过蚀刻以及去胶的方法在玻璃基板上成形一层挡光金属70，采用这一层挡光金属70，可以在之后的制程中，对TFT开关器件起到很好的保护作用，从而可以避免其由于受到强光的照射而导致的稳定性降低的问题。
在上述实施例中，TFT阵列基板还包括在成形挡光金属70时一并成形于玻璃基板10上的第一存储电容的下电极81，该第一存储电容的下电极81与挡光金属70可以通过同样的方法得到。在成形挡光金属70的同时，可以采用同样的方法，对沉积在玻璃基板10上的第一金属膜层进行涂胶曝光显影的制程，并且同样采用湿法刻蚀的方式对玻璃基板10上所留下的第一金属膜层进行蚀刻及去胶，从而可以得到第一存储电容的下电极81。
参照图4，图4为在图3的基础上成形第一存储电容的上电极后的工艺结构示意图。
在本实施例中，TFT阵列基板还包括成形于第一绝缘层20上的第一存储电容的上电极82，第一存储电容的上电极82通过对沉积在第一绝缘层20上的第二金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶得到。
当得到挡光金属70和第一存储电容的下电极81后，可以采用真空溅射的方法在沉积在包含有挡光金属70和第一存储电容的下电极81的基板上的第一绝缘层20上沉积一层第二金属膜层，然后，采用PECVD的方法在该第二金属膜层上沉积一层欧姆接触层30，并对第二金属膜层和欧姆接触层30进行涂胶曝光显影的制程，此处，先不对经过显影所留下的图案进行去胶，而是直接对第二金属膜层和欧姆接触层30进行刻蚀，在本实施例中，可以先采用干法刻蚀的方式，对欧姆接触层30进行刻蚀，再用湿法刻蚀的方式，对第二金属膜层进行刻蚀，然后再进行去胶的步骤。这样，就可以得到第一存储电容的上电极82，在本实施例中，所得到的该第一存储电容的上电极82的金属的面积小于构成第一存储电容的下电极81的金属的面积。
采用与得到第一存储电容的上电极82同样的方法，同时还可以成形信号线、源极金属41和漏极金属42，并且在信号线、源极金属41和漏极金属42，以及第一存储电容的上电极82的上方都附有一层欧姆接触层30。
参照图5，图5为在图4的基础上刻蚀掉欧姆接触层以及成形栅电极后的结构示意图。
在上述实施例中，在附在信号线、源极金属41和漏极金属42，以及第一存储电容的上电极82上方的欧姆接触层30上，采用PECVD的方法沉积一层半导体层50，并在该半导体层50上方沉积一层第二绝缘层60，本实施例中，半导体层50可以为a-Si，第二绝缘层60可以为SiNx，然后在第二绝缘层60上方采用真空溅射的方法沉积一层第三金属膜层；并对第三金属膜层、半导体层50和第二绝缘层60进行涂胶曝光显影的制程，在本实施例中，可以先用湿法刻蚀的方式，对第三金属膜层进行刻蚀，再用干法刻蚀的方式，对半导体层50和第二绝缘层60进行刻蚀，最后再进行去胶的步骤。在这个步骤中，附在漏极金属42上的一部分欧姆接触层30和附在第一存储电容的上电极82上的欧姆接触层30同时被刻蚀掉，并且成形了栅电极40。
参照图6，图6为在图5的基础上成形第二存储电容的上电极后的工艺结构示意图。
在本实施例中，当附在栅电极40的漏极金属42上的部分欧姆接触层30和附在第一存储电容的上电极82上的欧姆接触层30被刻蚀掉，并且成形了栅电极40后，采用PECVD的方法在玻璃基板10上此时所留下的图案的上方沉积一层保护层，并且对该保护层进行涂胶曝光显影的制程，在这个步骤中，所采用的曝光为半曝光，并且需要采用半曝光罩。经历了涂胶曝光显影后，用干法刻蚀的方式，在保护层上蚀刻出两个通孔，即通孔1和通孔2，然后在蚀刻了通孔1和通孔2的保护层上采用真空溅射的方法沉积一层ITO膜90，并且最终成形第二存储电容的上电极和像素ITO电极。本实施例中，当在保护层上沉积了ITO膜90后，该ITO膜90通过通孔1与栅电极40的漏极金属42连接，便可成形像素电极；同时，ITO膜通过通孔2与构成第一存储电容下电极81的金属连接，就可以形成第二存储电容的上电极。这样，便完成了TFT阵列基板的制作方法的全部步骤。
在上述实施例中，第一存储电容的上电极82可以作为第二存储电容的下电极使用，第二存储电容的下电极和ITO膜90通过通孔2与第一存储电容下电极81的金属连接所成形的第二存储电容的上电极共同构成第二存储电容。这样，第一存储电容和第二存储电容便实现了其之间的并联连接，从而共同构成像素的存储电容。
将第一存储电容的上电极82作为第二存储电容的下电极，当ITO膜90通过通孔2和构成第一存储电容下电极81的金属相连接后，就成形了第二存储电容的上电极，这样，第一存储电容和第二存储电容便可以实现并联连接，采用这种连接的方式，在需要增大存储电容的电容值时，可以同时保证存储电容的面积的减小，这样，便可以在很大程度上提高相应像素的开口率。
以上所述仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围。

Claims (17)

  1. 一种TFT阵列基板的制作方法，其特征在于，包括：
    在基板上沉积第一金属膜层；
    对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到挡光金属；
    对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，成形第一存储电容的下电极。
  2. 如权利要求1所述的制作方法，其特征在于，还包括：
    在包含有所述挡光金属的基板上沉积第一绝缘层，该第一绝缘层为SiNx。
  3. 如权利要求1所述的制作方法，其特征在于，还包括：
    在包含有所述挡光金属和第一存储电容的下电极的基板上沉积第二金属膜层，对第二金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到第一存储电容的上电极。
  4. 如权利要求3所述的制作方法，其特征在于，在得到第一存储电容的上电极之后，还包括：
    在所述第二金属膜层上沉积一层欧姆接触层，并对所述欧姆接触层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到信号线和栅电极的源、漏极金属；在所述信号线、源漏极金属和第一存储电容的上电极的上方都附有一层欧姆接触层。
  5. 如权利要求4所述的制作方法，其特征在于，在得到信号线和栅电极的源、漏极金属之后，还包括：
    在附在所述信号线、源漏极金属和第一存储电容的上电极上方的欧姆接触层上，依次沉积半导体层、第二绝缘层和第三金属膜层；
    对所述半导体层、第二绝缘层和第三金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，附在所述栅电极漏极金属上的一部分欧姆接触层和附在第一存储电容的上电极上的欧姆接触层同时被刻蚀掉。
  6. 如权利要求5所述的制作方法，其特征在于，当附在所述栅电极漏极金属上的一部分欧姆接触层和附在第一存储电容的上电极上的欧姆接触层同时被刻蚀掉之后，还包括：
    沉积一层保护层，对保护层进行涂胶曝光显影的制程，并在所述保护层上蚀刻出通孔1和通孔2；
    在所述保护层上沉积一层ITO膜，所述ITO膜通过通孔1与栅电极的漏极金属连接形成像素电极；ITO膜通过通孔2与构成第一存储电容下电极的金属连接形成第二存储电容的上电极。
  7. 如权利要求6所述的制作方法，其特征在于，将所述第一存储电容的上电极作为第二存储电容的下电极，并将所述第一存储电容和所述第二存储电容并联连接共同构成像素的存储电容。
  8. 一种TFT阵列基板的制作方法，其特征在于，包括：
    在基板上沉积第一金属膜层；
    对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到挡光金属。
  9. 如权利要求8所述的制作方法，其特征在于，在执行所述对第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到挡光金属之后还包括：
    对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，成形第一存储电容的下电极。
  10. 如权利要求9所述的制作方法，其特征在于，还包括：
    在包含有所述挡光金属和第一存储电容的下电极的基板上沉积第二金属膜层，对第二金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶，得到第一存储电容的上电极。
  11. 如权利要求10所述的制作方法，其特征在于，将所述第一存储电容的上电极作为第二存储电容的下电极，并将所述第一存储电容和所述第二存储电容并联连接共同构成像素的存储电容。
  12. 如权利要求11所述的制作方法，其特征在于，还包括：
    在包含有所述挡光金属的基板上沉积第一绝缘层，该第一绝缘层为SiNx。
  13. 一种TFT阵列基板，包括玻璃基板和第一绝缘层，其特征在于，还包括成形于所述玻璃基板上的挡光金属，所述挡光金属通过对沉积在所述玻璃基板上的第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶的方法得到。
  14. 如权利要求13所述的TFT阵列基板，其特征在于，还包括对所述第一金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶而成形于所述玻璃基板上的第一存储电容的下电极。
  15. 如权利要求14所述的TFT阵列基板，其特征在于，还包括成形于所述第一绝缘层上的第一存储电容的上电极，所述第一存储电容的上电极通过对沉积在所述第一绝缘层上的第二金属膜层进行涂胶曝光显影制程，并经过刻蚀及去胶得到。
  16. 如权利要求15所述的TFT阵列基板，其特征在于，所述第一存储电容的上电极作为第二存储电容的下电极，所述第一存储电容和所述第二存储电容为并联连接，共同构成像素的存储电容。
  17. 如权利要求16所述的TFT阵列基板，其特征在于，构成所述第一存储电容上电极的金属的面积小于构成所述第一存储电容下电极的金属的面积。
PCT/CN2011/083871 2011-12-07 2011-12-13 Tft阵列基板的制作方法及tft阵列基板 Ceased WO2013082827A1 (zh)

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