WO2013081306A1 - Lead frame and semiconductor package including the same - Google Patents

Lead frame and semiconductor package including the same Download PDF

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Publication number
WO2013081306A1
WO2013081306A1 PCT/KR2012/009087 KR2012009087W WO2013081306A1 WO 2013081306 A1 WO2013081306 A1 WO 2013081306A1 KR 2012009087 W KR2012009087 W KR 2012009087W WO 2013081306 A1 WO2013081306 A1 WO 2013081306A1
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WO
WIPO (PCT)
Prior art keywords
metal layer
lead frame
layer
alloy
base material
Prior art date
Application number
PCT/KR2012/009087
Other languages
English (en)
French (fr)
Inventor
Sung-Kwan Paek
Dong-Il Shin
Se-Chuel Park
Original Assignee
Samsung Techwin Co., Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Techwin Co., Ltd filed Critical Samsung Techwin Co., Ltd
Publication of WO2013081306A1 publication Critical patent/WO2013081306A1/en

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    • H—ELECTRICITY
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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Definitions

  • the present invention relates to an electric device, and more particularly, to a lead frame and a semiconductor package including the lead frame.
  • the present invention relates to an electric device, and more particularly, to a lead frame and a semiconductor package including the lead frame.
  • a lead frame electrically connects a semiconductor chip to an external device and supports the semiconductor chip.
  • a semiconductor chip is attached to a lead frame, and the semiconductor chip is bonded to the lead frame by using a bonding wire and is sealed by a mold resin, thereby manufacturing a semiconductor package.
  • the PPF type is a method of forming a palladium plating layer on a nickel plating layer; however, palladium may be oxidated in an assembling process in which heat is applied or nickel may be diffused in the palladium plating layer to form nickel oxide on a surface of the palladium plating layer, thereby degrading wire bondability, solder wettability, and solderability.
  • KR Laid-open Patent No. 2010-0103015 discloses a structure in which a gold (Au) plating layer is formed on a palladium plating layer.
  • Au gold
  • the price of gold (Au) per unit weight is tens to hundreds times higher than that of any other metal materials, manufacturing costs of a lead frame increase, thereby degrading the economic competitiveness of the lead frame.
  • JP Laid-open Patent No. 1999-111909 discloses a structure in which a palladium alloy plating layer is formed on a nickel plating layer without using gold.
  • a content of palladium in the palladium alloy is 50% or greater, and a thickness of the palladium alloy plating layer is about 0.05 to 1 ⁇ m.
  • the palladium is as expensive as gold (Au), and thus, if the content of the palladium in the palladium alloy plating layer is 50% or greater and the thickness of the palladium alloy plating layer is 0.05 to 1 ⁇ m, the manufacturing costs of the lead frame are not much less than that of the case where the gold (Au) plating layer is formed.
  • the palladium material largely affects the solder wettability, the solder wettability is greatly reduced when the content of the palladium material is 50% or greater.
  • the present invention provides a lead frame having excellent solder wettability and an excellent bonding property with a copper wire, wherein the lead frame is manufactured at low manufacturing costs.
  • the present invention also provides a semiconductor package manufactured by using the lead frame at low manufacturing costs, thus having high reliability.
  • a lead frame includes: a base material; a first metal layer formed on at least a surface of the base material by using copper; and a second metal layer formed of an alloy including at least silver (Ag) and palladium (Pd) on a surface of the first metal layer.
  • an attachability to bonding wires formed of copper is excellent and an epoxy bleeding may be effectively restrained during a die-attach process. Also, since an outermost metal layer is formed of an Ag-Pd alloy or an alloy including Ag and Pd, expensive gold does not need to be used, thereby reducing manufacturing costs of the lead frame greatly and improving a solder wettability and a solderability of the lead frame.
  • a semiconductor package according to the invention includes the lead frame, and thus, the semiconductor package may be manufactured at low manufacturing costs to obtain high reliability.
  • FIG. 1 is a plan view of a lead frame to which the present invention may be applied;
  • FIG. 2 is a cross-sectional view showing a part of a lead frame according to an embodiment of the present invention
  • FIG. 3 is a diagram showing an expanded portion of a part A shown in FIG. 2;
  • FIG. 4 is a cross-sectional view of the lead frame to which a semiconductor chip is mounted, according to the embodiment of the present invention.
  • FIGS. 5A through 5C are photographs showing a result of testing a solderability of the lead frame according to an embodiment of the present invention.
  • FIGS. 6A through 6C are graphs showing a result of testing solder wettability of the lead frame according to an embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view of a semiconductor package manufactured by using the lead frame according to the embodiment of the present invention.
  • a lead frame includes: a base material; a first metal layer formed on at least a surface of the base material by using copper; and a second metal layer formed of an alloy including at least silver (Ag) and palladium (Pd) on a surface of the first metal layer.
  • the first metal layer may be surface-treated to have surface roughness.
  • the second metal layer may have a thickness of 0.5 to about 5 ⁇ m.
  • a content amount of Pd included in the alloy including at least silver (Ag) and palladium (Pd) may be one of 1 to 30 atomic% and 0.9 to 27.7 weight%.
  • the second metal layer may be formed of an Ag-Pd-copper (Cu) alloy.
  • a content amount of Pd included in the Ag-Pd-Cu alloy is 1 to 30 atomic%, and a content amount of Cu in the Ag-Pd-Cu alloy may be 1 to 30 atomic%.
  • the second metal layer may be formed of an Ag-Pd-gold (Au) alloy.
  • a content amount of Pd included in the Ag-Pd-Au alloy is 1 to 30 atomic%, and a content amount of Au in the Ag-Pd-Au alloy may be 1 to 10 atomic%.
  • the second metal layer may be formed of an Ag-Pd-Cu-Au alloy.
  • a content amount of Pd included in the Ag-Pd-Cu-Au alloy may be about 1 to 30 atomic%
  • a content amount of Cu in the Ag-Pd-Cu-Au alloy may be 1 to 30 atomic%
  • a content amount of Au in the Ag-Pd-Cu-Au alloy may be 1 to 10 atomic%.
  • the lead frame may further include an organic coating layer on a surface of the second metal layer.
  • a surface of the base material may be plasmatized.
  • a semiconductor package includes: a lead frame comprising: a base material comprising a die pad and a lead unit; a first metal layer formed on at least a surface of the base material; and a second metal layer formed of an alloy including at least silver (Ag) and palladium (Pd) on a surface of the first metal layer; a semiconductor chip attached on the die pad; and a plurality of bonding wires connecting the semiconductor chip to the lead unit.
  • FIG. 1 is a plan view of a lead frame 100 according to an embodiment of the present invention.
  • the lead frame 100 includes a die pad 103 and a lead unit 105.
  • a semiconductor chip (211, refer to FIG. 7) is attached to the die pad 103.
  • the lead unit 105 includes a plurality of leads, and is connected to the semiconductor chip 211 (refer to FIG. 7) via a plurality of wires (231, refer to FIG. 7). Therefore, electric signals output from the semiconductor chip 211 (refer to FIG. 7) are transferred to an external device via the lead unit 105, and electric signals input from the external device to the lead unit 105 may be transferred to the semiconductor chip 211 (refer to FIG. 7).
  • FIG. 2 is a cross-sectional view of a part of a lead frame 101 according to an embodiment of the present invention.
  • the lead frame 101 according to the present embodiment includes a base material 107, a first metal layer 111, and a second metal layer 121.
  • the base material 107 is a plane metal plate on which the first and second metal layers 111 and 121 are plated.
  • the base material 107 is formed of a hardening material supporting the first and second metal layers 111 and 121.
  • the first and second metal layers 111 and 121 may be formed on opposite surfaces of the base material 107, or may be formed on only one surface of the base material 107.
  • the base material 107 corresponds to the die pad 103 and the lead unit 105 in the lead frame 100 of FIG. 1.
  • the base material 107 may be formed of copper or a copper alloy.
  • a surface of the base material 107 may be processed with plasma in order to improve an adhesive force between the base material 107 and the first metal layer 111 formed of copper.
  • the first and second metal layers 111 and 121 may be formed as the following examples
  • the first metal layer 111 may be formed by copper strike plating, and the second metal layer 121 may be formed of a silver-palladium (Ag-Pd) alloy.
  • the first metal layer 111 is formed on a surface of the base material 107.
  • the first metal layer 111 is formed by copper strike plating in an electrolytic plating method.
  • the base material 107 is dipped in a metal ion solution tube, and high electric current is supplied thereto to form the first metal layer 111 on the base material 107.
  • the second metal layer 121 is formed on a surface of the first metal layer 111 to form an outermost metal layer of the lead frame 101.
  • the second metal layer 121 may be formed of an alloy including at least silver (Ag) and palladium (Pd).
  • the Ag-Pd alloy forming the second metal layer 121 may further include other metal materials, for example, gold (Au), nickel (Ni), copper (Cu), cobalt (Co), molybdenum (Mo), ruthenium (Ru), phosphor (P), tin (Sn), and indium (In), and the sum of the other materials may not exceed about 10%.
  • the second metal layer 121 has a thickness of about 0.5 to about 5 ⁇ m in consideration of stability, price, and surface roughness thereof, and a content of palladium is about 1 to about 30 atomic% or about 0.9 to about 27.7 weight%.
  • the remaining content includes Ag, and the above described other metal materials.
  • the first metal layer 111 is formed of nickel or a nickel alloy
  • the second metal layer 121 may be formed of an Ag-Pd alloy.
  • the first metal layer 111 is formed on a surface of the base material 107.
  • the first metal layer 111 is formed of nickel or a nickel alloy in an electrolytic plating method.
  • the base material 107 is dipped in a metal ion solution tube and high electric current is supplied to the base material 107 so as to form the first metal layer 111 on the base material 107.
  • the Ag-Pd alloy forming the second metal layer 121 is the same as that of the first embodiment, and thus, detailed descriptions thereof are omitted here.
  • the first metal layer 111 is formed as a copper-plated layer, a surface of which is processed to have roughness, and the second metal layer 121 may be formed of an Ag-Pd alloy.
  • the first metal layer 111 is formed on a surface of the base material 107.
  • the first metal layer 111 is formed as a copper-plated layer, and a surface of the first metal layer 111 is processed to have roughness. That is, the first metal layer 111 may be processed to have roughness by using copper.
  • the base material 107 is dipped in a copper sulfate solution and an electric current at a high concentration about 15 A/dm2 (ASD) is applied for a short period of 5 to 20 seconds in order to rapidly grow the first metal layer 111.
  • ASSD A/dm2
  • the copper-plated layer is formed on the base material 107, and a surface of the copper-plated layer is formed as nodules, thereby making the surface of the copper-plated layer rough.
  • the Ag-Pd alloy forming the second metal layer 121 is the same as that of the first embodiment, and thus, detailed descriptions thereof are omitted here.
  • the second metal layer 121 forming the outermost layer of the lead frame 101 is formed of an Ag-Pd alloy.
  • the second metal layer 121 includes Ag that is more active than gold (Au)
  • Au gold
  • a bleeding phenomenon of epoxy that is used in a die-attaching process is efficiently reduced.
  • a predetermined fraction of Ag included in the second metal layer 121 has to be ensured. That is, a fraction of the palladium in the Ag-Pd alloy forming the second metal layer 121 may not exceed 40%. Since the second metal layer 121 is formed of the Ag-Pd alloy, a ductility and corrosion resistance of the lead frame 101 may be improved.
  • the first metal layer 111 is formed by copper strike plating, and the second metal layer 121 may be formed of an Ag-Pd-Au alloy.
  • the copper strike plating forming the first metal layer 111 is described in the first embodiment, and thus, detailed descriptions thereof are omitted here.
  • the second metal layer 121 is formed on a surface of the first metal layer 111 to form the outermost layer of the lead frame 101.
  • the second metal layer 121 may be formed of an Ag-Pd-Au alloy material.
  • the second metal layer 121 has a thickness of about 0.5 to about 5 ⁇ m in consideration of stability, price, and surface roughness.
  • a content of Pd may be about 1 to 30 atomic%
  • a content of Au may be about 1 to 10 atomic%.
  • the remaining content includes Ag.
  • the first metal layer 111 is formed as a copper-plated layer that is roughness processed, and the second metal layer 121 may be formed of an Ag-Pd-Au alloy.
  • the copper-plated layer, the surface of which is processed to have roughness, forming the first metal layer 111 is described in above third embodiment, and the Ag-Pd-Au alloy forming the second metal layer 121 is described in the above fourth embodiment. Thus, detailed descriptions thereof are not provided here.
  • the first metal layer 111 may be formed by copper strike plating, and the second metal layer 121 may be formed of an Ag-Pd-Cu alloy.
  • the copper strike plating forming the first metal layer 111 is described in the above first embodiment, and thus, detailed descriptions thereof are omitted here.
  • the second metal layer 121 is formed on a surface of the first metal layer 111 to form the outermost layer of the lead frame 101.
  • the second metal layer 121 may be formed of an Ag-Pd-Cu alloy.
  • the second metal layer 121 has a thickness of about 0.5 to about 5 ⁇ m in consideration of stability, price, and surface roughness.
  • a content of Pd may be about 1 to 30 atomic%
  • a content of Cu may be about 1 to 30 atomic%.
  • the remaining content includes Ag.
  • the first metal layer 111 is formed as a copper-plated layer, a surface of which is processed to have roughness, and the second metal layer 121 may be formed of an Ag-Pd-Cu alloy.
  • the copper-plated layer, the surface of which is processed to have roughness, forming the first metal layer 111 is described in the above third embodiment, and the Ag-Pd-Cu alloy forming the second metal layer 121 is described in the above sixth embodiment. Thus, detailed descriptions are not omitted here.
  • the first metal layer 111 is formed by copper strike plating, and the second metal layer 121 may be formed of an Ag-Pd-Cu-Au alloy.
  • the copper strike plating forming the first metal layer 111 is described in the above first embodiment, and thus, detailed descriptions thereof are omitted here.
  • the second metal layer 121 is formed on a surface of the first metal layer 111 to form the outermost layer of the lead frame 101.
  • the second metal layer 121 may be formed of an Ag-Pd-Cu-Au alloy material.
  • the second metal layer 121 has a thickness of about 0.5 to about 5 ⁇ m in consideration of stability, price, and surface roughness.
  • a content of Pd may be about 5 to 30 atomic%
  • a content of Cu may be about 1 to 30 atomic%
  • a content of Au may be about 1 to 10 atomic%.
  • the remaining content includes Ag.
  • the first metal layer 111 is formed as a copper-plated layer, a surface of which is processed to have roughness, and the second metal layer 121 may be formed of an Ag-Pd-Cu-Au alloy.
  • the copper-plated layer, the surface of which is processed to have roughness, forming the first metal layer 111 is described in the above third embodiment, and the Ag-Pd-Cu-Au alloy forming the second metal layer 121 is described in the above eighth embodiment. Thus, detailed descriptions thereof are omitted here.
  • the first metal layer 111 may be formed of a Ni-Pd alloy, and the second metal layer 121 may be formed of an Ag-Pd-Cu-Au alloy.
  • the first metal layer 111 is formed on a surface of the base material 107.
  • the first metal layer 111 may be formed of the Ni-Pd alloy.
  • the second metal layer 121 may have a thickness of about 0.5 to about 5 ⁇ m in consideration of stability, price, and surface roughness.
  • a content of Pd may be about 5 to 30 atomic%
  • a content of Cu may be about 1 to 30 atomic%
  • a content of Au may be about 1 to 10 atomic%.
  • the remaining content includes Ag.
  • FIG. 3 is an expanded view showing a portion A of FIG. 2.
  • the first metal layer 111 may include two layers, namely, a seed layer 113 and a protective layer 115.
  • the seed layer 113 is formed on a surface of the base material 107
  • the protective layer 115 is formed on a surface of the seed layer 113.
  • the seed layer 113 and the protective layer 115 may be formed of the same metal material, or may be formed of different metal materials.
  • the seed layer 113 may have a rough surface.
  • the base material 107 is dipped in a copper sulfate solution, and a high-density electric current, about 15 A/dm2 (ASD), is applied for a short period of about 5 to 20 seconds to rapidly grow the seed layer 113.
  • ASD high-density electric current
  • the surface of the seed layer 113 is formed as nodules, and thus, the surface is rough.
  • the copper sulfate solution used to form the seed layer 113 of copper includes sulfuric acid (CuSO4) and copper sulfate hydrate (CuSO4 ⁇ 5H2O).
  • a concentration of the sulfuric acid and the copper sulfate hydrate included in the copper sulfate solution may be about 10 to 30 g/l.
  • the concentration of the copper sulfate hydrate (CuSO4 ⁇ 5H2O) is less than 10 g/l, there are not sufficient copper sulfate ions to perform an electrolytic plating process of the seed layer 113, thereby increasing a processing time and current density. In this case, the growth of the seed layer 113 is not stabilized, and thus, an adhesive force between the seed layer 113 and the base material 107 may be degraded. On the other hand, if the concentration of the copper sulfate hydrate (CuSO4 ⁇ 5H2O) is higher than 30 g/l, the seed layer 113 may be excessively grown to generate smut.
  • the smut may cause a peeling phenomenon of the seed layer 113, that is, the seed layer 113 may be peeled off from the base material 107 or the surface of the seed layer 113 may be peeled off. Also, if the concentration of the copper sulfate hydrate (CuSO4 ⁇ 5H2O) is higher than 30 g/l, the seed layer 113 may be excessively grown to generate burr. Therefore, the concentration of the copper sulfate hydrate (CuSO4 ⁇ 5H2O) may be within a range from 10 to 30 g/l.
  • the concentration of the sulfuric acid may range from 20 to 60 ml/l. If the concentration of the sulfuric acid is less than 20 ml/l, the copper sulfate solution lacks conductive salt, and a portion of the seed layer 113, on which the electric current is concentrated, may be burnt to black. In this case, the seed layer 113 may not have a surface roughness at a required level, and a conductivity of the seed layer 113 may be reduced. If the concentration of the sulfuric acid is higher than 60 ml/l, there is too much conductive salt, thereby polishing the seed layer 113. Thus, it is difficult to form the seed layer 113 having a predetermined roughness.
  • the processing time may be set as about 5 to 20 seconds, because if the processing time is less than 5 seconds, an adhesiveness between the seed layer 113 and the base material 107 is degraded, and if the processing time exceeds 20 seconds, the peeling phenomenon may occur.
  • the surface roughness (Ra) of the seed layer 113 may be about 0.1 to 0.5 um on average.
  • a ruggedness of the surface becomes fine, and thus, a ruggedness of the protective layer 115 to be formed on a seed layer and that of a plating layer to be formed later also become fine, thereby degrading an interlocking effect with a molding unit.
  • the surface roughness of the seed layer 113 is greater than 0.5 um, the seed layer 113 is not stabilized, and thus, the peeling or elimination of a part of the seed layer 113 may be generated.
  • the protective layer 115 is formed on the surface of the seed layer 113.
  • the protective layer 115 may be formed on the surface of the seed layer 113 by an electrolyte plating method at a low speed, in which a lower-density electric current than that of the seed layer 113 is applied.
  • a coupling force between the seed layer 113 and the protective layer 115 is improved and manufacturing processes are simple, thereby rapidly forming the first metal layer 111.
  • the protective layer 115 may have a thickness of about 0.125 to 1.0 ⁇ m. When the thickness of the protective layer 115 is less than 0.125 ⁇ m, a support for the adhesive force of the seed layer 113 may be reduced. If the thickness of the protective layer 115 is greater than 1.0 ⁇ m, the surface roughness of the protective layer 115 may be reduced.
  • the surface roughness of the seed layer 113 may be reflected in a surface of the protective layer 115. That is, the surface of the protective layer 115 also has a surface roughness corresponding to that of the seed layer 113, wherein similar to the seed layer 113, the surface roughness of the protective layer 115 may range from about 0.1 to about 0.5 um.
  • the adhesive force of the seed layer 113 to the base material 107 may be degraded or some parts of the seed layer 113 may be eliminated.
  • the protective layer 115 is formed on the seed layer 113 to compensate for the weak adhesive force of the seed layer 113, and thus, the adhesive force of the seed layer 113 may be improved efficiently. Therefore, the seed layer 113 may be stably fixed on the base material 107. Also, the protective layer 115 also prevents impurities from infiltrating into the seed layer 113.
  • the first metal layer 111 may be stably fixed on the base material 107. Also, the first metal layer 111 has superior flexibility to that of the plating layer that is formed from the base material 107 at once and has a surface roughness, and thus, a bonding property of a wire may be improved in a wire bonding process.
  • the seed layer 113 and the protective layer 115 are formed of different materials , the seed layer 113 and the protective layer 115 may be formed in a method similar to the above described method.
  • the second metal layer 121 forming the outermost layer of the lead frame 101 includes Ag that is more active than Au, the bleeding of the epoxy that is used in a die-attach process may be effectively reduced.
  • a predetermined fraction of Ag in the second metal layer 121 has to be ensured. That is, if the second metal layer 121 is formed of an Ag-Pd alloy or an alloy including Ag and Pd, the fraction of Pd may not exceed 40%.
  • the second metal layer 121 is formed of the Ag-Pd alloy or the alloy including Ag and Pd, the ductility and the corrosion resistance of the lead frame 101 may be improved.
  • a die pad 107-1 on which a semiconductor chip 211 is mounted may be coated with an organic coating layer 131.
  • the organic coating layer 131 includes an organic material.
  • the semiconductor chip 211 is mounted on the die pad 107-1 of the lead frame 101 using the epoxy.
  • the epoxy bleeding may occur, and then, the organic coating layer 131 effectively restrains the epoxy bleeding.
  • FIGS. 5A through 5C are photographs showing results of testing a solderability of the lead frame 101 (refer to FIG. 2). That is, FIGS. 5A through 5C show dip and look test results of the lead frame 101.
  • first through third lead frames a, b, and c were used.
  • the first lead frame a is formed by plating a copper layer/an Ag-Pd alloy layer (Pd content amount: 5 weight%) (3 um) on a surface of a base material
  • the second lead frame b is formed by plating a copper layer/an Ag-Pd alloy layer (Pd content amount: 5 weight%) (9 um) on a surface of a base material
  • the third lead frame c is formed by plating a copper layer/an Ag-Pd alloy layer (Pd content amount: 5 weight%) (15 um) on a surface of a base material.
  • Test were performed under conditions that a lead frame (101 of FIG. 2) was exposed to a temperature of 175 degrees Celsius for two hours and to steam aging for eight hours, and dipped in R-flux: alpha -100 for five seconds.
  • solders are sufficiently stuck on leads of the first, second, and third lead frames a, b, and c, which shows that the first, second, and third lead frames a, b, and c have excellent solderability.
  • FIGS. 6A through 6C are graphs showing results of testing solder wettability of the lead frame (101 of FIG. 2) according to the embodiment of the present invention. That is, FIGS. 6A through 6C show zero-cross time test results.
  • first through third lead frames a, b, and c were used.
  • the first lead frame a is formed by plating a copper layer/an Ag-Pd alloy layer (Pd content amount: 5 weight%) (3 um) on a surface of a base material
  • the second lead frame b is formed by plating a copper layer/an Ag-Pd alloy layer (Pd content amount: 5 weight%) (9 um) on a surface of a base material
  • the third lead frame c is formed by plating a copper layer/an Ag-Pd alloy layer (Pd content amount: 5 weight%) (15 um) on a surface of a base material.
  • Test were performed under conditions that the lead frame (101 of FIG. 2) was exposed to a temperature of 175 degrees Celsius for two hours and to steam aging for eight hours, and dipped in R-flux: alpha -100 for five seconds.
  • a zero-cross time of the first lead frame a was 0.58 seconds
  • a zero-cross time of the second lead frame b was 0.15 seconds
  • a zero-cross time of the third lead frame c was 0.17 seconds. Since the zero-cross times of the first through third lead frames a, b, and c were less than 3 seconds, the solder wettability of the first, second, and third lead frames a, b, and c are excellent.
  • the adhesive force of the lead frame to the bonding wire 231 is strong, and the epoxy bleeding during the die-attach process may be restrained effectively.
  • the outermost metal layer (121 of FIG. 2) is formed of the Ag-Pd alloy or the alloy including Ag and Pd, expensive Au may not be used. Even when gold (Au) is used, a fine amount may be used, thereby greatly reducing manufacturing costs of the lead frame 101. Also, the solder wettability and the solderability of the lead frame 101 may be improved.
  • nickel since nickel may not be used or a small amount of nickel is used, the bonding attachability between the lead frame 101 and a wire formed of copper may be improved.
  • An interface between the base material 107 and the second metal layer 121 including the Ag-Pd alloy or between the first metal layer 111 and the second metal layer including the Ag-Pd alloy is plasmatized, and thus, the attachability between the base material 107 and the second metal layer 121 or between the first metal layer 111 and the second metal layer 121 may be improved.
  • FIG. 7 is a schematic diagram of a semiconductor package 200 manufactured by using the lead frame 101, according to an embodiment of the present invention.
  • the semiconductor chip 211 is attached to the die pad 107-1 using an epoxy 221, and the semiconductor chip 211 and the lead unit 107-2 lead unit are electrically connected to each other by using the bonding wires 231.
  • a plurality of solder balls 251 are formed on an opposite side to the semiconductor chip 211.
  • the plurality of solder balls 251 are electrically connected to the bonding wires 231 through via lines (not shown) that electrically connect upper and lower portions of the lead unit 107-2 to each other.
  • the plurality of solder balls 251 may transmit/receive electric signals to/from the semiconductor chip 211.
  • the semiconductor chip 211, the bonding wires 231, and a part of the or the whole lead frame 101 are sealed by a mold resin 241, for example, an epoxy mold compound, thereby completing the manufacture of the semiconductor package 200.
  • the semiconductor package 200 is highly reliable.
  • the attachability between the lead frame 101 and the mold resin 241 is excellent. Therefore, an isolation of the mold resin 241 from the interface and the infiltration of impurities into the lead frame 101 in the mold resin 241 may be prevented.
  • Embodiments of the present invention may be applied to the field of lead frames and the field of semiconductor packages including lead frames.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
PCT/KR2012/009087 2011-12-01 2012-11-01 Lead frame and semiconductor package including the same WO2013081306A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3015567A1 (en) * 2014-10-30 2016-05-04 Heraeus Deutschland GmbH & Co. KG Suppression of the formation of hillocks or crystals when sintering metal-organic silver compounds

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102085870B1 (ko) * 2013-08-21 2020-03-09 엘지이노텍 주식회사 칩 패키지

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0380176A1 (en) * 1989-01-25 1990-08-01 Meco Equipment Engineers B.V. method for producing a solderable finish on metal frames for semiconductors
KR19980074509A (ko) * 1997-03-25 1998-11-05 이대원 다중 도금층을 가진 반도체 리드프레임
JP2006344925A (ja) * 2005-05-11 2006-12-21 Sharp Corp 発光素子搭載用フレームおよび発光装置
KR20090043907A (ko) * 2007-10-30 2009-05-07 삼성테크윈 주식회사 리드 프레임, 그를 구비한 반도체 패키지 및 그 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0380176A1 (en) * 1989-01-25 1990-08-01 Meco Equipment Engineers B.V. method for producing a solderable finish on metal frames for semiconductors
KR19980074509A (ko) * 1997-03-25 1998-11-05 이대원 다중 도금층을 가진 반도체 리드프레임
JP2006344925A (ja) * 2005-05-11 2006-12-21 Sharp Corp 発光素子搭載用フレームおよび発光装置
KR20090043907A (ko) * 2007-10-30 2009-05-07 삼성테크윈 주식회사 리드 프레임, 그를 구비한 반도체 패키지 및 그 제조방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3015567A1 (en) * 2014-10-30 2016-05-04 Heraeus Deutschland GmbH & Co. KG Suppression of the formation of hillocks or crystals when sintering metal-organic silver compounds
WO2016066598A1 (en) * 2014-10-30 2016-05-06 Heraeus Deutschland GmbH & Co. KG Suppression of the formation of hillocks or crystals when sintering metal-organic silver compounds

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