WO2013041424A1 - Verfahren zur herstellung eines optoelektronischen bauelements - Google Patents
Verfahren zur herstellung eines optoelektronischen bauelements Download PDFInfo
- Publication number
- WO2013041424A1 WO2013041424A1 PCT/EP2012/067808 EP2012067808W WO2013041424A1 WO 2013041424 A1 WO2013041424 A1 WO 2013041424A1 EP 2012067808 W EP2012067808 W EP 2012067808W WO 2013041424 A1 WO2013041424 A1 WO 2013041424A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- transfer layer
- layer
- carrier substrate
- substrate
- semiconductor layer
- Prior art date
Links
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 239000004065 semiconductor Substances 0.000 claims abstract description 56
- 150000002500 ions Chemical class 0.000 claims abstract description 20
- 229910052738 indium Inorganic materials 0.000 claims description 43
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 42
- 238000000926 separation method Methods 0.000 claims description 24
- 230000005855 radiation Effects 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 2
- 238000007669 thermal treatment Methods 0.000 abstract 2
- -1 nitride compound Chemical class 0.000 description 15
- 239000000463 material Substances 0.000 description 12
- 229910052594 sapphire Inorganic materials 0.000 description 7
- 239000010980 sapphire Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 238000007517 polishing process Methods 0.000 description 5
- 239000002131 composite material Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052743 krypton Inorganic materials 0.000 description 2
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 2
- 229910052754 neon Inorganic materials 0.000 description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 2
- 229910052756 noble gas Inorganic materials 0.000 description 2
- 150000002835 noble gases Chemical class 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
Definitions
- the invention relates to a method for producing an optoelectronic component.
- the optoelectronic component is an optoelectronic component.
- Component may, in particular, a light-emitting
- opto-electronic device such as an LED or a semiconductor laser.
- nitride compound semiconductor materials are frequently used which are frequently used which are frequently used which are frequently used which are frequently used which are frequently used.
- the electronic band gap of the nitride compound semiconductor material can be adjusted in particular by the indium content.
- the indium content For example, in the material system In x Gai- x N, depending on the indium content x, a
- Band gap between about 3.4 eV (GaN) and about 0.7 eV (InN) can be adjusted.
- nitride compound semiconductor layers with a comparatively high indium content is made more difficult by the fact that the lattice constant of the nitride compound semiconductor material increases with increasing indium content. This causes a lattice mismatch with the growth substrates typically used for epitaxially growing nitride compound semiconductor layers, such as sapphire or GaN. In general, be on the growth substrate first one or more
- Buffer layers for example of GaN, grown before an indium-containing layer, in particular the active layer of the optoelectronic device is grown.
- the invention is based on the object, an improved method for producing an optoelectronic
- the growth substrate is a substrate suitable for epitaxially growing a nitride compound semiconductor material, preferably a sapphire substrate, a GaN substrate or an SiC substrate.
- a nitride compound semiconductor material preferably a sapphire substrate, a GaN substrate or an SiC substrate.
- Transfer layer containing epitaxially grown at least one semiconductor layer of In x Gai- x N with 0 ⁇ x ⁇ 1.
- Growth substrate is separated and transferred to a carrier different from the growth substrate.
- the ions are preferably hydrogen ions.
- the ions may be ions of noble gases such as helium, neon, krypton or xenon.
- the carrier substrate is
- the carrier substrate must be in
- a carrier substrate can be selected that is characterized by comparatively low costs and / or a good thermal conductivity distinguishes.
- the carrier substrate may be any suitable carrier substrate.
- the carrier substrate may be any suitable carrier substrate.
- the carrier substrate may be any suitable carrier substrate.
- the carrier substrate may comprise Ge, GaAs, AlN, Mo, Au or an alloy with Mo or Au.
- Process step divides the transfer layer along the separation zone by means of a temperature treatment in the lateral direction.
- a temperature treatment in the lateral direction.
- Transfer layer for example, to a temperature in the range of 300 ° C to 900 ° C, preferably to a temperature in
- the heating can, for example, by increasing the
- Ambient temperature for example in an oven, or by a local heating by electromagnetic
- Radiation for example laser or microwave radiation, be effected.
- the implanted ions diffuse in the separation zone and produce bubbles (so-called blisters).
- the spreading of the bubbles in the separation zone finally leads to the separation of the transfer layer into a first part, which is arranged on the growth substrate, and a second part, which is arranged on the carrier substrate.
- the first part of the transfer layer arranged after dicing on the growth substrate is preferably subsequently removed from the growth substrate, for example by means of an etching or polishing process, around the growth substrate for the epitaxial growth of further semiconductor layers to be able to use.
- This is particularly advantageous when a comparatively expensive growth substrate such as
- GaN or sapphire is used.
- a second part of the transfer layer is arranged after the dicing on the carrier substrate.
- a further transfer layer is grown, the at least one
- Semiconductor layer of In y Gai- y N with 0 ⁇ y -S 1 contains.
- the further transfer layer advantageously has a larger one
- the transfer layer first grown on the growth substrate may include Ino, o3Gao, 97N and the further transfer layer Ino, o6Gao, 94N.
- Opto-electronic device containing the active layer.
- the transfer layer having the indium content x on the growth substrate By growing the transfer layer having the indium content x on the growth substrate, transferring the transfer layer to a support substrate, growing another transfer layer having a larger indium content y on the transfer layer, and then transferring the further transfer layer to another support substrate advantageously a quasi-substrate for growing the
- the quasi-substrate thus produced enables the growth of a semiconductor layer sequence comprising one or more layers of InGaN, with low layer voltages and high crystal quality.
- an active layer containing InGaN can be grown in high film quality.
- Transfer layer has a greater indium content than the at least one semiconductor layer of the respectively previously applied transfer layer.
- Transfer layer is thus advantageously increased stepwise at each repetition.
- the invention makes use of the knowledge that the when the transfer layer is grown on the growth substrate and / or on a previously grown transfer layer
- the last-applied transfer layer has a
- the indium component y of the at least one semiconductor layer is the further one
- Transfer layer by a value between 0.02 inclusive and 0.05 inclusive, more preferably by a value between 0.03 and 0.04 inclusive, greater than the indium content of the at least one semiconductor layer of the previously applied transfer layer.
- Transfer layer is present only a small lattice mismatch to the previous transfer layer, on the other hand, however, the increase in the indium content is sufficiently large, that a not too large number of repetitions achieves a target value for the indium content.
- the number of repetitions in a preferred embodiment is at least two, more preferably between two and eight inclusive.
- Semiconductor layer sequence of the optoelectronic component is grown, In y Gai- y N with y ⁇ 0.1, preferably y ⁇ 0.2, more preferably y ⁇ 0.3. The last used
- Carrier substrate with the last applied transfer layer thus forms a quasi-substrate for the semiconductor layer sequence of the optoelectronic component, which has a high
- the method is particularly suitable for producing an optoelectronic component in which the active layer has a high indium content.
- the active layer contains at least one layer of In z Ga z z N with z> 0.1.
- z is> 0.2, more preferably z> 0.3.
- the active layer may be, for example, as a pn junction, as a double heterostructure, as
- Simple quantum well structure or multiple quantum well structure may be formed.
- the active portion is configured to:
- the transfer layer and / or the at least one further transfer layer has a thickness of between 200 nm and 2 ym inclusive. This thickness range is advantageous for the
- the transfer layer and / or the at least one further transfer layer consists of one
- the transfer layer and / or the at least one further transfer layer can advantageously be applied to the growth substrate and / or the previously applied layer in a single method step
- the transfer layer and / or the at least one further transfer layer may have a plurality of partial layers which have a superlattice structure
- Embodiment an In x iGai- x iN / In x2 Gai X X 2N superlattice with x2> xl exhibit.
- mechanical stresses that arise when growing a single transfer layer can be advantageously reduced.
- the growth substrate is a GaN substrate or a sapphire substrate.
- the carrier substrate and / or the further carrier substrate preferably has Ge, GaAs, AlN, Mo, Au or alloys with Au or Mo. These materials are characterized in particular by good thermal conductivity and / or electrical conductivity.
- Figures 1 to 12 is a schematic representation of a
- Embodiment of the method for producing an optoelectronic component based on intermediate steps Embodiment of the method for producing an optoelectronic component based on intermediate steps
- Figure 13 is a schematic representation of a
- a transfer layer 2 is on
- Growth substrate 1 has been grown.
- the growth of the transfer layer 2 takes place epitaxially, for example by means of MOVPE (Metal Organic Vapor Phase Epitaxy).
- MOVPE Metal Organic Vapor Phase Epitaxy
- Growth substrate 1 is a growth substrate suitable for the epitaxial growth of a nitride compound semiconductor, preferably a sapphire substrate or a GaN substrate.
- the transfer layer 2 is a semiconductor layer of In x Ga x-x N with 0 ⁇ x ⁇ 1.
- the indium content x of the transfer layer 2 grown directly on the growth substrate is preferably between 0.02 and 0.05, more preferably between 0 and 0 , 03 and inclusive
- the indium content x of the transfer layer 2 is comparatively low in this case, so that the transfer layer 2 has only a small lattice mismatch with the growth substrate 1. This has the advantage that mechanical stresses in the growth of the transfer layer 2 are low, so that the transfer layer 2 with a high layer quality
- the thickness of the transfer layer 2 is preferably between 200 nm inclusive and 2 ⁇ m inclusive.
- Hydrogen ions 3 implanted to form a separation zone 4 in the transfer layer 2.
- hydrogen ions 3 other ions, for example ions of
- Transfer layer 2 are implanted.
- the position of the separation zone 4 in the transfer layer 2 is determined by the penetration depth of the Ion 3 is determined in the semiconductor material of the transfer layer 2, and thus can be adjusted by the energy of the implanted ions 3 targeted.
- a carrier substrate 5 is placed on a growth substrate 1
- the carrier substrate 5 can be connected to the transfer layer 2, for example, by soldering or bonding.
- the carrier substrate may be, for example, a substrate of Ge, GaAs, AlN, a metal such as Mo, Au or alloys thereof.
- the carrier substrate 5 does not have to be suitable for the epitaxial growth of a nitride compound semiconductor material and can therefore be advantageously used on the basis of other criteria, such as
- the thermal expansion coefficient, the thermal conductivity and / or the electrical conductivity can be selected.
- a comparatively inexpensive carrier substrate 5 compared to GaN or sapphire can be used.
- a temperature treatment is performed, in which the composite of the growth substrate 1, the transfer layer 2 and the carrier substrate 5 to a temperature between about 300 ° C and 900 ° C, preferably between 300 ° C and inclusive including 700 ° C, is heated. This forms in the separation zone 4, in the previously the hydrogen ions
- Be supported action in which, for example, a torque on the growth substrate 1 and / or the
- Carrier substrate 5 is exercised. After cutting the
- Transfer layer 2 is for example a part of
- the part of the transfer layer 2 remaining on the growth substrate 1 can be removed from the growth substrate 1 by means of an etching or polishing process, for example, so that it can be reused for growing further transfer layers. This is especially true
- Transfer layer 2 is preferably treated with an etch or
- Carrier substrate 5 and the transfer layer 2 arranged thereon forms a quasi-substrate for growing one or more further semiconductor layers. The so produced
- smoothed transfer layer 2 is shown in FIG.
- a further temperature treatment may be carried out in order to prevent any damage to the crystal structure of the substrate caused by the previous ion implantation
- a further transfer layer 7 to the from Support substrate 5 facing away from the surface of the transfer layer 2 grown.
- the further transfer layer 7 is a layer of In y Gai- y N whose indium content y is greater than the indium content of the previously applied transfer layer 2.
- the indium content y of the further transfer layer 7 is preferably one Value between
- the further transfer layer 7 therefore advantageously has only a comparatively small amount
- applied transfer layer 2 can be grown.
- ions preferably hydrogen ions, are implanted in the further transfer layer 7 to form a separation zone 4.
- the remaining on the other carrier substrate 8 part of the further transfer layer 7 can be smoothed subsequently, for example, with an etching or polishing process, so that the composite shown in Figure 11 from the other
- Quasi-substrate for epitaxially growing one or more further semiconductor layers is formed.
- the method steps illustrated in FIGS. 7 to 11 can subsequently be repeated once or several times, wherein the indium content y of the further transfer layer 7 is increased stepwise at each repetition.
- the indium content of the further transfer layer 7 is at each repetition by a value between 0.02 and 0.05 inclusive, preferably between 0.03 and 0.03 inclusive
- Transfer layer 7 is formed, a growth surface for growing one or more further semiconductor layers having a comparatively large indium content.
- the indium content y of the further transfer layer 7 after the last repeat carried out is at least 0.1, preferably at least 0.2 and particularly preferably at least 0.3. ,
- the semiconductor layer sequence 9 of the optoelectronic component 12 contains, in particular, the active layer 10. Furthermore, the semiconductor layer sequence 9 may contain one or more further semiconductor layers 11.
- the active layer 10 of the optoelectronic component 12 preferably contains at least one layer of In z Ga z z N with z> 0.1, preferably z> 0.2 and particularly preferably z> 0.3.
- the further transfer layer 7 has a relatively large indium content.
- the indium content in the active layer 10 is preferably not more than 0.05, preferably not more than 0.02, greater than the indium content in the further transfer layer 7.
- the active layer 10 and the further transfer layer are particularly preferred 7 the same indium content.
- the active layer 10 may in one embodiment a
- electrical contacting can be the optoelectronic
- the optoelectronic component 12 may in particular be an LED or a semiconductor laser.
- the optoelectronic component 12 is preferably a
- Such large emission wavelengths can be in the based on a nitride compound semiconductor active layer in particular by the
- FIG. 13 shows by way of example the first method step in a further exemplary embodiment of the method
- the transfer layer 2 has been epitaxially grown on the growth substrate 1.
- Transfer layer 2 and / or the further transfer layer do not necessarily have to be formed by a single semiconductor layer in the method. Rather, the
- Transfer layer 2 and / or the further transfer layer comprise a plurality of sub-layers.
- the transfer layer 2 and / or the further transfer layer comprise a plurality of sub-layers.
- Transfer layer 2 and / or the further transfer layer may be configured as a superlattice structure 15.
- the transfer layer 2 has a in this embodiment
- the later applied further transfer layers 7 can also be designed as a superlattice structure 15. At this
- Embodiment are preferably the indium contents xl and x2 at each repetition of the growth of a further transfer layer 7 by a value between 0.02 and 0.05, preferably between 0.03 and 0.04, increased.
- Embodiment of the transfer layer 2 and / or the further transfer layer 7 as a superlattice structure 15 can Tension in the semiconductor material can be further reduced.
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014530192A JP5727677B2 (ja) | 2011-09-19 | 2012-09-12 | オプトエレクトロニクス部品の製造方法 |
US14/344,573 US9373747B2 (en) | 2011-09-19 | 2012-09-12 | Method for producing an optoelectronic component |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102011113775.4A DE102011113775B9 (de) | 2011-09-19 | 2011-09-19 | Verfahren zur Herstellung eines optoelektronischen Bauelements |
DE102011113775.4 | 2011-09-19 |
Publications (1)
Publication Number | Publication Date |
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WO2013041424A1 true WO2013041424A1 (de) | 2013-03-28 |
Family
ID=47008509
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/EP2012/067808 WO2013041424A1 (de) | 2011-09-19 | 2012-09-12 | Verfahren zur herstellung eines optoelektronischen bauelements |
Country Status (5)
Country | Link |
---|---|
US (1) | US9373747B2 (de) |
JP (1) | JP5727677B2 (de) |
DE (1) | DE102011113775B9 (de) |
TW (1) | TWI472060B (de) |
WO (1) | WO2013041424A1 (de) |
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JP6213046B2 (ja) * | 2013-08-21 | 2017-10-18 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP6686962B2 (ja) * | 2017-04-25 | 2020-04-22 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
Citations (3)
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US5374564A (en) | 1991-09-18 | 1994-12-20 | Commissariat A L'energie Atomique | Process for the production of thin semiconductor material films |
WO2006054737A1 (en) * | 2004-11-18 | 2006-05-26 | Showa Denko K.K. | Gallium nitride-based semiconductor stacked structure, method for fabrication thereof, gallium nitride-based semiconductor device and lamp using the device |
US20090117711A1 (en) * | 2005-09-01 | 2009-05-07 | Osram Opto Semiconductors Gmbh | Method for Laterally Cutting Through a Semiconductor Wafer and Optoelectronic Component |
Family Cites Families (13)
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JP4595207B2 (ja) | 2001-01-29 | 2010-12-08 | パナソニック株式会社 | 窒化物半導体基板の製造方法 |
TWI240434B (en) | 2003-06-24 | 2005-09-21 | Osram Opto Semiconductors Gmbh | Method to produce semiconductor-chips |
JP4414312B2 (ja) | 2003-09-26 | 2010-02-10 | エス. オー. アイ. テック シリコン オン インシュレーター テクノロジーズ | エピタキシャル成長のための基板の作製方法 |
DE102004062290A1 (de) | 2004-12-23 | 2006-07-06 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines Halbleiterchips |
JP4458116B2 (ja) * | 2007-05-30 | 2010-04-28 | 住友電気工業株式会社 | エピタキシャル層成長用iii族窒化物半導体層貼り合わせ基板および半導体デバイス |
TWI416615B (zh) | 2007-10-16 | 2013-11-21 | Epistar Corp | 分離二種材料系統之方法 |
JP5026946B2 (ja) | 2007-12-19 | 2012-09-19 | 古河電気工業株式会社 | 窒化物半導体単結晶基板製造方法 |
JP5297219B2 (ja) * | 2008-02-29 | 2013-09-25 | 信越化学工業株式会社 | 単結晶薄膜を有する基板の製造方法 |
DE102008019268A1 (de) | 2008-02-29 | 2009-09-03 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und Verfahren zur Herstellung eines optoelektronischen Bauelements |
JP2009245982A (ja) | 2008-03-28 | 2009-10-22 | Sumitomo Electric Ind Ltd | 窒化物発光素子 |
TWI407491B (zh) | 2008-05-09 | 2013-09-01 | Advanced Optoelectronic Tech | 分離半導體及其基板之方法 |
US9117944B2 (en) * | 2008-09-24 | 2015-08-25 | Koninklijke Philips N.V. | Semiconductor light emitting devices grown on composite substrates |
US8637383B2 (en) * | 2010-12-23 | 2014-01-28 | Soitec | Strain relaxation using metal materials and related structures |
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2011
- 2011-09-19 DE DE102011113775.4A patent/DE102011113775B9/de not_active Expired - Fee Related
-
2012
- 2012-08-31 TW TW101131741A patent/TWI472060B/zh not_active IP Right Cessation
- 2012-09-12 WO PCT/EP2012/067808 patent/WO2013041424A1/de active Application Filing
- 2012-09-12 JP JP2014530192A patent/JP5727677B2/ja not_active Expired - Fee Related
- 2012-09-12 US US14/344,573 patent/US9373747B2/en active Active
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US5374564A (en) | 1991-09-18 | 1994-12-20 | Commissariat A L'energie Atomique | Process for the production of thin semiconductor material films |
WO2006054737A1 (en) * | 2004-11-18 | 2006-05-26 | Showa Denko K.K. | Gallium nitride-based semiconductor stacked structure, method for fabrication thereof, gallium nitride-based semiconductor device and lamp using the device |
US20090117711A1 (en) * | 2005-09-01 | 2009-05-07 | Osram Opto Semiconductors Gmbh | Method for Laterally Cutting Through a Semiconductor Wafer and Optoelectronic Component |
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TWI472060B (zh) | 2015-02-01 |
TW201316547A (zh) | 2013-04-16 |
DE102011113775A1 (de) | 2013-03-21 |
JP2014526801A (ja) | 2014-10-06 |
DE102011113775B9 (de) | 2021-10-21 |
US20150044798A1 (en) | 2015-02-12 |
US9373747B2 (en) | 2016-06-21 |
JP5727677B2 (ja) | 2015-06-03 |
DE102011113775B4 (de) | 2021-07-22 |
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