JP5727677B2 - オプトエレクトロニクス部品の製造方法 - Google Patents
オプトエレクトロニクス部品の製造方法 Download PDFInfo
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- JP5727677B2 JP5727677B2 JP2014530192A JP2014530192A JP5727677B2 JP 5727677 B2 JP5727677 B2 JP 5727677B2 JP 2014530192 A JP2014530192 A JP 2014530192A JP 2014530192 A JP2014530192 A JP 2014530192A JP 5727677 B2 JP5727677 B2 JP 5727677B2
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- 230000005693 optoelectronics Effects 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims description 99
- 239000004065 semiconductor Substances 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 51
- 229910052738 indium Inorganic materials 0.000 claims description 44
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 44
- 238000000926 separation method Methods 0.000 claims description 23
- 150000002500 ions Chemical class 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 claims description 14
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 230000005855 radiation Effects 0.000 claims description 4
- -1 nitride compound Chemical class 0.000 description 16
- 238000010586 diagram Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 12
- 229910052594 sapphire Inorganic materials 0.000 description 7
- 239000010980 sapphire Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 239000002131 composite material Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229910052743 krypton Inorganic materials 0.000 description 2
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 2
- 229910052754 neon Inorganic materials 0.000 description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Recrystallisation Techniques (AREA)
- Led Devices (AREA)
Description
<関連出願>
本特許出願は、独国特許出願第102011 113 775.4号の優先権を主張し、この文書の開示内容は参照によって本明細書に組み込まれている。
Claims (15)
- オプトエレクトロニクス部品(12)を製造する方法であって、
a) InxGa1−xN(0<x<1)からなる少なくとも1層の半導体層を含む転送層(2)を、成長基板(1)の上にエピタキシャル成長させるステップと、
b) 前記転送層(2)の中にイオン(3)を注入して分離ゾーン(4)を形成するステップと、
c) 前記成長基板(1)とは反対側の前記転送層(2)の表面にキャリア基板(5)を貼り付けるステップと、
d) 熱処理によって、前記分離ゾーン(4)に沿って横方向に前記転送層(2)を分離するステップと、
e) InyGa1−yN(0<y≦1)からなる少なくとも1層の半導体層を含むさらなる転送層(7)を、前記キャリア基板(5)とは反対側の、前に成長させた前記転送層(2)の表面上に、成長させるステップであって、前記さらなる転送層(7)の前記少なくとも1層の半導体層が、前に成長させた前記転送層(2)の前記少なくとも1層の半導体層よりも高いインジウム割合yを有する、前記ステップと、
f) 前記さらなる転送層(7)の中にイオン(3)を注入して分離ゾーン(4)を形成するステップと、
g) 前記さらなる転送層(7)にさらなるキャリア基板(8)を貼り付けるステップと、
h) 熱処理によって、前記分離ゾーン(4)に沿って横方向に前記さらなる転送層(7)を分離するステップと、
i) 前記さらなるキャリア基板(8)とは反対側の前記さらなる転送層(7)の表面上に、活性層(10)を含む半導体積層体(9)をエピタキシャル成長させるステップと、
を含む方法。 - 前記ステップe)〜ステップh)が1回または何回か繰り返され、前記さらなる転送層(7)の前記少なくとも1層の半導体層それぞれが、それぞれの前に形成された前記転送層(2,7)の前記少なくとも1層の半導体層よりも高いインジウム割合yを有する、
請求項1に記載の方法。 - 前記さらなる転送層(7)の前記少なくとも1層の半導体層の前記インジウム割合yが、前に形成された前記転送層(2,7)の前記少なくとも1層の半導体層のインジウム割合よりも、それぞれ0.02〜0.05の範囲内の値だけ大きい、
請求項2に記載の方法。 - 前記繰返しの回数が少なくとも2回である、
請求項2または請求項3に記載の方法。 - 前記繰返しの回数が2〜8回の範囲内(両端値を含む)である、
請求項4に記載の方法。 - 最後に形成される前記転送層(7)が、InyGa1−yN(y≧0.1)を含んでいる、
請求項1から請求項5のいずれかに記載の方法。 - 最後に形成される前記転送層(7)が、InyGa1−yN(y≧0.3)を含んでいる、
請求項1から請求項6のいずれかに記載の方法。 - 前記活性層(10)が、InZGa1−zN(z≧0.1)からなる少なくとも1層を備えている、
請求項1から請求項7のいずれかに記載の方法。 - 前記活性層(10)が、InZGa1−zN(z≧0.3)からなる少なくとも1層を備えている、
請求項1から請求項8のいずれかに記載の方法。 - 前記活性層(10)が、450nm以上の波長を有する放射を放出するのに適している、
請求項1から請求項9のいずれかに記載の方法。 - 前記活性層(10)が、600nm以上の波長を有する放射を放出するのに適している、
請求項1から請求項10のいずれかに記載の方法。 - 前記転送層(2)もしくは前記少なくとも1層のさらなる転送層(7)またはその両方が、200nm〜2μmの範囲内(両端値を含む)の厚さを有する、
請求項1から請求項11のいずれかに記載の方法。 - 前記転送層(2)もしくは前記少なくとも1層のさらなる転送層(7)またはその両方が、単一の半導体層からなる、
請求項1から請求項12のいずれかに記載の方法。 - 前記転送層(2)もしくは前記少なくとも1層のさらなる転送層(7)またはその両方が、超格子構造(15)を形成する何層かのサブ層(16,17)を備えている、
請求項1から請求項13のいずれかに記載の方法。 - 前記キャリア基板(5)もしくは前記さらなるキャリア基板(8)またはその両方が、Ge、GaAs、AlN、Mo、Au、あるいはAuまたはMoとの合金を含んでいる、
請求項1から請求項14のいずれかに記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102011113775.4 | 2011-09-19 | ||
DE102011113775.4A DE102011113775B9 (de) | 2011-09-19 | 2011-09-19 | Verfahren zur Herstellung eines optoelektronischen Bauelements |
PCT/EP2012/067808 WO2013041424A1 (de) | 2011-09-19 | 2012-09-12 | Verfahren zur herstellung eines optoelektronischen bauelements |
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JP2014526801A JP2014526801A (ja) | 2014-10-06 |
JP5727677B2 true JP5727677B2 (ja) | 2015-06-03 |
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Country Status (5)
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US (1) | US9373747B2 (ja) |
JP (1) | JP5727677B2 (ja) |
DE (1) | DE102011113775B9 (ja) |
TW (1) | TWI472060B (ja) |
WO (1) | WO2013041424A1 (ja) |
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JP6213046B2 (ja) * | 2013-08-21 | 2017-10-18 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP6686962B2 (ja) * | 2017-04-25 | 2020-04-22 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
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FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JP4595207B2 (ja) * | 2001-01-29 | 2010-12-08 | パナソニック株式会社 | 窒化物半導体基板の製造方法 |
TWI240434B (en) | 2003-06-24 | 2005-09-21 | Osram Opto Semiconductors Gmbh | Method to produce semiconductor-chips |
JP4414312B2 (ja) | 2003-09-26 | 2010-02-10 | エス. オー. アイ. テック シリコン オン インシュレーター テクノロジーズ | エピタキシャル成長のための基板の作製方法 |
DE112005002838T5 (de) | 2004-11-18 | 2007-11-15 | Showa Denko K.K. | Halbleiterstapelstruktur auf Basis von Galliumnitrid, Verfahren zu dessen Herstellung, Halbleitervorrichtung auf Basis von Galliumnitrid und Lampe unter Verwendung der Vorrichtung |
DE102004062290A1 (de) | 2004-12-23 | 2006-07-06 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines Halbleiterchips |
DE102005052358A1 (de) | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement |
JP4458116B2 (ja) | 2007-05-30 | 2010-04-28 | 住友電気工業株式会社 | エピタキシャル層成長用iii族窒化物半導体層貼り合わせ基板および半導体デバイス |
TWI416615B (zh) | 2007-10-16 | 2013-11-21 | Epistar Corp | 分離二種材料系統之方法 |
JP5026946B2 (ja) | 2007-12-19 | 2012-09-19 | 古河電気工業株式会社 | 窒化物半導体単結晶基板製造方法 |
DE102008019268A1 (de) | 2008-02-29 | 2009-09-03 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und Verfahren zur Herstellung eines optoelektronischen Bauelements |
JP5297219B2 (ja) * | 2008-02-29 | 2013-09-25 | 信越化学工業株式会社 | 単結晶薄膜を有する基板の製造方法 |
JP2009245982A (ja) | 2008-03-28 | 2009-10-22 | Sumitomo Electric Ind Ltd | 窒化物発光素子 |
TWI407491B (zh) | 2008-05-09 | 2013-09-01 | Advanced Optoelectronic Tech | 分離半導體及其基板之方法 |
US9117944B2 (en) | 2008-09-24 | 2015-08-25 | Koninklijke Philips N.V. | Semiconductor light emitting devices grown on composite substrates |
US8637383B2 (en) * | 2010-12-23 | 2014-01-28 | Soitec | Strain relaxation using metal materials and related structures |
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2011
- 2011-09-19 DE DE102011113775.4A patent/DE102011113775B9/de not_active Expired - Fee Related
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2012
- 2012-08-31 TW TW101131741A patent/TWI472060B/zh not_active IP Right Cessation
- 2012-09-12 US US14/344,573 patent/US9373747B2/en active Active
- 2012-09-12 WO PCT/EP2012/067808 patent/WO2013041424A1/de active Application Filing
- 2012-09-12 JP JP2014530192A patent/JP5727677B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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TW201316547A (zh) | 2013-04-16 |
JP2014526801A (ja) | 2014-10-06 |
DE102011113775B4 (de) | 2021-07-22 |
US20150044798A1 (en) | 2015-02-12 |
TWI472060B (zh) | 2015-02-01 |
WO2013041424A1 (de) | 2013-03-28 |
US9373747B2 (en) | 2016-06-21 |
DE102011113775B9 (de) | 2021-10-21 |
DE102011113775A1 (de) | 2013-03-21 |
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