WO2013032279A1 - Procédé de fabrication de substrat pour boîtiers de puces - Google Patents

Procédé de fabrication de substrat pour boîtiers de puces Download PDF

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Publication number
WO2013032279A1
WO2013032279A1 PCT/KR2012/007002 KR2012007002W WO2013032279A1 WO 2013032279 A1 WO2013032279 A1 WO 2013032279A1 KR 2012007002 W KR2012007002 W KR 2012007002W WO 2013032279 A1 WO2013032279 A1 WO 2013032279A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit pattern
chip packages
pattern layers
layers
plating
Prior art date
Application number
PCT/KR2012/007002
Other languages
English (en)
Inventor
Tea Hyuk Kang
Original Assignee
Lg Innotek Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Innotek Co., Ltd. filed Critical Lg Innotek Co., Ltd.
Publication of WO2013032279A1 publication Critical patent/WO2013032279A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages

Definitions

  • the present invention relates to a method of manufacturing a substrate for chip packages.
  • a silicon chip or an LED (light emitting diode) chip, a smart IC chip and the like are bonded onto a substrate using a wire bonding method or an LOC (lead on chip) bonding method.
  • FIG. 1 is a view showing a conventional process of manufacturing a substrate for chip packages.
  • an insulation layer 110 is first prepared (S1).
  • the insulation layer 110 may be formed of an insulating film, for example, a polyimide film.
  • via holes 112 are formed in the insulation layer 110 (S2).
  • a metal layer 120 is laminated on the insulation layer 120 (S3).
  • the metal layer 120 may be composed of Cu.
  • a surface of the metal layer is activated through various chemical treatments, a photoresist is then applied thereto, and exposure and development processes are performed.
  • a necessary circuit is formed by an etching process, and a circuit pattern layer 120 is formed by peeling off the photoresist (S4).
  • one surface of the circuit pattern layer 120 namely, an upper surface becomes a contact area.
  • Another surface of the circuit pattern layer 120 namely, a lower surface is bonded to the substrate of chip packages. Therefore, the surface bonded to the substrate of the circuit pattern layer 120 becomes a bonding area.
  • the contact area of the circuit pattern layer 120 may be plated with Ni, Pd, and Au in order.
  • the bonding area of the circuit pattern layer 120 may be plated with Ni, and Au in order.
  • the insulation layer 110 which is exposed to the outside by a circuit pattern of the insulation layer 110 and the circuit pattern layer 120 may be composed of an insulating material such as polyimide or resins. Thus, the insulation layer is not plated in principle.
  • the bonding area of the circuit pattern layer 120 and the contact area of the circuit pattern layer 120 may be plated with different methods or materials from each other in order to implement their own physical properties or desired characteristics.
  • the bonding area of the circuit pattern layer 120 is plated, the bonding area of the circuit pattern layer 120 is masked on the insulation layer 110 using a first mask part 120 so that the plating of the contact area of the circuit pattern layer 120 has no effect on the bonding area of the circuit pattern layer 120, and the contact area of the circuit pattern layer 120 is plated (S5).
  • the present invention has been made keeping in mind the above problems, and an aspect of the present invention provides a method of manufacturing a substrate for chip packages which simplifies processes of the substrate for chip packages.
  • a method of manufacturing a substrate for chip packages comprising: forming two substrates for chip packages comprising circuit pattern layers having bonding areas on one surface and contact areas on another surface, insulation layers bonded to the bonding areas of the circuit pattern layers, respectively; attaching the insulation layers of the two substrates for chip packages to both surfaces of a first double-sided adhesive sheet, respectively; plating the contact areas of the circuit pattern layers of the two substrates for chip packages; separating the insulation layers from the first double-sided adhesive sheet; attaching the contact areas of the circuit pattern layers of the two substrates for chip packages to both surfaces of a second double-sided adhesive sheet, respectively; and plating the bonding areas of the circuit pattern layers of the two substrates for chip packages.
  • the method of manufacturing the substrate for chip packages may further include separating the contact areas of the circuit pattern layers from the second double-sided adhesive sheet.
  • the method of manufacturing the substrate for chip packages may further include plating the contact areas of the circuit pattern layers using Ni, Pd, and Au in order.
  • the method of manufacturing the substrate for chip packages may further include plating the bonding areas of the circuit pattern layers using Ni and Au in order.
  • the plating of the contact areas of the circuit pattern layers may be performed by a different method from the plating of the bonding areas of the circuit pattern layers.
  • the first double-sided adhesive sheet and the second double-sided adhesive sheet may be implemented as one sheet.
  • the forming of the substrate for chip packages may include forming via holes in the insulation layer, laminating a metal layer on one surface of the insulation layer, and forming the circuit pattern layer by patterning the metal layer.
  • the metal layer may be composed of Cu.
  • the metal layer may be patterned by an etching process.
  • the contact areas or the bonding areas of two substrates for chip packages can be plated at a time using the double-sided adhesive film or the sheet without a masking process.
  • FIG. 1 is a view showing a conventional process of manufacturing a substrate for chip packages.
  • FIG. 2 is a view showing a process of manufacturing a substrate for chip packages according to a preferred exemplary embodiment of the present invention.
  • FIG. 2 is a view showing a process of manufacturing a substrate for chip packages according to a preferred exemplary embodiment of the present invention.
  • an insulation layer 210 is first prepared (S10).
  • the insulation layer 210 may be formed of a polyimide film.
  • via holes 112 are formed in the insulation layer 210 (S20).
  • the via holes formed by passing through the insulation layer 210 may include an optical device, namely, via holes on which chips are mounted, via holes for electrically connecting each layer, thermal via holes for easily diffusing heat, and via holes which become a basis for the array of each layer.
  • a metal layer 220 is laminated on the insulation layer 220 (S30).
  • the metal layer 220 may be composed of Cu.
  • a surface of the metal layer is activated through various chemical treatments, a photoresist is then applied thereto, and exposure and development processes are performed.
  • a necessary circuit is formed by an etching process, and a circuit pattern layer 220 is formed by peeling off the photoresist (S40). That is, the circuit pattern layer is formed by patterning the metal layer 220.
  • one surface of the circuit pattern layer 220 namely, an upper surface becomes a contact area.
  • Another surface of the circuit pattern layer 220 namely, a lower surface is bonded to the substrate of LED packages. Therefore, the surface which is bonded to the substrate of the circuit pattern layer 220 becomes a bonding area.
  • the insulation layer 210 in which the via holes 212 are formed, and a substrate for chip packages 310 to which the circuit pattern layer 220 are bonded may be manufactured.
  • the insulation layer 210 in which the via holes 212 are formed, and a substrate for chip packages 310 to which the circuit pattern layer 220 are bonded may be manufactured.
  • at least two substrates for chip packages 310 and 320 may be manufactured.
  • the insulation layers 210 of the two substrates for the chip packages manufactured as described above are attached to a film whose both surfaces are coated with an adhesive or both surfaces of a double-sided adhesive sheet 230, respectively (S50).
  • each insulation layer 210 of the two substrates for chip packages 310 is attached to the film or the both surfaces of the sheet 230. That is, the insulation layer 210 of one substrate for chip packages 310 is attached to the adhesive film or one surface of the sheet 230.
  • the insulation layer 210 of another substrate for chip packages 320 is attached to the adhesive film or another surface of the sheet 230.
  • the insulation layers of the substrate for chip packages 310 and 320 are masked by the adhesive film or the sheet 230.
  • a part of the circuit pattern layer 220 which is exposed by the via holes of the insulation layers 210, namely, the bonding areas of the circuit pattern layer 220 are also masked.
  • the contact area of the circuit pattern layer 220 of one substrate for chip packages 310, and the contact area of the circuit pattern layer 220 of another one substrate for chip packages 320 are exposed to the outside. Then, the contact areas of the circuit pattern layer 220 of two substrates for chip packages 310 and 320 may be plated at a time and using the same method.
  • the contact areas of the circuit pattern layer 220 are plated several times using a plurality of metals, for example, Ni, Pd, and Au in order (S50).
  • the present invention is not limited to this, and the circuit pattern layer 220 may be plated using one metal.
  • the insulation layer 210 which is exposed to the outside by a circuit pattern of the circuit pattern layer 120 may be composed of an insulating material such as polyimide or resins. Thus, the insulation layer is not plated in principle.
  • the two substrates for chip packages 310 and 320 are separated from the adhesive film or the sheet 230 (S60).
  • the contact areas of the circuit pattern layer 220 of the two substrates for chip packages 310 and 320 are attached to a film whose both surfaces are coated with an adhesive, or both surfaces of a double-sided adhesive sheet 240, respectively (S70).
  • each circuit pattern layer 220 of the two substrates for chip packages 310 and 320 are attached to the film or both surfaces of the sheet 240. That is, the contact area of the circuit pattern layer 220 of one substrate for chip packages 310 is attached to the adhesive film or one surface of the sheet 240. Furthermore, the contact area of the circuit pattern layer 220 of another one substrate for chip packages 320 is attached to the adhesive film or another surface of the sheet 240.
  • the contact areas of the circuit pattern layers of the substrates for chip packages 310 and 320 are masked by the adhesive film or the sheet 240.
  • some parts of the circuit pattern layers are exposed by the via holes of the insulation layers 210.
  • the bonding area of the circuit pattern layer 220 of one substrate for chip packages 310, and the bonding area of the circuit pattern layer 220 of another one substrate for chip packages 320 are exposed to the outside.
  • the bonding areas of the circuit pattern layer 220 of two substrates for chip packages 310 and 320 may be plated at a time and using the same method.
  • the bonding areas of the circuit pattern layer 220 are plated several times using the plurality of metals, for example, Ni, and Au in order.
  • the present invention is not limited to this, and the bonding area of the circuit pattern layer 220 may be plated using one metal.
  • the insulation layer 110 may be composed of the insulating material such as polyimide or resins. Thus, the insulation layer is not plated in principle.
  • the contact area of the circuit pattern layer 220 is plated, and thereafter, the bonding area of the circuit pattern layer 220 is plated, but the present invention is not limited to this.
  • the orders of the processes of plating the contact areas of the circuit pattern layer 220 and the bonding areas of the circuit pattern layer 220 may be changed according to a condition for the manufacturing process or other conditions.
  • the adhesive film or the sheet 230 attached to the insulation layers 210 is different from the adhesive film or the sheet 240 attached to the contact areas of the circuit pattern layers.
  • these adhesive sheets 230 and 240 may be implemented as one adhesive sheet.
  • these adhesive sheets 230 and 240 may be formed of a same material as each other. For example, after plating the contact areas of the circuit pattern layers or after plating the bonding areas of the circuit pattern layers 220, the insulation layers or the circuit pattern layers are separated from the adhesive film or the sheet so that they can be again used.
  • the contact areas or the bonding areas of the two substrates for chip packages may be plated at a time using the double-sided adhesive film or the sheet without any masking process.
  • the processes for plating the contact areas or the bonding areas of the two substrates for chip packages are simplified, thereby reducing the costs and time.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un substrat pour boîtiers de puces, qui consiste à: former deux substrats pour boîtiers de puces comprenant des couches de motifs de circuit présentant deux zones de liaison sur une de ses surfaces, et des zones de contact sur l'autre surface; et des couches isolantes liées aux zones de liaison des couches de motifs de circuit, respectivement; fixer les couches isolantes des deux substrats pour boîtiers de puces aux deux surfaces d'une première feuille adhésive double face, respectivement; plaquer les surfaces de contact des couches de motifs de circuit des deux substrats pour boîtiers de puces séparant les couches isolantes de la première feuille adhésive double face; fixer les zones de contact des couches de motifs de circuit des deux substrats pour boîtiers de puces aux deux surfaces d'une seconde feuille adhésive double face, respectivement; et plaquer les zones de liaison des couches de motifs de circuit des deux substrats pour boîtiers de puces.
PCT/KR2012/007002 2011-09-02 2012-08-31 Procédé de fabrication de substrat pour boîtiers de puces WO2013032279A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020110089070A KR101776322B1 (ko) 2011-09-02 2011-09-02 칩 패키지 부재 제조 방법
KR10-2011-0089070 2011-09-02

Publications (1)

Publication Number Publication Date
WO2013032279A1 true WO2013032279A1 (fr) 2013-03-07

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PCT/KR2012/007002 WO2013032279A1 (fr) 2011-09-02 2012-08-31 Procédé de fabrication de substrat pour boîtiers de puces

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KR (1) KR101776322B1 (fr)
TW (1) TWI486107B (fr)
WO (1) WO2013032279A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105701532B (zh) * 2014-11-25 2018-09-11 茂邦电子有限公司 晶片卡的晶片封装件及其成型用片状封装板与成型方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100214562B1 (ko) * 1997-03-24 1999-08-02 구본준 적층 반도체 칩 패키지 및 그 제조 방법
JP2003179188A (ja) * 2002-11-29 2003-06-27 Hitachi Chem Co Ltd 半導体パッケージ用基板
US20060131755A1 (en) * 2004-03-31 2006-06-22 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate
KR20100129784A (ko) * 2008-05-09 2010-12-09 고쿠리츠 다이가쿠 호진 큐슈 코교 다이가쿠 칩 사이즈 양면 접속 패키지 및 그의 제조 방법
US20100314037A1 (en) * 2009-06-11 2010-12-16 Unimicron Technology Corporation Method for fabricating packaging substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004296481A (ja) * 2003-03-25 2004-10-21 Nitto Denko Corp 多層配線回路基板
TWI402015B (zh) * 2009-05-27 2013-07-11 Chuan Ling Hu Integration of surface mount components of the packaging structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100214562B1 (ko) * 1997-03-24 1999-08-02 구본준 적층 반도체 칩 패키지 및 그 제조 방법
JP2003179188A (ja) * 2002-11-29 2003-06-27 Hitachi Chem Co Ltd 半導体パッケージ用基板
US20060131755A1 (en) * 2004-03-31 2006-06-22 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate
KR20100129784A (ko) * 2008-05-09 2010-12-09 고쿠리츠 다이가쿠 호진 큐슈 코교 다이가쿠 칩 사이즈 양면 접속 패키지 및 그의 제조 방법
US20100314037A1 (en) * 2009-06-11 2010-12-16 Unimicron Technology Corporation Method for fabricating packaging substrate

Also Published As

Publication number Publication date
TWI486107B (zh) 2015-05-21
KR101776322B1 (ko) 2017-09-07
KR20130025640A (ko) 2013-03-12
TW201330742A (zh) 2013-07-16

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