WO2013026277A1 - 多层半导体衬底的制备方法 - Google Patents

多层半导体衬底的制备方法 Download PDF

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Publication number
WO2013026277A1
WO2013026277A1 PCT/CN2012/073866 CN2012073866W WO2013026277A1 WO 2013026277 A1 WO2013026277 A1 WO 2013026277A1 CN 2012073866 W CN2012073866 W CN 2012073866W WO 2013026277 A1 WO2013026277 A1 WO 2013026277A1
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semiconductor substrate
bonding
multilayer
rinsing
fabricating
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PCT/CN2012/073866
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English (en)
French (fr)
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张峰
叶斐
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上海新傲科技股份有限公司
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Publication of WO2013026277A1 publication Critical patent/WO2013026277A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

  • the present invention relates to a method of fabricating a multilayered semiconductor substrate, and more particularly to a method of fabricating a multilayer semiconductor substrate that is low cost, high efficiency, and process stable.
  • Thick-film epitaxial wafers are widely used in circuits such as power supply control in integrated circuits.
  • the so-called thick-film epitaxial wafers are epitaxial layers having different resistivities on the surface of the semiconductor substrate, and the thickness of the epitaxial layer is usually greater than 100 ⁇ m.
  • the main epitaxial fabrication technique uses a planar epitaxial furnace to prepare such substrates by preparing epitaxial layers having different resistivities by epitaxial processes on a semiconductor substrate.
  • the disadvantage of the epitaxial process is that the time is long, the single furnace process time exceeds 2.5 hours, and the production efficiency is low, the preparation cost is high, and the sheet thickness uniformity can only be controlled at about 5%.
  • the technical problem to be solved by the present invention is to provide a method for preparing a multilayer semiconductor substrate which is low in cost, high in efficiency, and stable in process.
  • the present invention provides a method of fabricating a multilayer semiconductor substrate, comprising the steps of: providing a first semiconductor substrate and a second semiconductor substrate; and disposing the first semiconductor substrate and the second semiconductor substrate At least one of the immersion in an oxidizing solution or an oxidizing gas to form an oxidized bonding medium layer on the surface; and bonding the dielectric layer as an intermediate layer to bond the first semiconductor substrate and the second semiconductor substrate together.
  • the first semiconductor substrate and the second semiconductor substrate are made of the same material and have different resistivities or have different conductivity types; the first semiconductor substrate and the second semiconductor substrate
  • the material of the semiconductor substrate is single crystal silicon.
  • the first semiconductor substrate and the second semiconductor substrate are made of different materials, and the specific process parameters of the cleaning are washed with a hydrofluoric acid solution for more than 1 minute, and then deionized water is used. Wash for no more than 10 minutes.
  • a step of performing annealing on a pair of bonding interfaces is further included.
  • the first half of the thinning is further included The step of a conductor substrate or a second semiconductor substrate.
  • An advantage of the present invention is to provide a method for fabricating a multilayer semiconductor substrate by immersing a first semiconductor substrate and/or a second semiconductor substrate in an oxidizing solution or an oxidizing gas to form a natural oxide layer, and performing bonding
  • the substrate has a multilayer structure, and the electrical and crystallographic properties of the upper and lower layers are determined by the previous first semiconductor substrate and the second semiconductor substrate, and the method provided has low cost, high efficiency, and stable process.
  • the present invention further proposes the step of performing annealing after bonding, which can further promote the fusion at the lattice scale between the two layers in the multilayer semiconductor substrate, and it can be clearly seen from the obtained TEM photograph that the bonding interface oxygen has been Ablation, the lattice is continuous.
  • Figure 1 is a schematic illustration of the implementation steps of the specific embodiment of the present invention.
  • FIGS. 2A through 2E are schematic views of processes of the specific embodiment of the present invention.
  • Figure 3 is a transmission electron microscope (TEM) photograph of a multilayer semiconductor substrate at a multilayer interface in accordance with an embodiment of the present invention.
  • Step S10 providing a first semiconductor substrate and a second semiconductor substrate
  • Step S11 the first semiconductor substrate and the second semiconductor lining
  • the bottom is rinsed with a hydrofluoric acid solution and deionized water to form an oxidized bonding medium layer on the surface to be cleaned
  • step S12 the first semiconductor substrate and the second semiconductor substrate are bonded with the bonding medium layer as an intermediate layer Bonding together
  • step S13 performing annealing on the bonding interface
  • step S14 thinning the first semiconductor substrate or the second semiconductor substrate.
  • FIGS. 2A to 2E are schematic views of the process of the present embodiment.
  • a first semiconductor substrate 100 and a second semiconductor substrate 200 are provided.
  • the above two semiconductor substrates are intended to respectively constitute two different semiconductor layers of the multilayer semiconductor substrate, so that the first semiconductor substrate 100 and the second semiconductor substrate 200 may be composed of the same or different materials, both being the same In the case of material composition, each should have a different resistivity. Or have different conductivity types, or there are differences in other crystallographic or electrical indicators. In the case where the materials of the first semiconductor substrate 100 and the second semiconductor substrate 200 are the same, the material of both may be, for example, single crystal silicon.
  • the first semiconductor substrate 100 and the second semiconductor substrate 200 are rinsed with a hydrofluoric acid solution and deionized water to form an oxidized bonding medium layer 101 on the surface.
  • the specific process parameters for cleaning are HF cleaning for more than 1 minute, and then washing with deionized water for no more than 10 minutes, and the thickness of the obtained bonding medium layer is usually less than 0.5 nm.
  • the above cleaning time is closely related to the concentration of the hydrofluoric acid solution, the oxygen content in the deionized water, the temperature, and the substrate material, and needs to be adjusted by those skilled in the art according to the thickness of the oxide layer actually obtained.
  • HF is used to clean the surface.
  • Increasing the hydrofluoric acid time is advantageous for obtaining a clean surface, and increasing the time of deionized water cleaning is advantageous for increasing the thickness of the surface oxidized bonding medium layer 101.
  • the step of rinsing with an ammonium hydroxide solution and the step of rinsing with a hydrogen chloride solution may be further included, the purpose of cleaning the two solutions is to improve the cleanliness of the surface, the two cleaning liquids.
  • the concentration and the cleaning time can be determined experimentally, and it is preferred to not significantly thicken the bonding medium layer. The specific embodiment is described by taking the first semiconductor substrate 100 as an example.
  • the bonding medium layer may be formed on the surface of the second semiconductor substrate 200, or in the first semiconductor substrate 100 and the first semiconductor substrate 100.
  • the surfaces of the two semiconductor substrates 200 each form a bonding medium layer.
  • a bonding medium layer In immersing the first semiconductor substrate 100 in the oxidizing solution, a bonding medium layer should be formed on both surfaces thereof, and only one surface of the bonding medium layer 101 is shown in Fig. 2B for the convenience of the subsequent steps. .
  • the bonding medium layer is naturally formed in an oxidizing solution or an oxidizing gas, the thickness is usually less than 0.5 nm, and a thicker bonding medium layer 101 is drawn in FIG. 2B for the sake of clarity. It does not mean that the thickness between the bonding medium layer 101 and the first semiconductor substrate 100 has such a proportional relationship, and is merely an illustration made for convenience of description.
  • the first semiconductor substrate 100 and the second semiconductor substrate 120 are bonded together with the bonding medium layer 101 as an intermediate layer.
  • the bonding surface should be selected according to other properties of the surface, such as whether it is a polished surface, and of course any surface can be selected as a key for a double-sided polishing substrate. Combined surface. Since the first semiconductor substrate 100 is immersed in an oxidizing solution or an oxidizing gas in the previous step, no additional contamination is applied to the surface of the substrate, and it is immersed in the oxidizing solution and even the surface is cleaned. The effect of the bonding step can be implemented immediately after the implementation of step S11 without having to perform an additional cleaning step.
  • the first semiconductor substrate 100 and the second semiconductor substrate 200 after bonding are formed into a plurality of semiconductor substrates. After subsequent thinning and polishing, the substrate has a multilayer structure and two layers of upper and lower layers.
  • the electrical and crystallographic properties are determined by the previous first semiconductor substrate 100 and second semiconductor substrate 200. If the previous first semiconductor substrate 100 and the second semiconductor substrate 200 have different electrical conductivities, the obtained multilayered semiconductor substrate also has a plurality of layers of electrical conductivity.
  • the surface of the first semiconductor substrate 100 or the second semiconductor substrate 120 may be further selectively doped, and may be selectively implanted or diffused.
  • the doped first semiconductor substrate 100 or the second semiconductor substrate 120 itself has a two-layer structure having different electrical conductivity, and then the two are bonded together, that is, three layers are formed (select one to perform doping Even a four-layer (both doped) semiconductor substrate, for a three-layer semiconductor structure with a heavily doped interlayer in the middle, has an important application value for power devices such as IGBTs.
  • the bonding interface is annealed with reference to step S13.
  • the annealing temperature is preferably greater than 1000 ° C, so that the bonding interface layer 101 is ablated and latticed at the interface after high temperature hardening annealing, and the subsequent device performance is not affected. Since the bonding medium layer 101 at the interface is formed by natural oxidation and has a small thickness, the oxygen atoms contained therein can be diffused into the crystal lattice during the annealing process, diluted by the lattice atoms, and the first semiconductor is further The crystal lattice of the substrate 100 and the second semiconductor substrate 200 can remain continuous at the interface.
  • Figure 3 is a transmission electron microscope (TEM) photograph of the interface after annealing, from which it can be clearly seen that the bonding interface oxygen has been ablated and the lattice is continuous. Therefore, the annealing step can further promote the fusion between the two layers in the multilayer semiconductor substrate at the lattice scale.
  • TEM transmission electron microscope
  • the first semiconductor substrate 100 and the second semiconductor substrate 200 are thinned.
  • the thickness of the thinning is determined according to the needs of the actual application. Usually, during the wafer processing, the thickness is given by the customer who needs the wafer.
  • the thinning can be first performed by mechanical thinning and then chemical mechanical polishing. Surface finishing. Can be further implemented as needed before thinning Chamfering process.
  • a semiconductor substrate may be further introduced to repeatedly perform the above-described natural oxidation process, bonding process, and doping process to further form a semiconductor substrate having more layers.

Abstract

提供一种多层半导体衬底的制备方法，包括歩骤：提供第一半导体衬底和第二半导体衬底（S10），将第一半导体衬底和第二半导体衬底中的至少一个浸入氧化性溶液或者氧化性气体中，以在表面形成氧化的键合媒介层（S11），以键合媒介层为中间层，将第一半导体衬底和第二半导体衬底键合在一起（S12）。

Description

多层半导体衬底的制备方法
技术领域
本发明是关于多层半导体衬底的制备方法， 特别涉及低成本、 高效率且 工艺稳定的多层半导体衬底的制备方法。
背景技术
集成电路中电源控制等电路广泛使用厚膜外延片， 所谓厚膜外延片是指 在半导体衬底表面外延一层具有不同电阻率的外延层， 改外延层厚度通常大 于 100um。 目前主要的外延制备技术采用平板式外延炉制备该类衬底， 通过 在一半导体衬底上通过外延工艺制备具有不同电阻率的外延层。 外延工艺的 缺点在于时间长， 单炉工艺时间超过 2.5小时， 并且生产效率低， 制备成本 高， 片内厚度均匀性仅能控制在 5%左右。
发明内容
本发明所要解决的技术问题是， 提供一种低成本、 高效率且工艺稳定的 多层半导体衬底的制备方法。
为了解决上述问题， 本发明提供了一种多层半导体衬底的制备方法， 包 括如下步骤： 提供第一半导体衬底和第二半导体衬底； 将第一半导体衬底和 第二半导体衬底中的至少一个浸入氧化性溶液或者氧化性气体中， 以在表面 形成氧化的键合媒介层； 以键合媒介层为中间层， 将第一半导体衬底和第二 半导体衬底键合在一起。
作为可选的技术方案， 所述第一半导体衬底和第二半导体衬底由相同的 材料构成， 且具有不同的电阻率， 或者具有不同的导电类型； 所述第一半导 体衬底和第二半导体衬底的材料为单晶硅。
作为可选的技术方案， 所述第一半导体衬底和第二半导体衬底由不同的 材料构成， 所述清洗的具体的工艺参数是采用氢氟酸溶液清洗 1分钟以上， 再采用去离子水清洗不超过 10分钟。
作为可选的技术方案， 在键合步骤实施完毕后， 进一步包括一对键合界 面实施退火的步骤。
作为可选的技术方案， 在键合步骤实施完毕后， 进一步包括减薄第一半 导体衬底或者第二半导体衬底的步骤。
本发明的优点在于提出了一种多层半导体衬底的制备方法， 将第一半导 体衬底和 /或第二半导体衬底浸入氧化性溶液或者氧化性气体中形成自然氧 化层， 并实施键合， 此衬底即具有多层结构， 且上下两层的电学和晶体学性 质由之前的第一半导体衬底和第二半导体衬底决定， 所提供的方法具有低成 本、 高效率且工艺稳定的优点。
本发明进一步提出了在键合之后实施退火的步骤， 可以进一步促进多层 半导体衬底中两层之间在晶格尺度上的融合， 从所获得的 TEM 照片可以明 显看到键合界面氧已经消融， 晶格是连续的。
附图说明
附图 1是本发明所述具体实施方式的实施步骤示意图。
附图 2A至附图 2E是本发明所述具体实施方式的工艺示意图。
附图 3是本发明所述具体实施方式中多层半导体衬底在多层界面处的透 射电子显微镜 （TEM) 照片。
具体实施方式
接下来结合附图详细介绍本发明所述一种多层半导体衬底的制备方法的 具体实施方式。
附图 1所示是本发明所述具体实施方式的实施步骤示意图， 包括： 步骤 S10, 提供第一半导体衬底和第二半导体衬底； 步骤 S11 , 将第一半导体衬底 和第二半导体衬底采用氢氟酸溶液和去离子水冲洗， 以在被清洗的表面形成 氧化的键合媒介层； 步骤 S12, 以键合媒介层为中间层， 将第一半导体衬底 和第二半导体衬底键合在一起； 步骤 S13 , 对键合界面实施退火； 步骤 S14, 减薄第一半导体衬底或者第二半导体衬底。
附图 2A至附图 2E所示是本具体实施方式的工艺示意图。
附图 2A所示， 参考步骤 S10, 提供第一半导体衬底 100和第二半导体 衬底 200。 上述两半导体衬底意在分别构成多层半导体衬底的两个不同的半 导体层， 故第一半导体衬底 100和第二半导体衬底 200可以由相同或者不同 的材料构成，在两者是相同材料构成的情况下，应当各自具有不同的电阻率， 或者具有不同的导电类型， 或者在其他晶体学或者电学指标上存在差异。 在 第一半导体衬底 100和第二半导体衬底 200的材料相同的情况下， 两者的材 料例如可以是单晶硅。
附图 2B所示， 参考步骤 S11 ,将第一半导体衬底 100和第二半导体衬底 200采用氢氟酸溶液和去离子水冲洗， 以在表面形成氧化的键合媒介层 101。 以单晶硅衬底为例， 清洗的具体的工艺参数是 HF清洗 1分钟以上， 再采用 去离子水清洗不超过 10分钟，所获得的键合媒介层的厚度通常是小于 0.5nm 的。 以上清洗时间和氢氟酸溶液浓度、 去离子水中的含氧量、 温度以及衬底 材料都具有密切关系， 需要本领域内技术人员根据实际所获得的氧化层厚度 进行调整。 一般来说， HF 是为了对表面起到清洁作用， 增加氢氟酸时间有 利于获得清洁的表面， 而增加去离子水清洗的时间有利于增加表面氧化的键 合媒介层 101 的厚度。 在上述 HF清洗和去离子水冲洗之间， 还可以进一步 包括一氢氧化铵溶液冲洗的步骤和一氯化氢溶液冲洗的步骤， 上述两种溶液 清洗的目的在于提高表面的清洁度， 两种清洗液的浓度以及清洗时间可以通 过实验确定， 以不明显增厚键合媒介层为宜。 本具体实施方式以第一半导体 衬底 100为例进行描述， 在其他的实施方式中， 也可以是在第二半导体衬底 200表面形成键合媒介层，或者在第一半导体衬底 100和第二半导体衬底 200 的表面均形成键合媒介层。 在将第一半导体衬底 100浸入氧化性溶液中， 应 当在其两个表面均形成键合媒介层， 附图 2B 中为了方便后续步骤的叙述， 仅示出了一个表面的键合媒介层 101。 由于键合媒介层是在氧化性溶液或者 氧化性气体中自然形成的， 故厚度通常是小于 0.5nm的， 附图 2B中为了清 晰起见而绘制了一个较厚的键合媒介层 101， 这并不意味着键合媒介层 101 与第一半导体衬底 100之间的厚度是具有如此的比例关系的， 而只是为了方 便表述而做出的示意。
附图 2C所示， 参考步骤 S12, 以键合媒介层 101为中间层， 将第一半导 体衬底 100和第二半导体衬底 120键合在一起。 对于两个表面都具有键合媒 介层的情况而言， 应当根据表面的其他性质， 例如是否是抛光的表面来选择 键合面， 当然对于双面抛光衬底而言可以选取任何一个表面作为键合表面。 由于前一步骤中将第一半导体衬底 100浸入氧化性溶液或者氧化性气体中， 并未对衬底表面带来任何额外的沾污， 将其浸入氧化性溶液中甚至还有对表 面进行清洁的作用， 故本键合步骤可以在步骤 S11实施完毕后立即实施而不 必再实施额外的清洗步骤。 键合完毕后的第一半导体衬底 100和第二半导体 衬底 200即形成了多层的半导体衬底， 在后续减薄并抛光之后， 此衬底即具 有多层结构， 且上下两层的电学和晶体学性质由之前的第一半导体衬底 100 和第二半导体衬底 200决定。 如果之前的第一半导体衬底 100和第二半导体 衬底 200具有不同的电导率， 则所获得的多层半导体衬底也具有多层的电导 率。
在步骤 S11实施之前， 还可以进一步选择对第一半导体衬底 100或第二 半导体衬底 120的表面进行掺杂， 可以选择注入或者扩散的方法实施。 掺杂 后的第一半导体衬底 100或第二半导体衬底 120本身即具有不同电导率的双 层结构， 再将两者键合在一起， 即形成了具有三层 （选择其一进行掺杂） 甚 至四层 （两者均进行掺杂） 的半导体衬底， 对于中间具有重掺杂夹层的三层 半导体结构对于 IGBT等功率器件尤其具有重要的应用价值。
附图 2D所示， 参考步骤 S13 , 对键合界面实施退火。 退火温度优选大 于 1000°C， 以使键合界面在高温加固退火后界面处氧化形成的键合媒介层 101消融晶格化， 不影响后续器件性能。 由于界面处的键合媒介层 101是通 过自然氧化形成的， 厚度较薄， 故其中所含有的氧原子可以在退火过程中扩 散到晶格中去， 被晶格原子稀释， 进而使第一半导体衬底 100和第二半导体 衬底 200的晶格在界面处能够保持连续。 附图 3是退火后的界面处的透射电 子显微镜 （TEM) 照片， 从中可以明显看到键合界面氧已经消融， 晶格是连 续的。 故此退火的步骤可以进一步促进多层半导体衬底中两层之间在晶格尺 度上的融合。
附图 2E所示， 参考步骤 S14, 减薄第一半导体衬底 100和第二半导体衬 底 200。 减薄的厚度根据实际应用的需要来确定， 通常在晶圆加工的过程中， 这个厚度都是由需要此晶圆的客户给定的， 减薄可以首先采用机械减薄， 再 实施化学机械抛光进行表面精加工。 在减薄之前还可以进一步根据需要实施 倒角工艺。
减薄之后， 还可以再引入一半导体衬底重复实施上述自然氧化工艺、 键 合工艺以及掺杂工艺， 进一步形成具有更多叠层的半导体衬底。
综上所述， 虽然本发明已用较佳实施例揭露如上， 然其并非用以限定本 发明， 本发明所属技术领域中具有通常知识者， 在不脱离本发明的精神和范 围内， 当可作各种的更动与润饰， 因此本发明的保护范围当视权利要求书所 申请的专利范围所界定者为准。

Claims

1. 一种多层半导体衬底的制备方法， 其特征在于， 包括如下步骤： 提供第一半导体衬底和第二半导体衬底；
将第一半导体衬底和第二半导体衬底中的至少一个进行冲洗，所述冲洗依 次包括一氢氟酸溶液冲洗的步骤和一去离子水冲洗的步骤，以在被清洗的 表面形成氧化的键合媒介层；
以键合媒介层为中间层， 将第一半导体衬底和第二半导体衬底键合在一 起。
2. 根据权利要求 1所述的多层半导体衬底的制备方法， 其特征在于， 所述第 一半导体衬底和第二半导体衬底由相同的材料构成， 且具有不同的电阻 率。
3. 根据权利要求 1所述的多层半导体衬底的制备方法， 其特征在于， 所述第 一半导体衬底和第二半导体衬底由相同的材料构成，且具有不同的导电类 型。
4. 根据权利要求 2或 3所述的多层半导体衬底的制备方法， 其特征在于，所 述第一半导体衬底和第二半导体衬底的材料为单晶硅。
5. 根据权利要求 4所述的多层半导体衬底的制备方法， 其特征在于， 所述氢 氟酸溶液冲洗步骤的清洗时间是 1分钟以上，所述去离子水冲洗步骤的清 洗时间不超过 10分钟。
6. 根据权利要求 1所述的多层半导体衬底的制备方法， 其特征在于， 所述第 一半导体衬底和第二半导体衬底由不同的材料构成。
7. 根据权利要求 1所述的多层半导体衬底的制备方法， 其特征在于， 在键合 步骤实施完毕后， 进一步包括一对键合界面实施退火的步骤。
8. 根据权利要求 1所述的多层半导体衬底的制备方法， 其特征在于， 在键合 步骤实施完毕后，进一步包括减薄第一半导体衬底或者第二半导体衬底的 步骤。
9. 根据权利要求 1所述的多层半导体衬底的制备方法， 其特征在于， 所述将 第一半导体衬底和第二半导体衬底中的至少一个进行冲洗的步骤中，在所
PCT/CN2012/073866 2011-08-19 2012-04-12 多层半导体衬底的制备方法 WO2013026277A1 (zh)

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CN103208737B (zh) * 2012-12-20 2016-01-20 上海显恒光电科技股份有限公司 一种紫外出光屏的制作方法及制得的紫外出光屏和应用
CN104637813B (zh) * 2013-11-13 2019-10-01 江苏物联网研究发展中心 Igbt的制作方法
CN105374862B (zh) * 2014-09-01 2018-09-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置

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