TWI284360B - Semiconductor substrate, manufacturing method thereof, and semiconductor device - Google Patents

Abstract

A separation layer is formed on a silicon substrate. An SiGe layer serving as a strain induction layer and a silicon layer serving as a strained semiconductor layer are formed sequentially on the separation layer to prepare a first substrate. The first substrate is bonded to a second substrate made of the same material as the silicon layer of the strained semiconductor layer. The structure is separated into two parts at the separation layer. When the residue of the separation layer and the SiGe layer are removed, and the surface is planarized by hydrogen annealing, an Si substrate having a strained silicon layer on the uppermost surface is obtained.

Description

1284360 (1) Description of the Invention [Technical Field] The present invention relates to a semiconductor substrate, a method of fabricating the same, and a semiconductor device. [Prior Art] A substrate having a strained layer has attracted a lot of attention as a substrate is used to form a semiconductor device at a high speed and low energy consumption. A SiGe layer made of tantalum and niobium is grown on a substrate, and a single crystal layer is grown on the layer. Therefore, a strain is applied to the tantalum layer, and a strained tantalum layer can be obtained. This strain is generated because the lattice constant of the SiGe layer is slightly larger than the lattice constant of the single crystal germanium layer. For example, U.S. Patent No. 5,221,413 to AT&T, discloses a substrate that incorporates strain enthalpy, SiGe, and strained Si/SiGe/Si. On the other hand, a silicon on insulator (SOI) substrate having a buried oxide film on a substrate also attracts a lot of attention and is used as a substrate for a high speed and low energy consumption. To form a semiconductor device. The combination of strain enthalpy and the structure of the upper layer of the insulating layer has also been published in a wide range of studies. This substrate is implemented to achieve two advantages, one is high-speed operation by strain enthalpy, and the other is low energy consumption performance and high calculation speed by 绝缘 on the insulating layer (see Shin for details) -ichi Tackagi, "Metal-Oxide-Semiconductior (MOS) device technologies using Si/SiGe heretointerfaces'', Oy o Buturi 5 vol. 72. no. 3, pp. 284-290, (2) 1284360 2 0 03 ). In this reference, the substrate and a structure incorporating a strained sand, SiGe, insulator, and (strained-Si/SiGe/insulator/Si) substrate are described. A strained sand, insulator, and sand without a SiGe layer The substrate of (strained-Si/insulator/Si) has also been published (for details, see T. A. Langdo, et. al., Appl. Phys. Lett., vol. 2, no. 24, pp. 4256-4257, 2003). In this method, after the strain 矽/SiGe formed on a first substrate is converted into an insulating substrate by hydrogen ion implantation, bonding, and separation, the SiGe layer is removed.矽-large integrated circuit (Si-LSI), The above techniques require further equipment and optimization of process design. The existence of SiGe has been described in the paper by TA Langdo, et. al. However, there are still other problems, such as: The difference between doping diffusion, metal contact forming, and germanium diffusion. In addition, due to the appearance of the insulating layer, the structure having an insulating layer also has the same problem as the upper layer of the insulating layer, and also includes the thermal accumulation of the device operation. SUMMARY OF THE INVENTION The present invention has been specifically considered based on the problems of the above-described prior art, and has a new technique for forming a germanium wafer having a strained germanium layer (as an example). According to a first aspect of the present invention, a semiconductor substrate is provided, comprising: a strained semiconductor layer on the semiconductor substrate, wherein the strained semiconductor layer is made of the same material as the semiconductor substrate. The semiconductor substrate package (3) 1284360 At least one single crystal semiconductor substrate and a polycrystalline semiconductor substrate also including a polycrystalline semiconductor (including a microcrystal) A substrate of the conductor layer is formed on a semiconductor substrate. According to a second aspect of the present invention, a method of fabricating a semiconductor substrate of the present invention includes: a first step of forming a first material made of a first material The strained semiconductor layer is formed on a semiconductor substrate made of a second material to form a first substrate, and at least on the surface thereof can be used as a strain sensing material; a second step: the first step The strained semiconductor layer of the substrate is bonded to a second substrate made of the first material; and a third step of removing a member on the side of the first substrate other than the strained semiconductor layer, and leaving The strained semiconductor layer is underlying the second substrate. According to a third aspect of the present invention, a semiconductor substrate manufactured by the above manufacturing method is proposed. According to a fourth aspect of the present invention, there is provided a semiconductor device having a field effect transistor formed on the strain sensing layer of the semiconductor substrate. With the semiconductor layer of the present invention, the channel mobility can be increased by the strain without changing the process developed by the conventional 矽-large integrated circuit technology. Other features, objects, and advantages of the invention will be described in the following description. (4) (4) 1284360 [Embodiment] Some preferred embodiments of the present invention will be described in detail below. However, the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited by the embodiments, except as described below. Furthermore, in order to provide a more succinct description and a better understanding of the invention, the various parts of the drawings are not drawn according to their relative dimensions, and some dimensions have been exaggerated compared to other related dimensions; the irrelevant details are not fully Draw, in order to make the schema simple. (First Embodiment) A strain sensing layer is formed on the surface of a half conductor substrate made of a second material. A strained semiconductor layer made of the second material is formed on the strain sensing layer to form a first substrate. A second substrate made of a first material is bonded to the first substrate. The semiconductor substrate made of the second material and the strain sensing layer are removed. Therefore, the strained semiconductor layer made of the first material may be formed on the second substrate made of the first material to be in contact with the second substrate. The first and second materials generally use ruthenium. The strain sensing layer is formed of a layer (Sh. x Gex layer) containing ruthenium and osmium. This layer (preferably a single crystal germanium layer) is almost entirely made of tantalum and is formed on the Si layer as a strained semiconductor layer. The (5) (5) 1284360 formed on the semiconductor substrate made of the second material

In the Sh-xGex layer, x preferably falls within the range of 0 to 0.5. More preferably, on the surface of the semiconductor substrate, X is almost zero and gradually changes. On the highest surface, i.e., where the strained semiconductor layer is formed, X is preferably from 0.1 to 0.5. The lattice relaxation occurs at least on the highest surface so that the strain at that point is minute. The member on the side of the first substrate other than the strained semiconductor layer can be removed by a mechanical removal method such as honing or polishing. Alternatively, before and after bonding, hydrogen ions may be implanted onto the semiconductor substrate made of the second material or on the strain sensing layer, and the portion may be Separation. The Sh-xGex layer on the strained semiconductor layer is removed by a polishing method or a chemical etching method. After the SihXGex layer is removed, and only the strained semiconductor layer is left on the second substrate, surface planarization is completed. The manufacturing method according to the first embodiment of the present invention may further comprise a step of forming a circuit component by using the strained semiconductor layer as an active layer. For devices having such a circuit component, a high speed operation can be performed by the strained semiconductor layer. (Second Embodiment) • A separation layer is formed on the surface of a semiconductor substrate made of a second material. A strain sensing layer is formed on the separation layer. Further, a strained semiconductor layer made of a first material is formed on the -9-(6) (6) 1284360 variable-sensing layer to form a first substrate. A second substrate made of the first material is bonded to the first substrate. The portions are separated at the separation layer. Then, the remaining separation layer and strain sensing layer are removed. Thus, the strained semiconductor layer made of the first material may be formed on the second substrate made of the first material to be in contact with the second substrate. The first and second materials generally use ruthenium. The separation layer can usually be formed by polishing the surface of the semiconductor substrate (ruthenium substrate) made of the second material using an electrominening method. As for other methods, after the strain sensing layer and the sensing semiconductor layer are formed, ions (eg, hydrogen ions) are implanted for the semiconductor substrate made of the strain sensing layer or the second material. The separation layer is formed. The strain sensing layer is formed of a layer containing germanium (Si^Gex layer). This layer (preferably a single crystal germanium layer) is almost made of the stone and formed on the Sii.xGex layer as a strained semiconductor layer. In the SihXGex layer formed on the separation layer, X is preferably within the range of 〇 to 0.5. More preferably, on the surface of the separation layer, X is almost 0 and gradually changes. On the highest surface, i.e., the formation of the strained semiconductor layer, X is preferably from 0.1 to 0.5. The lattice relaxation occurs at least on the highest surface so that the strain at that location is minute. When the separation layer is a porous layer, the separation step is performed by wedge insertion, tension/shear application, liquid jet (water jet) injection, gas jet injection or ultrasonic application. When the separation layer is formed by ion cloth-10-(7)(7)1284360, the separation step must be completed by annealing at a temperature of 200 to 300 ° C to 500 ° C to 600 ° C. . The Si! 4 layer on the strained semiconductor layer is removed by a polishing method or a chemical etching method. After the Si^Gex layer is removed, and only the strained semiconductor layer is left on the second substrate, surface planarization is completed. The manufacturing method according to the second embodiment of the present invention may further comprise a step of forming a circuit component by using the strained semiconductor layer as an active layer. For devices having such a circuit component, a high speed operation can be performed by the strained semiconductor layer. (Third Embodiment) A separation layer is formed on the surface of a semiconductor substrate made of a second material. A strain sensing layer is formed on the separation layer. Further, a strained semiconductor layer made of a first material is formed on the strain sensing layer to form a first substrate. A second substrate made of the first material is bonded to the first substrate. The portions are separated at the separation layer. Then, the remaining separation layer and strain sensing layer are removed. Therefore, the strained semiconductor layer made of the first material may be formed on the second substrate made of the first material to be in contact with the second substrate. The first and second materials generally use ruthenium. The separation layer can usually be formed by polishing the surface of the semiconductor substrate (ruthenium substrate) made of the second material using electroplating. -11 - (8) 1284360

The strain sensing layer is formed of a layer (Si layer) containing germanium as the pore sealing material for the porous surface layer. The layer (preferably a single crystal germanium layer) is almost entirely made of tantalum and is formed on the Si bxGex layer as a strained semiconductor layer. Fig. 8 is a sectional view for explaining the state in which the layer containing ruthenium (Si!.xGex layer) is formed as the pore sealing portion of a porous surface layer. As shown in Fig. 8, the pores of the surface layer of a porous layer 40 are filled with a layer 41 so that the surface of the crucible is covered by the Sh. xGex layer 41. In the strain-sensing Si !.xGex layer, X is preferably within the range of 〇 to 〇·5. More preferably, the Sh.xGex layer is formed by filling a plurality of pores in the porous surface layer. The lattice relaxation occurs at least on the highest surface so that the strain at that point is minute. When the separation layer is a porous layer, the separation step is performed by wedge insertion, tension/shear application, liquid jet (water jet) injection, gas jet injection or ultrasonic application.

The Si ^ x Gex layer on the strained semiconductor layer is removed by a polishing method or a chemical etching method. After the SinGex layer is removed, and only the strained semiconductor layer is left on the second substrate, surface planarization is completed. The manufacturing method according to the third embodiment of the present invention may further comprise a step of forming a circuit component by using the strained semiconductor layer as an active layer. For devices having such a circuit component, a high speed operation can be performed by the strained semiconductor layer. -12- (9) (9) 1284360 (Fourth Embodiment) A layer containing germanium (Si^Gex layer) is formed on the surface of a semiconductor substrate made of a second material. Next, a porous SiGe layer is formed by annealing to serve as a separation layer. A layer containing germanium (SinGex layer) is again formed on the porous SiGe layer to serve as a strain sensing layer. The layer (preferably a single crystal sand layer) is almost entirely made of tantalum and is formed on the Si!-xGex layer as a strained semiconductor layer made of a first material. a first substrate. A first substrate made of a material of the table is joined to the first substrate. The portions are separated at the separation layer. Then, the remaining separation layer and the SiGe layer are removed. Therefore, the strained semiconductor layer made of the first material may be formed on the second substrate made of the first material to be in contact with the second substrate. The first and second materials generally use ruthenium. In the Si].xGex layer as a strain sensing layer, x is preferably within the range of 〇·1 to 0.5. More preferably, on the surface of the semiconductor substrate, X is almost zero and gradually changes. On the highest surface, X is preferably from 0.1 to 0.5. The lattice relaxation occurs at least on the highest surface so that the strain at that point is minute. When the separation layer is a porous layer, the separation step is performed by wedge insertion, tension/shear application, liquid jet (water jet) injection, gas jet injection or ultrasonic application. The Si! 4 layer on the strained semiconductor layer is removed by a polishing method or a chemical etching method. -13· (10) (10) 1284360 After the Sh_xGex layer is removed, and only the strained semiconductor layer is left on the second substrate, surface planarization is completed. The manufacturing method according to the fourth embodiment of the present invention may further comprise a step of forming a circuit component by using the strained semiconductor layer as an active layer. For devices having such a circuit component, a high speed operation can be performed by the strained semiconductor layer. (Fifth Embodiment) A layer containing germanium (SihXGex layer) is formed as a strain sensing layer on the surface of a semiconductor substrate made of a second material. Next, a porous SiGe layer is formed by annealing to serve as a separation layer. In the strain-sensing Sh.xGex layer formed on the semiconductor substrate made of the second material, X preferably falls within the range of ο·· to 〇.5. More preferably, on the surface of the semiconductor substrate, germanium is almost 〇 and gradually changes. On the highest surface, X is preferably from 0.1 to 0.5. Lattice relaxation occurs at least on the highest surface so that the strain at that location is minute. Therefore, the Si hxGex layer acts almost as the same - strain sensing layer even after the formation of the porous. The layer (preferably a single crystal sand layer) is almost made of sand and is formed on the Si^Gex layer as a strained semiconductor layer made of a first material, thereby fabricating a layer The first substrate. A second substrate made of the first material is bonded to the first substrate. The portions are separated at the separation layer. Then, the remaining separation layer and the Si!.xGex layer are removed. Therefore, the -14-(11) 1284360 strained semiconductor layer made of the first material may be formed on the second substrate made of the first material to be in contact with the second substrate. The first and second materials generally use ruthenium. When the separation layer is a porous layer, the separation step is performed by wedge insertion, tension/shear application, liquid jet (water jet) injection, gas jet injection or ultrasonic application. The Si hxGex layer on the strained semiconductor layer is removed by a polishing method or a chemical etching method. After the Sii-xGex layer is removed, and only the strained semiconductor layer is left on the second substrate, surface planarization is completed. The manufacturing method according to the fifth embodiment of the present invention may further comprise a step of forming a circuit component by using the strained semiconductor layer as an active layer. For devices having such a circuit component, a high speed operation can be performed by the strained semiconductor layer. Some examples of the invention will be described below with the accompanying drawings. Examples 1 to 5 described below correspond to the first to fifth embodiments described above, respectively. (Example 1) A method of manufacturing a semiconductor substrate (member) according to Example 1 of the present invention will be described below, and reference is made to Figs. 1A to 1C. In this step (thinning step) as shown in Fig. 1A, a first substrate (component) 10 has a layer containing ruthenium, iridium (additional material) (8丨1.>(〇6\layer) 12 is formed on a sand substrate 11, and a sand layer 13 is formed on the SiGe layer. -15- (12) (12) 1284360 (film growth of the SiGe layer) First, the strain-sensing Si1·xGex layer 12 ( The X system is 0.1 to 0.5, and x = 0.3 is exemplified by chemical vapor deposition, and heated by an illuminator for growth of the germanium substrate 11. The preferred growth conditions are as follows. It should be noted that pre-baking can be performed before growth. • Carrier gas (H2) The flow rate of H2 is preferably 25 to 45 liters/min, and is usually 30 liters/min. Source gas (SiH4)

The flow rate of SiH4 is preferably from 50 to 200 cubic centimeters per minute, and is usually from 1 cubic centimeters per minute. • The gas flow rate of the source gas (2% GeH4) 2% GeH4 is preferably 20 to 500 cubic centimeters per minute, and is usually 300 cubic centimeters per minute. • Cavity Air Pressure The chamber air pressure is preferably 10 to 100 Torr, and is usually 1 00 Torr. • Temperature (base temperature) This temperature is preferably 65 0 to 6 80 °c. • Growth rate The growth rate is preferably 〇~50 nm/min. -16- (13) (13) 1284360 The ratio of the proportion of niobium may vary depending on the mixing ratio of the source gas. Preferably, the erbium concentration is set to be lower in the initial stage of growth on the single crystal germanium substrate, and increases as the crystal film growth progresses. The ratio of the ruthenium is preferably such that X is set to 0 · 1 to 0 · 5. This strain on the highest surface can be relaxed, for example: introduced defects. Further preferably, the surface of the ruthenium substrate 11 is annealed (pre-baked) under a hydrogen gas before the growth of the Sh-xGex layer 12. In the pre-baking, the flow rate of hydrogen is preferably 15 to 45 liters/minute, and is usually 40 liters/minute. The temperature is preferably from 700 to 1000 ° C, and is usually 950 ° C. The chamber gas pressure is preferably from 10 to 760 Torr, and is usually 80 Torr. In the initial stage, the single crystal germanium layer is preferably grown at a low growth rate, usually 50 nm/min or less. When a sample is loaded in or unloaded from the chemical vapor deposition apparatus, a natural oxide film formed on the surface can be used in each step before being loaded in the apparatus. The surface was immersed in a diluted hydrofluoric acid solution for removal. (Formation of strained ruthenium layer) Next, the single crystal ruthenium layer 13 is grown on the Si].xGex layer 12 by chemical vapor deposition. The lattice constant of the single crystal germanium layer 13 formed in this manner is different from the lattice constant of the Si layer 12 located therebelow, and therefore acts as the same strained germanium layer. According to this example, between the strained layer 13 and the Si].xGex layer 12, the concentration of germanium in the Si].xGex -17-(14) (14) 1284360 layer 1 2 close to the interface can be Control it precisely. Furthermore, the concentration profile at the interface can be a uniform (planar) distribution. Therefore, the strain of the strained layer formed on the Si!.xGex layer 12 can be easily controlled. For this reason, a high quality strain enthalpy layer 13 can be obtained. The growth conditions of the single crystal germanium layer as the strained germanium layer 13 are as follows: • Carrier gas (H2) The flow rate of hydrogen is preferably 15 to 45 liters/minute, and is usually 3 liters/minute. . • Source gas (SiH4) The flow rate of the source gas is preferably 50 to 500 cubic centimeters per minute, and is usually 100 cubic centimeters per minute. • Chamber Air Pressure The chamber air pressure is preferably 1 〇 1 〇〇 1 Torr, and is usually 80 Torr. • Growth temperature (base temperature) The growth temperature is preferably 65 0 to 1 ° C, and is usually 900 ° C. • Growth rate The growth rate is preferably 10 to 5 nanometers per minute. (Completion at the side of the first substrate) Through the above steps, the first -18 - (15) 1284360 substrate (component) 10 as shown in Fig. 1A can be obtained. The Si hGex J and the strained layer 13' are formed by a plurality of steps. The Sch. xGex layer 12 can also be formed by a single (for example, chemical vapor deposition). By changing the concentration of helium (or other gases) and other conditions gradually or stepwise. (joining) after the step as shown in FIG. 1A, then in the step (joining step) as shown in FIG. 1, a second substrate (the member is bonded to the first substrate (component) 1) The upper surface side. A substrate (component) 1 and the second substrate (component) 30 may be joined. Alternatively, plating or annealing may be performed in order to be firmly coupled to the bonded substrate. The second substrate (the component is usually a crucible substrate. The bonding surface of the two substrates to be joined preferably needs to undergo a hydrophobic treatment (also applied to the following example because if the bonding surface is hydrophobic) a single oxide is formed in the bonding interface. (Removal of the substrate) After the step as shown in FIG. 1B, then in the step (removal step) as shown in FIG. The ruthenium substrate 11 formed by the bonding step (the bonded substrate stack) is removed. The removal step can be performed by a mechanical removal method such as honing polishing, or a chemical Removal method, for example: Wet etching i 12 step and concentration B map) 30 This simple is the connection) 30, more than ° film shape C map. Method, engraved or -19- (16) (16) 1284360 dry etching to complete. If the substrate is removed by chemical etching, a mixed solution containing potassium hydroxide, potassium dichromate, propanol and water will be used.矽 can be removed by selectivity about Si〇.7Ge().3 about 20 times (for details, see D. J. Godbey, et al., Appl. Phys Lett., vol. 56, No. 4, pp. 3 73 -3 79,1 990 ). Alternatively, when EDP is used, Ethylene Diamine Pyrochatechol can be removed by a temperature of 82 ° C with a selectivity of about 390 times associated with SimGem (see, for details, D. Feijoo, et. al., J. Electro. Mat., vol. 23, no. 6, ρρ· 493-496, 1994) 〇 In addition, the Sii_xGex layer 12 is removed. The Sii.xGex layer 12 can be removed by, for example, polishing or chemical etching. It is assumed that the Si 1-XG ex layer 12 is removed by chemical etching, and a mixed solution containing hydrofluoric acid (0.5%), nitric acid, and water (in a ratio of 5 ··40··20) is used. . Si〇.7Ge().3 can be removed by the selectivity associated with 矽 about 13 times (for details, see 6.11.«:1^以,61&1.,八??1· Phys · Lett·, vol· 58, no. 17, pp. 1 8 99- 1 90 1,1991) 0 That is, a conversion step is performed by the bonding step as shown in FIG. 1B and as shown in FIG. 1C. The removal steps shown are performed. Fig. 1C is a cross-sectional view for explaining the semiconductor substrate manufactured according to Example 1 of the present invention. (Strain enthalpy and circuit obtained by hydrogen annealing) When a circuit component is formed by the strain enthalpy layer 13, -20-(17) (17) 1284360 can be obtained as a device with high speed and low energy consumption. The formation of the circuit element of the semiconductor device will be described below. The surface can be planarized by polishing or hydrogen annealing, if desired. (Example 2) According to Example 2 of the present invention, a method of manufacturing a semiconductor substrate (member) will be described below, and reference is made to Figs. 2A to 2D. In the example! Before the formation of the Sii_xGex layer, a porous layer is formed on the surface close to the sand substrate η as a separation layer. (Electroplating) First, a porous tantalum layer 14 is formed on the single crystal germanium base 11 by electroplating. Usually, the electroplating is performed in such a manner that a solution containing hydrofluoric acid is filled with a shovel reservoir having a platinum electrode pair, the crucible substrate 1 is placed between the electrodes, and a current is supplied between the electrodes. . The porous tantalum layer 14 formed by this step has a fragile structure and is used as a separate layer in a later separation step. For the electric ore, the technique disclosed in Japanese Patent Application No. 7-3 028 8 9 can be used as the plating condition. A protective film, such as an oxide film, may be formed on the surfaces of the pores inside the porous layer 14. Alternatively, a plurality of layers having different porosities may be formed by controlling the plating solution or current. For example, a first porous layer may be formed on the side of the surface, and a second porous layer having a higher porosity may be formed on the porous layer of the 21 - (18) 1284360 below. (SiGe/矽 epitaxial bonding) forming a strain-inducing Si hGcx layer 12 containing tantalum and niobium (attachment) and a strained tantalum layer 1 on the porous tantalum layer 14 to bond the first substrate to the second Steps such as substrate and Example 1 A first substrate (component) having a structure as shown in Fig. 2B shown in Fig. 2A is obtained by the bonding step. It is also preferred that the surface of the porous layer 14 is subjected to a hydrogen fire (pre-baked) before the layer 12 is formed into the aperture layer 14. In the pre-baking, the flow rate of hydrogen is preferably 15 to 45 liters / minute, and is usually 40 liters / minute. The temperature is 700 to 1 ° C, and is usually 950 ° C. The chamber pressure is 10 to 760 taels, and is usually 80 taels. In the initial stage, the germanium layer is preferably grown at a low growth rate, typically 50 minutes or less. When a sample is loaded in the chemical vapor deposition device or the vapor deposition device is unloaded, a natural film formed on the surface can be surface-immersed in each step before being loaded on the device. Remove in diluted hydrofluoric acid solution. (Removal of Substrate) After this step as shown in Fig. 2B, in the step (separation step) as shown in the first step, the material which is formed by the bonding step; and the same structure. Preferably, the multi-gas retreat is a better system, the single nano/from the oxidation, the 2 C is formed into the -22-(19) 1284360 substrate (joined substrate stack) It is separated into two substrates at a portion of the separation layer (porous ruthenium layer) 14. That is, a conversion step is performed by the joining step as shown in Fig. 2B and the separating step as shown in Fig. 2C. This separation step can be performed by, for example, injecting a fluid to the separation layer 14 as it rotates the bonded substrate stack about its axis. Reference numerals IV and 14 are used to indicate the porous layer left on the substrates after separation. Separation methods using tensile stress, compression or shear stress can be used instead of the above separation method using a fluid such as a liquid or a gas. Alternatively, these methods can be combined. The porous layer 14" remaining in the second substrate 30 after separation is removed by etching, polishing, honing or by annealing under a reducing air containing hydrogen. In order to remove the porous layer by etching, the porous layer 14" can be selectively moved by using a mixed solution containing hydrofluoric acid, hydrogen peroxide, and water and with a selectivity of about 1:105. except. When many surface areas of the porous layer have been used, they can also be selectively removed by other ruthenium etchants. In addition, the Si^Gex layer 12 is removed. The 12 can be removed by, for example, polishing or chemical etching. It is assumed that the Si!.xGex layer 12 is removed by chemical etching, and a mixed solution containing hydrofluoric acid (0.5%), nitric acid, and water (in a ratio of 5:40:20) is used. Si〇.7Ge().3 can be removed by selectivity about 矽 about 13 times (for details, see A. H_ Krist, et. al., Appl. Phys· Lett·, vol. 58, No. 17, pp. 1 899- 1 90 1,1991) o -23- (20) 1284360 The 2D drawing is a cross-sectional view for explaining the semiconductor substrate manufactured according to Example 2 of the present invention. (Strain enthalpy and circuit obtained by hydrogen annealing) When a circuit component is formed by the strain enthalpy layer 13, a device of high speed and low energy consumption can be obtained. The formation of this circuit element (manufacture of a semiconductor device) will be described below. The surface can be planarized by polishing or hydrogen annealing, if desired. (Example 3) According to Example 3 of the present invention, a method of manufacturing a semiconductor substrate (member) will be described below, and reference is made to Figs. 3A to 3D. In the forming step of the Si bxGex layer of Example 2, the pores of the porous layer can be sealed by ruthenium.

(Electroplating) First, a porous tantalum layer 14 is formed on the single crystal germanium base 11 by electroplating as shown in Fig. 3A. Typically, electroplating is accomplished by filling a solution containing hydrofluoric acid with a shovel reservoir having a platinum electrode pair, placing the crucible substrate 11 between the electrodes, and providing a current between the two electrodes. The porous sand layer 14 formed by this step has a fragile structure and is used as a separation layer in a later separation step. For electroplating, the technique disclosed in Japanese Patent Application No. 7-3 0 8 8 9 can be used as its electric # condition. - 24 - (21) 1284360 A protective film, for example, an oxide film, may be formed on the surfaces of the pores inside the porous layer 14. Alternatively, a plurality of layers having different porosities can be formed by controlling the electrolysis solution or current. For example, a first porous layer may be formed on the side of the surface, and a second porous layer having a higher porosity may be formed under the first porous layer. (The pores are sealed by SiGe) The surface pores of the porous tantalum layer 14 can be sealed by Si hxGex. These preferred growth conditions are as follows. It should be noted that pre-drying (described below) can be performed prior to growth. • The flow rate of the carrier gas (H2) H2 is preferably from 25 to 45 liters/min, and is usually 30 liters/min.

• First source gas (SiH4)

The flow rate of SiH4 is preferably from 50 to 200 cubic centimeters per minute, and is usually from 1 cubic centimeters per minute. • The flow rate of the second source gas (2% GeH4) 2% GeH4 is preferably 20 to 500 cubic centimeters per minute, and is usually 300 cubic centimeters per minute. • Chamber Air Pressure The chamber air pressure is preferably 10 to 100 Torr, and is usually 1 00 Torr. -25· (22) 1284360 • Temperature This temperature is preferably 65 0 to 6 80 °C. • Growth rate The growth rate is preferably from 5 to 20 nm/min.

The ratio of the enthalpy of the sealed Sh-xGex layer may vary depending on the mixing ratio of the source gas. Preferably, the X system is from 0.1 to 0.5. This strain on the sealing layer can be relaxed due to the presence of surface holes. By this step, the strain-sensing Si layer is formed. Further preferably, the surface of the crucible substrate 11 is annealed (pre-baked) under a hydrogen gas prior to the pore sealing. In the pre-baking, the flow rate of hydrogen is preferably from 15 to 45 liters/min, and is usually 40 liters/min. The temperature is preferably from 7 〇〇 to 1 ° C, and is usually 950 ° C. The chamber pressure is preferably from 10 to 760 Torr and is typically 80 Torr.

When a sample is loaded in or unloaded from the chemical vapor deposition apparatus, a natural oxide film formed on the surface can be used in each step before being loaded in the apparatus. The surface was immersed in a diluted hydrofluoric acid solution for removal. (矽 epitaxial bonding to completion) A layer 13 is formed on the SiGe sealing layer, and the steps up to completion are the same as those in the example 2. A first substrate (component) 1 has a structure as shown in Fig. 3A. The structure shown in Fig. 3B is obtained by the joining step. After separation, the substrate is divided into two sections, as shown in Figure -26 (23) 1284360, Figure 3C, and a conversion step is performed. Fig. 3D is a cross-sectional view for explaining the semiconductor substrate manufactured according to Example 3 of the present invention. (Strain enthalpy and circuit obtained by hydrogen annealing) When a circuit component is formed by the strain enthalpy layer 13, a device which is high in speed and low in energy consumption can be obtained. The formation of this circuit element (manufacture of a semiconductor device) will be described below. The surface can be planarized by polishing or hydrogen annealing, if desired. (Example 4) A method of manufacturing a semiconductor substrate (member) according to Example 4 of the present invention will be described below, and reference is made to Figs. 4A to 4D. A SiGe layer formed on a substrate 11 was made porous to replace the porosity of the ruthenium base of Example 2. (Crystal film growth of SiGe layer) As shown in Fig. 4A, a layer 15 containing yttrium and lanthanum (additional material) (Si yGey layer, y is 〇·ΐ to 〇·5, and y = 〇. 3 is exemplified by chemical vapor deposition and heating via an illuminator for growth of the substrate on the single crystal substrate. These preferred growth conditions are as follows. It should be noted that pre-baking can be performed prior to growth. Carrier gas (H2) -27- (24) 1284360

The flow rate of H2 is preferably from 25 to 45 liters per minute, and is usually 30 liters per minute. • First source gas (SiH4)

The flow rate of SiH4 is preferably from 50 to 200 cubic centimeters per minute, and is usually from 1 cubic centimeters per minute. • Second source gas (2% GeH4)

The flow rate of 2% GeH4 is preferably from 20 to 500 cubic centimeters per minute, and is usually 300 cubic centimeters per minute. • Cavity Air Pressure The chamber air pressure is preferably 10 to 100 Torr, and is usually 1 00 Torr. • Temperature (base temperature) The temperature is preferably 650 to 680 °C. • Growth rate The growth rate is preferably from 10 to 50 nm/min.

The proportion of the bismuth produced may vary depending on the mixing ratio of the source gas. Preferably, the erbium concentration is set to be lower in the initial stage of growth on the single crystal germanium substrate, and increases as the crystal film growth progresses. The ratio of the ruthenium is preferably finally set to y from 0.1 to 0.5. This strain on the highest surface can be relaxed, for example, an introduced defect. (SiGe plating) After this step as shown in Fig. 4A, then in the step (electroplating step) as shown in Fig. 4B, a porous tantalum layer 6 is made by electricity - 28 - (25) 1284360 is plated on the SiwGey layer 15. Usually, the electroplating is performed in such a manner that a solution containing hydrofluoric acid is filled with a plating reservoir having a platinum electrode pair, and the crucible substrate 1 having the siHGey layer 15 is placed between the electrodes and in two The electrodes are superb. The porous tantalum layer 16 formed by this step has a violent structure and is used as a separate layer in a later separation step. A protective film, such as an oxide film, may be formed on the surfaces of the pores inside the porous layer 16. When SiGe is oxidized, cerium oxide is formed on the surface, and the ruthenium is advanced inward. An oxide film is formed on the surfaces of the internal pores. Alternatively, a plurality of layers having different porosity can be formed by controlling the plating solution or current. For example, a first porous layer may be formed on the surface side of the Sh.yGey layer 15 and a second porous layer having a higher porosity may be formed on the first porous layer. Below. The porous layer 16 can be deeper than the Sil.yGey layer 15 and reach the crucible substrate 11 (and the porous layer 16 in Figure 4B does not reach the crucible substrate 11). Since the formation of the porous layer by electroplating is an electrolytic etching method, these defects can be easily and selectively etched. Therefore, after the formation of the porous layer, the defects introduced during the formation of the Si!.yGey layer 15 hardly remain in the remaining portion of the single crystal germanium layer. As a result, the crystallinity is restored. (SiGe/矽 epitaxial to completion) Forms a strain sensing containing yttrium and lanthanum (additional material) -29- (26) 1284360

The Si]-xGex layer 12 is on the porous layer 16, and the steps up to completion are the same as those in the example 2. A first substrate (component) has a structure as shown in Fig. 4C. The structure shown in Fig. 4D is obtained by the joining step. After separation, the substrate is divided into two portions as shown in Fig. 4E, and a conversion step is performed. Fig. 4F is a cross-sectional view for explaining the semiconductor substrate manufactured according to Example 4 of the present invention. (Strain enthalpy and circuit obtained by hydrogen annealing) When a circuit component is formed by the strain enthalpy layer 13, a device which is high in speed and low in energy consumption can be obtained. The formation of this circuit element (manufacture of a semiconductor device) will be described below. The surface can be planarized by polishing or hydrogen annealing, if desired. (Example 5)

According to the fifth aspect of the present invention, a method of manufacturing a semiconductor substrate (member) will be described below, and reference is made to Figs. 5A to 5F. If lattice relaxation has occurred on the surface of the porous Si Ge layer of Example 4, a strained germanium layer 13 may be formed thereon without the need to form another Si Ge layer. The remaining steps are the same as in Example 4. Fig. 5A is a cross-sectional view for explaining the epitaxial step of the SiGe layer. Fig. 5B is a cross-sectional view for explaining the joining step. A first substrate (component) has a structure as shown in Fig. 5C. The structure shown in Fig. 5D is obtained by the joining step. After separation, the substrate is divided into two sections, as shown in Fig. 5E, and a conversion -30-(27)(27)1284360 step is performed. Fig. 5F is a cross-sectional view for explaining the semiconductor substrate manufactured according to Example 5 of the present invention. (Strain enthalpy and circuit obtained by hydrogen annealing) When a circuit component is formed by the strain enthalpy layer 13, a device which is high in speed and low in energy consumption can be obtained. The formation of this circuit element (manufacture of a semiconductor device) will be described below. The surface can be planarized by polishing or hydrogen annealing, if desired. (Example 6) According to Example 6 of the present invention, a method of manufacturing a semiconductor substrate (member) will be described below, and reference is made to Figs. 6A to 6E. - (semiconductor substrate) A semiconductor substrate made of the second material as described in Examples 4 and 5 and made of a material (for example, germanium, whose lattice constant is larger than the lattice constant of germanium) The base is used to replace a base. In addition to yttrium, a compound semiconductor, for example, a mixed crystal of a fourth group such as SiGe or gallium arsenide can be used. For the SiGe block crystallization, the Institute of Materials Research at Tohoku University of Japan has published the growth of single crystal block siGe in a new research report summary for the scientific research grant program. A porous layer 26 is formed on the -SiGe or germanium substrate (as shown in Figure 6A). Since the crystallization of the rude is a crystallization from the beginning, the lattice is aligned to the substrate. A strained sand layer 13 is grown on the porous layer 26 (as shown in Figures -31 - 30, (28) 1284360 6B). The structure is bonded to a second substrate (component) as shown in Fig. 6C. Next, the portions are on the porous layer 26 (as shown in Fig. 6D). As with the plurality of examples described above, the female is removed such that a strained semiconductor substrate having the strained layer 13 on the second substrate (sound | 30 can be fabricated (as shown in FIG. 6E). Before the formation of 26, a Sh-xGex layer can be opened to reduce the difference in lattice constant with germanium. (Strain enthalpy and circuit obtained by hydrogen annealing) When a circuit component is formed by the strain enthalpy layer 13, a high speed can be obtained. A device with low energy consumption. The fabrication of the circuit device to form a semiconductor device will be described below. The surface can be planarized by polishing or hydrogen annealing, if desired. In the above plurality of examples, a strained semiconductor layer is made of a material having a lattice constant greater than a lattice constant of a single crystal semiconductor to form a strain sensing layer. The present invention can also be applied to another example in which a strained semiconductor layer is made of a material having a lattice constant smaller than the lattice constant of a single conductor and used to form a strained layer. For example, in order to form a tantalum strained semiconductor layer having a crystal number smaller than the lattice constant of a single crystal germanium, tantalum carbide or diamond may be formed to form the strain sensing layer. In the above plurality of examples, the tantalum strained semiconductor layer is directly on the tantalum substrate for use as the second substrate. However, the amorphous separation layer is obtained by obtaining a crystal. The crystal is used to form a layer. -32- (29) 1284360 For example: a polycrystalline germanium (including microcrystals) Or a non-crystalline germanium may be formed on the strained semiconductor layer or on the second substrate, and bonded such that the strained semiconductor layer may be formed on the polycrystalline germanium layer or the amorphous germanium layer (formed on the germanium) On the substrate, when the annealing is performed to firmly couple the bonded substrate, the amorphous germanium layer is converted into a polycrystalline crystal. The method for fabricating the semiconductor substrate of the present invention also includes such a form. A crystal layer or other structure formed on the germanium substrate is also included in the semiconductor substrate of the present invention. The semiconductor substrate does not necessarily need to be a single crystal substrate. A polycrystalline substrate can also be used. The semiconductor substrate may have a densely doped impurity layer formed on the surface. Alternatively, the substrate itself may contain a high concentration of impurities. Said that when a P + substrate or a substrate having a P + layer is used as the semiconductor substrate of the second substrate, and a strained semiconductor layer such as the same P-layer is bonded to the substrate, a P_/P The substrate can be manufactured. (Example of a semiconductor device) A semiconductor device using a semiconductor substrate manufactured by the semiconductor substrate manufacturing method as in the above-described plurality of examples, and a method of manufacturing the semiconductor device will be described below. Referring to Figures 7A to 7D, first, a semiconductor substrate is manufactured by using the semiconductor substrate (component) manufacturing method as in the above Examples 1 to 5. The semiconductor substrate has a strained layer on a substrate. Above, as described above, in the following description, the semiconductor substrate will be used as a strained ruthenium substrate. Compared to a normal Shih-33-(30) 1284360 substrate, a strained ruthenium substrate can be obtained. A higher speed jg. This is because the strained layer is superior to a layer without strain. In the step shown in Figure 7A, an active region 丨103', a transistor (eg: field A transistor, a MOS transistor or a pair of crystals to be formed, and a device insulating region 1054 are formed on the prepared strain 矽 substrate 1 002. In particular, the active region and the device insulating region 1054 may A method of patterning a strained layer 1 1 05 into an island shape, a LOCOS oxidation method, or a trench method, a gate insulating film, is formed by the following method: 5 6 is formed on the surface of the sand layer 1 1 〇 5. The material of the gate insulating film 1 〇 5 6 can be as follows: yttrium oxide, tantalum nitride, yttrium oxynitride Alumina, oxidized giant, bell, titanium oxide, cerium oxide, cerium oxide, cerium oxide, cerium oxide, oxygen or a glass mixture as described above. The gate insulating film 1 0 5 6 can be formed by a method of, for example, oxidizing the surface of the strained layer Π 0 5 by chemical vapor deposition or physical vapor deposition to deposit an insulating layer on the strained layer 1 105 on. A gate electrode 205 is formed on the gate insulating film 1 〇 56. The gate electrode 205 5 can be made of the following materials, for example, retanning of doped or n-type impurities; a metal 'for example: Tungsten, molybdenum, titanium, molybdenum or copper, or an alloy containing at least one of the above metals; a metal such as: molybdenum telluride, tungsten telluride or cobalt telluride; or a metal such as titanium nitride or nitride Tungsten or nitrided giant. The gate 1056 can be formed by forming a plurality of layers made of different materials: the device is electrically connected to a 1103', such as the oxygen oxide, the following, by means of a substance. The P-aluminum-deposited nitride film, such as -34-(31) 1284360, is the same polycrystalline metal telluride (p01 yc 1 d e) gate. The gate electrode 10 5 5 may be formed by, for example, a self-asigned silicide (salicide) method, a damascene gate process, or any other method. By the above steps, the structure as shown in Fig. 7A can be obtained. In the step as shown in Fig. 7B, an n-type impurity such as phosphorus, arsenic, antimony or a germanium type impurity such as boron is used by the active region 1 1 〇 3 ' to form a relative Very lightweight doped source and drain region 1 0 5 8 . This impurity can be used by ion implantation and annealing. An insulating film is formed to cover the gate electrode 105 5 and is etched back to form a side wall 159 9 on the side of the gate electrode 1 055. An impurity having the same conductivity as the above impurity is used by the active region 1 103' to form a relatively dense doped source and drain region 1 05 7 . By the above steps, the structure as shown in Fig. 7 can be obtained. In the step shown in Fig. 7C, a metal telluride layer 〇6 is formed on the upper surface of the gate electrode 1055, the upper surface of the source and drain regions 1057. As for the loose material of the metal telluride layer 106, the following materials can be used, for example, nickel telluride, titanium telluride, cobalt telluride, molybdenum carbide or tungsten telluride. The telluride may be formed by depositing a metal to cover the upper surface of the gate electrode 085 5, the upper surface of the source and drain regions 185, and performing annealing treatment. This causes the metal to interact with the underlying crucibles and remove an unreacted portion of the metal by an etchant (eg, sulfuric acid). If desired -35-(32) (32) 1284360, the surface of the telluride layer can be nitrided. By the above steps, the structure as shown in Fig. 7C can be obtained. In the step shown in FIG. 7D, an insulating film 1061 is formed to cover the upper surface of the gate electrode 1 0 5 5 converted into a germanide, and the source and drain regions of the 507 The upper surface. As the material of the insulating film 1061, a material such as cerium oxide containing phosphorus and/or boron may be used. If necessary, a contact hole is formed in the insulating film 1061 by a chemical mechanical honing method. When a yellow light process is used, it uses a cesium fluoride excimer laser, an argon fluoride excimer laser, a fluorine excimer laser, an electron beam, or an X-ray to form a side shorter than 0.2 5 μπι. A rectangular contact hole or a circular contact hole having a diameter of less than 0.2 5 μm. The contact holes are filled with a conductor. As for a suitable conductor charging method, a film of a refractory metal or a nitride thereof is formed on the inner surface of the contact hole as a barrier metal 1 062 (if necessary), and a conductor 1 0 6 3, for example: · A crane alloy, saw, alloy, copper or copper alloy is deposited by chemical vapor deposition, physical vapor deposition or electromineralization. The conductor deposited higher than the upper surface of the insulating film 1061 is removed by back etching or chemical mechanical honing. The surface of the telluride exposed to the source and drain regions of the bottom portions of the contact holes may be nitrided before the contact holes are filled with the conductor. By the above steps, a transistor (for example, a field effect transistor) can be formed on the strained layer so that a semiconductor device having a transistor can be obtained, and the transistor has a 7D The structure shown in the figure. -36- (33) (33) 1284360 In order to form a complementary MOS transistor, a p-type substrate is used as the strain 矽 substrate, and an n-well is formed in the P-channel MOS. On the substrate of the (PM0S) region. The 7th to 7th diagrams only illustrate one, the transistor area. In order to obtain a half of the conductor device which can achieve the desired function, a large number of transistors or other circuit components can be formed on the strained substrate, and interconnections therebetween can be formed. The present invention is used in a semiconductor substrate for forming a circuit component, such as a transistor on a strained semiconductor layer, a method of fabricating the semiconductor substrate, and a semiconductor device forming the circuit component. The present invention can provide a new technique, for example, forming a wafer having a strained germanium layer. With the semiconductor substrate of the present invention, the channel mobility can be increased by the strain without changing the process developed by the conventional germanium-large integrated circuit technology. While the present invention has been described above in terms of several preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Many aspects of the present invention can be more clearly understood by reference to the following drawings. The related drawings are not drawn to scale ', and their functions are only to present the relevant theorems of the present invention. In addition, the use of numerals to indicate the corresponding parts in the drawings 0 - 37 - (34) 1284360 Figure 1A illustrates a layered structure of a first substrate according to an example of the present invention; A joining step of Example 1; and a first C drawing illustrating a removing step according to Example 1 of the present invention; and a second drawing showing a layered structure of a first substrate according to Example 2 of the present invention, the second drawing system A joining step according to Example 2 of the present invention; a second C drawing illustrating a separating step according to Example 2 of the present invention; and a 2D drawing illustrating a removing step according to Example 2 of the present invention; A layered structure of a first substrate of Example 3 of the present invention; a third drawing illustrating a joining step according to Example 3 of the present invention; and a third C drawing illustrating a separating step according to Example 3 of the present invention; and 3D The figure illustrates a removal step according to Example 3 of the present invention; the fourth diagram illustrates a growth step according to Example 4 of the present invention; the fourth diagram illustrates a plating step according to Example 4 of the present invention; and FIG. 4C illustrates Example of the invention 4 is a layered structure of a first substrate, FIG. 4D illustrates a joining step according to Example 4 of the present invention; FIG. 4 is a view showing a separating step according to Example 4 of the present invention; and -38 - (35) 1284360 FIG. 4F illustrates a removal step according to Example 4 of the present invention; FIG. 5A illustrates a growth step according to Example 5 of the present invention; FIG. 5B illustrates a plating step according to Example 5 of the present invention; The figure illustrates a layered structure of a first substrate according to Example 5 of the present invention; FIG. 5D illustrates a joining step according to Example 5 of the present invention; and FIG. 5E illustrates a separating step according to Example 5 of the present invention; And FIG. 5F illustrates a removal step according to Example 5 of the present invention; FIG. 6A illustrates a plating step according to Example 6 of the present invention; and FIG. 6B illustrates a first substrate according to Example 6 of the present invention. Layered structure; Figure 6C illustrates a joining step in accordance with Example 6 of the present invention; Figure 6D illustrates a separating step in accordance with Example 6 of the present invention; and Figure 6E illustrates a removal in accordance with Example 6 of the present invention. Step; 7A~7D diagram A semiconductor substrate and a manufacturing method; and FIG. 8 is a sectional view of a state-based pore-sealing portion of the layer containing germanium for explaining (Si] _xGex layer) is formed as a porous surface layer. [Major component symbol description] 10 First substrate - 39 - 1284360 (36) 10' First substrate 10, First substrate 1 0, · First substrate 10, M First substrate 11 矽 Substrate 12 S i 1 - XG e X layer 13 strained layer 14 porous layer 14* the remaining part of the porous layer 14, the remaining part of the porous layer 15 Si]-yGey layer 16 porous layer 16' the remaining part of the porous layer 16 , the remaining part of the porous tantalum layer 2 1 SiGe or tantalum substrate 26 porous layer 26' the remaining part of the porous layer 26 · the remaining part of the porous layer 30 second substrate 40 porous layer 4 1 S i 1 - XG ex layer 1002 strain矽Substrate 1054 Component Insulation Zone 1055 Gate Electrode-40- 1284360 (37) 1056 Gate Insulation Film 1057 Source and Deuterium Zone 1058 Source and Bungee Zone 1059 Sidewall 1060 Metallization Layer 1061 Insulation Film 1062 Resistance Barrier metal 1063 conductor 1103' active 1105 strained layer

-41 -

Claims (1)

12843®^S'———η 少年年月峙日修(缘)正本10, Patent Application No. 93 1 40622 Patent Application Chinese Patent Application Revision Amendment April 28, 1995 Revision I A Semiconductor The substrate includes: a variable semiconductor layer on the semiconductor substrate, wherein the strained semi-conductive layer is made of the same material as the semiconductor substrate. 2. The semiconductor substrate of claim 1, wherein the material of the #conductor substrate and the strained semiconductor layer is germanium. 3. A method for fabricating a semiconductor substrate, comprising: a step of forming a strained semiconductor made of a first material, a % of a semiconductor material made of a second material, for making a $~ The substrate 'and at least on the surface thereof can be used as a strain sensing material; the stomach one step: bonding the strained semiconductor layer of the first substrate to a second substrate made of the β first material; and An in-piece on the side of the first substrate except the strained semiconductor layer is removed and the strained semiconductor layer is left on the second substrate. 4 Female mouth string | ; Ancient, '% #利利范围范围 The manufacturing method of the semiconductor substrate according to Item 3, wherein the first material is 矽. 5. The method of manufacturing a semiconductor substrate according to claim 3, wherein the material of the town is 矽, and the second material is Si].xGex, wherein the range of x is 6. The method of fabricating a semiconductor substrate according to claim 3, wherein the semiconductor substrate is a substrate having a strain sensing layer formed on a surface. 7. The method of fabricating a semiconductor substrate according to claim 6, wherein the semiconductor substrate is a substrate obtained by forming the strain sensing layer on a substrate. 8. The method of fabricating a semiconductor substrate according to claim 6, wherein a separation layer is formed under the strain sensing layer. 9. The method of fabricating a semiconductor substrate according to claim 6, wherein the strain sensing layer also functions as a separation layer. The method of manufacturing a semiconductor substrate according to claim 8, wherein the removing the member on the side of the first substrate in the third step comprises the step of separating the separation layer A portion of the member on the side of the first substrate. A method of fabricating a semiconductor substrate as described in claim 6 wherein the strain sensing layer is essentially made of tantalum and an additional material. 12. The method of fabricating a semiconductor substrate according to claim n, wherein the strain sensing layer is substantially made of Si Ge. A method of manufacturing a semiconductor substrate as described in claim 8 wherein the separation layer is essentially made of a porous material. The method of producing a semiconductor substrate according to claim 13 wherein the porous material is one of porous tantalum or porous SiGe. The method of manufacturing a semiconductor substrate according to claim 9, wherein the strain sensing layer which is also the separation layer is essentially made of porous tantalum. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the third step, the member on the side of the first substrate except the strain sensing layer remains in the first substrate On one side of the second substrate, the separation step on the separation layer is removed. The method of manufacturing a semiconductor substrate according to claim 3, wherein the three steps include a step of planarizing the strain sensing layer after the strain sensing layer is left on the second substrate. a surface. The method for manufacturing a semiconductor substrate according to claim 9, wherein the strain sensing layer which is also the separation layer is a porous layer which is introduced into the strain sensing for sealing at least the surface hole. material. A semiconductor device having a transistor in which the transistor is formed on a strain sensing layer of a semiconductor substrate as described in claim 1 of the patent application.