TW200522161A - Semiconductor substrate, manufacturing method thereof, and semiconductor device - Google Patents

Abstract

A separation layer is formed on a silicon substrate. An SiGe layer serving as a strain induction layer and a silicon layer serving as a strained semiconductor layer are formed sequentially on the separation layer to prepare a first substrate. The first substrate is bonded to a second substrate made of the same material as the silicon layer of the strained semiconductor layer. The structure is separated into two parts at the separation layer. When the residue of the separation layer and the SiGe layer are removed, and the surface is planarized by hydrogen annealing, an Si substrate having a strained silicon layer on the uppermost surface is obtained.

Description

200522161 ⑴ IX. Description of the invention [Technical field to which the invention belongs] The present invention relates to a semiconductor substrate, a manufacturing method thereof, and a semiconductor device. [Prior Art] A substrate with a strained sand layer has attracted much attention as a substrate is used to form a semiconductor device at a high speed and low energy consumption. A SiGe layer made of silicon and germanium is grown on a silicon substrate, and a single crystal silicon layer is grown on this layer. Therefore, a strain is applied to the silicon layer, and a strained silicon layer can be obtained. This strain occurs because the lattice constant of the SiGe layer is slightly larger than the lattice constant of the single crystal silicon layer. For example, US Patent No. 5,221,413 of AT & T company describes a substrate combining strained silicon, SiGe, and sand (Strained-Si / SiGe / Si). On the other hand, a silicon on insulator (SOI) substrate with a buried oxide film on a silicon substrate has also attracted much attention and is used as a substrate for high speed and low energy consumption. To form a semiconductor device. Structures that combine strained silicon with silicon on insulation have also been published in extensive research. This substrate is implemented to achieve two advantages, one is the high-speed operation performed by strained silicon, and the other is the low energy consumption performance and high operation speed performed by silicon on the insulating layer (see Shin for details) -ichi Tackagi, “Metal-Oxide-Semiconductior (Μ 0 S) device technologies using Si / SiGe heretointerfaces”, Oyo B uturi 9 vo 1. 72. no. 3 5 pp. 2 8 4- 2 90, 200522161 (2 ) 2 0 0 3). In this reference, the structure of the substrate and a substrate combining strained silicon, SiGe, insulator, and (strained-Si / SiGe / insulator / Si) is described. A type without a SiGe layer Strained silicon, insulators, and substrates of strained-Si / insulator / Si have also been published (see T. A. Lan gd 〇, et · a 1 · 5 A pp 1 · Phy s. Le 11 ·, v ο 1 · 2, η〇 · 2 4, pp. 4256-425 7, 2003). In this method, strained silicon / SiGe formed on a first substrate is implanted and bonded by hydrogen ions. And after being separated and converted into an insulating substrate, the SiGe layer is removed. In the current silicon-large-scale integrated circuit (Si-LSI), all the above-mentioned technologies require further optimization of the device and process design. The existence of SiGe has been described in this paper by TA · Langdo, et. Al. However, there are still other problems, such as the differences between doping diffusion performed by annealing, metal contact forming, and germanium diffusion. In addition, due to the appearance of the insulating layer, there is also a structure with an insulating layer. The same problem as silicon on the insulating layer also includes the problem of thermal deposition of the device operation. [Summary of the Invention] The present invention proposes a new technology to form based on the problems of the conventional technology described above and has its purpose. A silicon wafer with a strained silicon layer (this is taken as an example). According to a first aspect of the present invention, a semiconductor substrate is provided, including: a strained semiconductor layer on the semiconductor substrate, wherein the strained semiconductor layer is formed by the semiconductor layer and the The semiconductor substrate is made of the same material. The semiconductor substrate package-200522161 (3) 3 at least one single crystal semiconductor substrate and polycrystalline semiconductor substrate It also includes a substrate having a polycrystalline semiconductor (including a microcrystalline semiconductor layer) formed on a semiconductor substrate. According to a second aspect of the present invention, a method for manufacturing a semiconductor substrate of the present invention is provided, including: a first A step of forming a strained semiconductor layer made of a first material on a semiconductor substrate made of a material and used to make a first substrate, and at least on its surface can be used as a strain Use of induction materials; a second step: bonding the strained semiconductor layer of the first substrate to a second substrate made of the first material; and a second step of removing the first substrate A member on one side other than the strained semiconductor layer, and the strained semiconductor layer is left on the second substrate. According to a third aspect of the present invention, a semiconductor substrate manufactured by the above manufacturing method is proposed. According to a fourth aspect of the present invention, there is provided a semiconductor device 'having a field effect crystal formed on the strain sensitive layer of the semiconductor substrate. With the semiconductor layer of the present invention, the channel mobility can be increased by the strain without changing the process developed by the conventional silicon-mass integrated circuit technology. Other features, objects, and advantages of the present invention will be described in detail below and more clearly described with accompanying drawings, wherein in all the drawings, the same reference numerals indicate the same or similar elements. 200522161 (4) [Embodiments] Some preferred embodiments of the present invention will be described in detail as follows. However, in addition to the following description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited by the embodiments, and it is subject to the scope of subsequent patents. Furthermore, in order to provide a more concise description and easier understanding of the present invention, the parts in the drawings have not been drawn according to their relative dimensions. 'Some dimensions have been exaggerated compared to other related dimensions; irrelevant details are not complete. Draw for brevity. (First Embodiment) A strain sensing layer is formed on the surface of a semi-conductive substrate made of a second material. A strained semiconductor layer made of the second material is formed on the strain-sensing layer to make a first substrate. A second substrate made of a primary material is bonded to the first substrate. The semiconductor substrate and the strain sensing layer made of the first material are removed. Therefore, the strained semiconductor layer made of the first material can be formed on the second substrate made of the first material to be in contact with the second substrate. For the first and first materials, sand is generally used. The strain-sensing layer 'is formed of a layer (Si) _xGex layer containing silicon and germanium. The (preferably a single crystal sand layer) is almost made of sand and is formed on the SlixGex layer as a strained semiconductor layer. -8- 200522161 (5) formed on the semiconductor substrate made of the second material

In the Sii-xGex layer, x preferably falls within a range of 0 to 0.5. More preferably, on the surface of the semiconductor substrate, X is almost 0 and gradually changes. On the highest surface, that is, where the strained semiconductor layer is formed, X is more preferably in the range of 0.1 to 0.5. Lattice relaxation occurs at least on the highest surface so that the strain there is minimal. The member 'on the side of the first substrate except the strained semiconductor layer can be removed by a mechanical removal method, such as a honing method or a polishing method. Alternatively, before bonding and after bonding, hydrogen ions can be implanted on the semiconductor substrate or the strain sensing layer made of the second material, and the portion can be implanted on the implant interface. Separation. The Si! _XGex layer on the strained semiconductor layer is removed by a polishing method or a chemical etching method. After the Si ^ Gex layer is removed and only the strained semiconductor layer is edged on the first substrate, the surface planarization is completed. The manufacturing method according to the first embodiment of the present invention may further include a step of forming a circuit element by using the strained semiconductor layer as an active layer. For a device having such a circuit element, a high-speed operation can be performed by the strained semiconductor layer. (Second embodiment) A separation layer is formed on the surface of a semiconductor substrate made of a second material. A strain sensing layer is formed on the separation layer. In addition, a strained semiconductor layer made of a first material is formed on the application layer to form a first substrate. A second substrate made of the first material is bonded to the first substrate. The parts are separated at the separation layer. Then, the remaining separation layer and the strain sensing layer are removed. Therefore, the strain-conducting conductor layer 'made of the first material can be formed on the first substrate of the piano made of the first material' and contact the substrate. The first and second materials generally use silicon. The separation layer can usually be formed by polishing the surface of the semiconductor substrate (silicon substrate) made of the second material using a plating method. As for other methods, after the strain sensing layer and the sensing semiconductor layer are formed, ions (for example, chloride ions) are implanted in the strain sensing layer or the semiconductor substrate made of the second material. To form the separation layer. As for the strain sensing layer, it is formed of a layer containing germanium (Sii xGex layer). This layer (preferably a single crystal silicon layer) is almost made of sand, and is formed on the SinGex layer as a strained semiconductor layer. In the Si bxGex layer formed on the separation layer, X preferably falls within a range of 0 to 0.5. More preferably, 'X is almost 0 on the surface of the separation layer and gradually changes. On the highest surface, that is, where the strained semiconductor layer is formed, X is preferably from 0.i to 0.5. Lattice relaxation occurs at least on the highest surface so that the strain there is minimal. When the separation layer is a porous layer, the separation step is performed by a wedge insertion method, application of tension / shear force, liquid jet (water jet) injection method, air jet injection method, or ultrasonic application. When the separation layer is formed by the ion cloth-10-200522161 (7) implantation method, the strain chemical etching method is used at the temperature of ° C to leave the Sih on the second substrate. According to the present invention, there is a step: borrow A circuit element. The calculation can be performed by (the third real and a separation layer bottom on the surface, from a first change induction layer, from the first bottom. These parts and the strain-induced strain semiconductor layer substrate, and the first The half of the separation layer, the separation step must be completed by annealing at 200 ~ 300 ° C to 5 00 ~ 600. The Si nGex layer on the semiconductor layer is' polished or removed. XGex layer After being removed, and only the strained semiconductor layer is on the bottom, the surface planarization is completed. It is clear that the manufacturing method of the second embodiment can further include forming the strained semiconductor layer as an active layer. For the device of the circuit element, a high-speed semiconductor layer is implemented. Example) The semiconductor layer is formed on a semiconductor substrate made of a second material. A strain sensing layer is formed on the separation layer. A strained semiconductor layer made of this material is formed on the application to make a first substrate. A second substrate made of material is bonded to the first substrate and is separated at the separation layer. Then, the remaining separation layers are removed. Therefore, the substrate made of the first material may be formed in contact with the second substrate made of the first material. The second material is generally silicon. It can usually be formed by polishing the surface of the first substrate M '/ Leyicai using an electroplated conductive substrate (silicon substrate). -11-200522161 (8) As for the strain-sensing layer, the pore sealing material formed by a layer (SibxC} e) containing germanium is used as the porous surface layer. This layer (preferably a single crystal silicon layer) is almost made of silicon, and is formed on the Si ^ Gex layer as a strained semiconductor layer. Fig. 8 is a sectional view for explaining a state where the germanium-containing layer (Si bXGex layer) is formed as the pore sealing portion of a porous surface layer. As shown in FIG. 8, the pores of the surface layer of a porous layer 40 are filled with a Sil_xGex layer 41 ′ so that the silicon surface is covered by the Si HGex layer 41. In the strain-inducing Si bXGex layer, X preferably falls in the range of 0 to 0.5. More preferably, the Si x Gex layer is formed by filling a plurality of pores in the porous surface layer. Lattice relaxation occurs at least on the highest surface so that the strain there is minimal. When the separation layer is a porous layer, the separation step is performed by wedge insertion method 'application of tension / shear force, liquid jet (water jet) injection method, air jet injection method or ultrasonic application. The Si] .xGex layer on the strained semiconductor layer is removed by a polishing method or a chemical etching method. After the layer is removed, and only the strained semiconductor layer is left on the second substrate, the surface planarization is completed. The manufacturing method according to the third embodiment of the present invention may further include a step of forming a circuit element by using the strained semiconductor layer as an active layer. For a device having such a circuit element, a high-speed operation can be performed by the strained semiconductor layer. -12-200522161 (9) (Fourth embodiment) A layer containing germanium (Si1_XGex layer) is formed on the surface of a semiconductor substrate made of a second material. Next, a porous SiGe layer is formed as a separation layer by annealing. A layer (Si ^ Gex layer) containing germanium is formed again on the porous SiGe layer to serve as a strain sensing layer. This layer (preferably a single crystal silicon layer) is almost made of sand, and is formed on the Sll_xGex layer as a strained semiconductor layer made of a first material, thereby making a first A base. A second substrate made of the first material is bonded to the first substrate. The parts are separated at the separation layer. Then the 'the remaining separation layer and the SiGe layer are removed. Therefore, the strained semiconductor layer made of the first material can be formed on the second substrate made of the first material and contact the first * substrate. The first and second materials generally use silicon. In the Si] xGex layer as a strain sensing layer, χ preferably falls within a range of 0.1 to 0.5. More preferably, 'X is almost 0 on the surface of the semiconductor substrate and gradually changes. On the highest surface, X is preferably 0 ·: [to 0 · 5. Lattice relaxation occurs at least on the highest surface so that the strain there is minimal. When the separation layer is a porous layer, the separation step is performed by wedge insertion method, application of tension / shear force, liquid jet (water jet) injection method, air jet injection method, or ultrasonic application . The S i! _ X G e χ layer on the strained semiconductor layer is removed by a polishing method or a chemical etching method. -13- 200522161 (10) After the Si bxGex layer is removed, and only the strained semiconductor layer is left on the second substrate, the surface planarization is completed. The manufacturing method according to the fourth embodiment of the present invention may further include a step of forming a circuit element by using the strained semiconductor layer as an active layer. For a device having such a circuit element, a high-speed operation can be performed by the strained semiconductor layer. (Fifth embodiment) A layer (SiHGex layer) containing germanium is used as a strain sensing layer formed on the surface of a semiconductor substrate made of a second material. Next, a porous SiGe layer is formed as a separation layer by annealing. In the strain-sensitive Sh.xGex layer formed on the semiconductor substrate made of the second material, X preferably falls within a range from ο · to 〇5. More preferably, on the surface of the semiconductor substrate, χ is almost 0 and gradually changes. On the highest surface, X is preferably from 0.1 to 0.5. Lattice relaxation occurs at least on the highest surface so that the strain there is minimal. Therefore, the Si! -XGex layer functions almost like the same strain-sensitive layer, even after the porosity is formed. The layer (preferably a single crystal silicon layer) is almost made of sand, and is formed on the S i 1 · x G ex layer as a strained semiconductor layer made of a first material, This is used to make a first substrate. A second substrate made of the first material is bonded to the first substrate. The parts are separated at the separation layer. Then, the remaining separation layer and the Si ^ Gex layer are removed. Therefore, the -14-200522161 (11) strained semiconductor layer 'made of the first material may be formed on the second substrate made of the first material to be in contact with the second substrate. The first and second materials generally use silicon. When the separation layer is a porous layer, the separation step is performed by wedge insertion method, application of tension / shear force, liquid jet (water jet) injection method, air jet injection method, or ultrasonic application. The strain on the strained semiconductor layer is removed by a polishing method or a chemical etching method. After the Si ^ Gex layer is removed, and only the strained semiconductor layer is left on the second substrate, the surface planarization is completed. The manufacturing method according to the fifth embodiment of the present invention may further include a step ... forming a circuit element by using the strained semiconductor layer as an active layer. For a device having such a circuit element, a high-speed operation can be performed by the strained semiconductor layer. Some examples of the present invention will be described below with accompanying drawings. The following examples 1 to 5 correspond to the first to fifth embodiments described above, respectively. (Example 1) A method for manufacturing a semiconductor substrate (component) according to Example 1 of the present invention will be described below, and please refer to FIGS. 1A to 1C. In this step (thinning step) as shown in FIG. 1A, a first substrate (part) 10 having a layer (Si ^ Gex layer) 12 containing silicon and germanium (an additional material) is formed on a substrate. A silicon layer 13 is formed on the silicon substrate 11 and a Si layer is formed on the Si Ge layer. -15- 200522161 (12) (Crystalline film growth of the SiGe layer) First, the strain-inducing SinGex layer 12 (X is from 0.1 to 0.5, and χ = 0.3) is used as an example. It is heated by an irradiator to grow a 11 film on the silicon substrate. These preferred growth conditions are described below. It should be noted that pre-baking can be performed before growing. • The flow rate of the carrier gas (Η2) Η2 is preferably 25 to 45 liters / minute, and usually 30 liters / minute. • First source gas (SiH4)

The flow rate of SiH4 is preferably 50 to 200 cm3 / min, and usually it is cm3 / min. • The second source gas (2% GeH4) The flow rate of 2% GeH4 is preferably 20 ~ 500 cm3 / min, and usually 300 cm3 / min. • Cavity air pressure The cavity air pressure is preferably 10 to 100 Tao, and usually 100 Tao. • Temperature (base temperature) The temperature is preferably 65 0 ~ 680 ° C. • Growth rate The growth rate is preferably 10 to 50 nm / minute. -16- 200522161 (13) The production ratio of germanium can be changed according to the mixing ratio of the source gas. Preferably, in the initial stage of growth on the single crystal silicon substrate, the germanium concentration is set to be low, and increases as the crystal film growth progresses. The proportion of germanium is preferably such that X is set to be from 0.1 to 0.5. The strain on the highest surface can be relaxed, for example: introduced defects. In addition, it is also preferable that the surface of the silicon substrate 11 is annealed (pre-dried) under a hydrogen gas before the Si ^ Gex layer 12 is grown. In the pre-drying, the flow rate of hydrogen is preferably 15 to 45 liters / minute, and usually 40 liters / minute. The temperature is preferably 700 to 1000 ° C, and usually 95 0 ° C. The cavity air pressure is preferably 10 to 760 Tao, and usually 80 Tao. In the initial stage, the single crystal silicon layer is preferably grown at a low growth rate, usually 50 nm / min or less. When a sample is loaded into or unloaded from the chemical vapor deposition device, a natural oxide film formed on the surface can be used in each step before loading in the device. The surface was immersed in a dilute hydrofluoric acid solution to remove it. (Formation of Strained Silicon Layer) Next, the single crystal silicon layer 13 is grown on the Si] .xGex layer 12 by a chemical vapor deposition method. The lattice constant of the single crystal silicon layer 13 formed in this way is different from the lattice constant of the Si! _XGex layer 12 underneath, and therefore, it acts as the same strained silicon layer. According to this example, between the strained silicon layer 13 and the S; h.xGex layer 12, the Si close to the interface] .xGex -17- 200522161 (14) the concentration of germanium in layer 12 can be accurately To control. In addition, the concentration distribution at this interface may be a uniform (planar) distribution. Therefore, the strain of the strained silicon layer formed on the S: h_xGex layer 12 can be easily controlled. For this reason, a high-quality strained silicon layer 13 can be obtained. The growth conditions of the single crystal silicon layer as the strained silicon layer 13 are as follows: The flow rate of the carrier gas (H2) hydrogen is preferably 15 to 45 liters / minute, and usually 30 liters / minute. . • Source gas (SiH4) The flow rate of the source gas is preferably 50-50 cm3 / min, and usually 100 cm3 / min. • Cavity air pressure The cavity air pressure is preferably 10 to 100 Taor, and usually 80 Tao. • Growth temperature (substrate temperature) The growth temperature is preferably 650 ~ 1000 ° C, and usually 900 ° C. • Growth rate The growth rate is preferably 10 to 500 nm / min. (Completion on the side of the first substrate) Through the above steps, the first -18- | 12 200522161 shown in Figure 1A can be obtained (15) The substrate (part) 1 0 ° is caused by multiple steps The si i. X G exf \ and the strained silicon layer 1 3 have been described above, and the Si hGex layer 12 can also be formed by a single (eg, chemical vapor deposition method) 12 the strained silicon layer 1 3, which is By gradually or gradually changing the concentration of germanium (or other gases) and other conditions. (Joining) After this step as shown in FIG. 1A and then in this step (joining step) as shown in FIG. 1, a second base member is bonded to the first base (part) 1 0 Of the upper surface side. A substrate (component) 10 and the second substrate (component) 30 may be bonded. Alternatively, plating or annealing may be performed 'for a substrate to be firmly attached to the substrate'. The second substrate (the component is usually a sand substrate. The joining surfaces of the two substrates to be joined preferably need to undergo a hydrophobic treatment (also applied to the following examples because this joining surface is hydrophobic By nature, a sand oxide is formed in the bonding interface. (Removal of the substrate) After this step as shown in Fig. 1B, it is followed by the ghai step (removal step) as shown in Fig. I. The silicon substrate 1], which is a substrate (bonded substrate stack) formed by the bonding step, is removed. The removal step can be performed by a mechanical removal method, such as honing and polishing, or a Chemical removal methods, such as: wet etching step and concentration B) 30 should be simpler than 30), and) ° should be divided by the C shape of the film. French, Engraved or -19- 200522161 (16)

Dry etching is done. If the substrate is removed by chemical axe method, a mixed solution containing potassium hydroxide, potassium dichromate, propanol, and water will be used. Silicon can be removed with selectivity related to Si0.7Ge (). 3 about 20 times (for details, see D.J. Godbey, et. A1., App1. Phys Lett., Vol. 56? no. 4? pp. 3 73 -3 79, 1 990). Another option is that when EDP Ethylene Diamine Pyrochatechol is used, the sand can be removed at a temperature of 82 ° C with a selectivity related to Sio.72Geo.28 about 390 times. (Please refer to D. Feijoo, et. Al ”J. Electro. Mat., Vol. 23, no. 6, pp. 493 -496, 1 994 for details.) In addition, the SinGex layer 12 is removed. The SihXGex The layer 12 can be removed by, for example, a polishing method or a chemical etching method. It is assumed that the Si nGex layer 12 is removed by a chemical etching method, which contains hydrofluoric acid (0.5%), nitric acid, and water (in 5: A ratio of 40:20) was used. SiG.7Ge (). 3 can be removed by silicon-related selectivity about 13 times (for details, see AH Krist, et. Al., Appl. Phys · Let.? Vol. 5 8? No. 17, pp. 1 8 99- 1 90 1, 1991) o That is, a conversion step is performed by the joining step as shown in FIG. The removal step shown in Figure 1C is performed. Figure 1C is a cross-sectional view illustrating the semiconductor substrate manufactured according to Example 1 of the present invention. (Strain sand and hydrogen annealing) Circuit) When a circuit element is formed by the strained silicon layer 13, -20-200522161 (17) can be obtained as a device with a fast speed and low energy consumption. The formation of the circuit element (a semiconductor device) (Manufacturing) will be described below. If necessary, the surface can be planarized by polishing or hydrogen annealing. (Example 2) According to Example 2 of the present invention-a method for manufacturing a semiconductor substrate (component) will be described below. Please refer to FIGS. 2A to 2D. Before the formation of the Sh-xGex layer in Example 1, a porous layer was formed on the surface close to a sand substrate u as a separation layer. (Plating) First, a porous silicon Layers 14 and 4 are formed on the single-crystal silicon substrate 11 by electroplating. Generally, electroplating is completed in the following manner, that is, a solution containing hydrofluoric acid is filled with a plating tank having a platinum electrode pair, and two electrodes The silicon substrate 11 is placed in between, and a current is provided between the two electrodes. The porous silicon layer 14 formed by this step has a fragile structure and is used as a separation layer in a later separation step. For electroplating, The technique disclosed in Japanese Patent Application No. 7-3 02 8 8 9 can be used as its plating conditions. A protective film, such as an oxide film, can be formed on the surfaces of the pores inside the porous silicon layer 14. Alternatively, a plurality of layers having different porosities can be formed by controlling the plating solution or current. For example, a first porous layer may be formed on the side of the surface, and a second porous layer having a higher porosity may be formed on the -21-200522161 (18) of a porous layer below. (SiGe / 5 Xijiajing bonding) Forming a strain induction 12 containing silicon and germanium (attachment) and a strained sand layer 13 on the porous silicon layer 14 The steps of bonding the first substrate to the second substrate are Example 1 A first substrate (part) 10 'has a structure as shown in Fig. 2A, and a structure shown in Fig. 2B is obtained by this joining step. It is also preferable that the surface of the porous silicon layer 14 is subjected to a hydrogen fire (pre-baking) before the porous silicon layer 14 is formed in the Si layer 12. In the pre-drying, the flow rate of hydrogen is preferably 15 to 45 liters / minute, and usually 40 liters / minute. The temperature ranges from 700 to 100CTC, and is usually 95 ° C. The cavity pressure is 10 to 760 Tau, and usually 80 Tau. In the initial stage, the crystalline silicon layer is preferably grown at a low growth rate, usually 50 minutes or less. When a sample is loaded in the chemical vapor deposition device or unloaded from the chemical vapor deposition device, a natural film formed on the surface can be immersed in the surface in each step before loading the device. Remove in diluted hydrofluoric acid solution. (Removal of the substrate) After this step as shown in FIG. 2B, and then in this step (separation step) as shown in FIG. 2, the material added by the joining step is the same.结构。 Structure. Secondly, the multi-gas receding ground system is a better ground system, the single nanometer / oxidation from the chemical, and the 2C map into the -22- 200522161 (19) substrate (bonded substrate stack), The separation layer 14 is separated into two substrates in part. That is, one turn of the joining step shown in Fig. 2B and performed as shown in Fig. 2C. This separation step can be performed by injecting the first substrate 14 with its axis rotating the bonded substrate stack. The reference numerals 14 'and 14' 'are used to indicate the porous layer left on the substrate. Separation methods using tensile, compressive, or shear stress Using a fluid, such as the above separation of liquids or gases. Alternatively, these methods can be used in combination. The multi-etching method, polishing method, honing method, or a flame containing hydrogen is used to remove the second substrate 30 after separation. In order to remove the pore layer 14 by etching, "the surface area of the porous layer can be selected by using a solution containing hydrofluoric acid, a hydrogen peroxide solution and a selectivity of about 1: 1.05. Has been used, his silicon etchant to selectively remove. In addition, the Sh_x Gex layer 12 is removed. The Si is removed by, for example, polishing or chemical etching. Sii-xGex Μ is removed by chemical etching. One (0.5%), nitric acid, and water (in a ratio of 5:40:20 are removed). Use. Si〇.7Ge (). 3 can be removed by $ times related to silicon (for details, see AH Krist, Phys. Lett "vol. 58, no. 17, ρρ. 1 8 9 9- 1 90 1, (porous silicon layer) The change step is shown by the separation step shown in the example. For example, when it is separated from the body to the separation layer, these can be used instead. The pore layer 1 4 " The reducing air descends the porous layer, and the water and the water mixture are removed sexually. The hGex layer 12 can also be used. Assuming that the type containing hydrofluoric acid is mixed, the selectivity is about 1 3 e t. a 1.? A pp 1. 1991). -23- 200522161 (20) Figure 2D is a cross-sectional view illustrating the semiconductor substrate manufactured according to Example 2 of the present invention. (Strained silicon and hydrogen The circuit obtained by annealing) When a circuit element is formed by the strained silicon layer 13, a device with high speed and low energy consumption can be obtained. The shape of the circuit element The fabrication (manufacturing of a semiconductor device) will be described below. If necessary, the surface can be planarized by polishing or hydrogen annealing. (Example 3) Example 3 according to the present invention-Method for manufacturing a semiconductor substrate (component) It will be described below, and please refer to FIGS. 3A to 3D. In the step of forming the Si HGex layer of Example 2, the pores of the porous layer can be sealed by germanium. (Plating) First, a porous silicon layer 14 is formed on the single crystal silicon substrate 11 by electroplating, as shown in FIG. 3A. Usually, the electroplating is completed in the following manner, that is, a solution containing hydrofluoric acid is filled with a platinum electrode pair. A plating tank, the silicon substrate 11 is placed between the two electrodes, and a current is provided between the two electrodes. The porous silicon layer 14 formed by this step has a fragile structure and is used as a later A separation layer in the separation step. For electroplating, the technique disclosed in Japanese Patent Application No. 7-3 02 8 8 9 can be used as its plating conditions. -24- 200522161 (21) A protective film, such as: An oxide film can be formed on the On the surfaces of the pores inside the porous silicon layer 14. Alternatively, a plurality of layers having different porosities can be formed by controlling the plating solution or current. For example, a first porous layer can be formed On the side of the surface, a second porous layer having a higher porosity may be formed under the first porous layer. (The pores are sealed by SiGe) The surfaces of the porous silicon layer 14 Faces can be sealed by Sii_xGex. These preferred growth conditions are described below. Note that pre-baking (described below) can be performed before growing. • The flow rate of the carrier gas (H2) H2 is preferably 25 to 45 liters / minute, and usually 30 liters / minute. • First source gas (SiH4)

The flow rate of SiH4 is preferably 50 to 200 cm 3 / min, and usually 100 cm 3 / min. • The second source gas (2% GeH4) The flow rate of 2% GeH4 is preferably 20 ~ 500 cm3 / min, and usually 300 cm3 / min. • Cavity air pressure The cavity air pressure is preferably 10 to 100 Tao, and usually 100 Tao. -25- 200522161 (22) • Temperature This temperature is preferably from 6 50 to 68 ° C. • Growth rate The growth rate is preferably 5 to 20 nm / minute. The manufacturing ratio of the germanium of the sealed SinGex layer can be changed according to the mixing ratio of the source gas. Preferably, the X system is from 0.1 to 0.5. Due to the presence of surface holes, the strain on the sealing layer can be relaxed. By this step, the strain-inducing Si ^ Gex layer is formed. In addition, it is also preferable that the surface of the chopped substrate 11 is annealed (pre-dried) under a hydrogen gas before the pores are sealed. In the pre-drying, the flow rate of hydrogen is preferably 15 to 45 liters / minute, and usually 40 liters / minute. The temperature is preferably 700 to 1 000 ° C, and usually 950 ° C. The cavity air pressure is preferably 10 to 760 Taur, and usually 80 Taur. When a sample is loaded into or unloaded from the chemical vapor deposition device, a natural oxide film formed on the surface can be used in each step before loading in the device. The surface was immersed in a dilute hydrofluoric acid solution to remove it. (Si epitaxial bonding to completion) A silicon layer 13 is formed on the SiGe sealing layer, and the steps up to completion are the same as those in Example 2. A first substrate (part) 10 ″ has a knot as shown in FIG. 3A. The structure shown in Fig. 3B is obtained by this joining step. After separation, the substrate is divided into two parts, as shown in Figure 3C of -26- 200522161 (23), and a conversion step is performed. Figure 3D is a sectional view illustrating the semiconductor substrate manufactured according to Example 3 of the present invention. (Strain sand and circuit obtained by hydrogen annealing) When a circuit element is formed by the strained silicon layer 13, a device with high speed and low energy consumption can be obtained. The formation of this circuit element (a manufacturing of a semiconductor device) will be described below. If necessary, the surface can be planarized by polishing or hydrogen annealing. (Example 4) A method for manufacturing a semiconductor substrate (component) according to Example 4 of the present invention will be described below, and please refer to FIGS. 4A to 4D. A SiGe layer formed on ~ #, vS substrate 1 1 is made porous, thereby replacing the porosity of the substrate of Example 2.

(Crystalline film growth of SiGe layer)

As shown in Fig. 4A, containing silicon and germanium (with additional material 15 (Si ^ yGey layer, y system is 0 "to 0.5, and y = 〇3 as an example) by chemical vapor deposition method 'and Heating via an irradiator is required for the growth of the 1 1 crystal film on the single crystal eve. The preferred growth conditions are as follows. Note that 'pre-drying can be performed before growth. Carrier gas (H2) -27- 200522161 (24) The flow rate of H2 is preferably 25 ~ 45 liters / minute, and usually 30 liters / minute. • First source gas (SiH4)

The flow rate of Si Η * is preferably 50 to 2000 cm 3 / min, and usually 100 cm 3 / min. • The second source gas (2% GeH4) The flow rate of 2% GeH4 is preferably 20-50 cm3 / min 'and usually 300 cm3 / min. • Cavity air pressure The cavity air pressure is preferably 10 to 100 Tao, and usually 100 Tao. • Temperature (base temperature) The temperature is preferably from 6 50 to 68 ° C. • Growth rate The growth rate is preferably 10 to 50 nanometers / minute. The production ratio of germanium can be changed according to the mixing ratio of the source gas. Preferably, in the initial stage of growth on the single crystal silicon substrate, the germanium concentration is set to be low, and increases as the crystal film growth progresses. The germanium ratio is preferably finally set to y to be 0.1 to 0.5. The strain on the highest surface can be relaxed, for example: introduced defects. (SiGe plating) After this step as shown in FIG. 4A and then in this step (plating step) as shown in FIG. 4B, a porous silicon layer 16 is electrically charged by -28- 200522161 (25 ) Is formed on the Si ^ Gey layer 15. Generally, the electroplating is completed in the following manner, that is, a solution containing hydrofluoric acid is filled in a plating storage tank having a platinum electrode pair, the silicon substrate 11 having the sil_yGey layer 15 is placed between the two electrodes, and A current is provided between the electrodes. The porous silicon layer 16 formed by this step has a fragile structure and is used as a separation layer in a later separation step. A protective film, such as an oxide film, may be formed on the surfaces of the pores inside the porous silicon layer 16. When Si Ge is oxidized, silicon dioxide is formed on the surface, and germanium is pushed inward. An oxide film is formed on the surfaces of the internal pores. Alternatively, a plurality of layers having different porosities can be formed by controlling the plating solution or current. For example, a first porous layer may be formed on the surface side of the Si ^ Gey layer 15, and a second porous layer having a higher porosity may be formed on the first porous layer. below. Compared to the Si layer 15, the porous layer 16 can be deeper and reach the silicon substrate 1 1 (while the porous layer 16 in FIG. 4B does not reach the silicon substrate 丨 丨). Since forming the porous layer by electroplating is an electrolytic etching method, it can easily and selectively etch these defects. Therefore, after the formation of the porous layer, the defects introduced during the formation of the Si! _YGey layer 15 hardly remain in the remaining portion of the single crystal sand layer. As a result, the crystallinity is restored. (SiGe / silicon epitaxy to completion) Formation of a strain sensor containing silicon and germanium (additional material) -29-200522161 (26)

The Si_xGex layer 12 on the porous layer 16 and the steps up to completion are the same as those in Example 2. —The first substrate (part) 10... Has a structure as shown in FIG. 4C. The structure shown in Fig. 40 is obtained by this joining step. After separation, the substrate is divided into two parts, as shown in the figure, and a conversion step is performed. Figure 4F is a sectional view for explaining the semiconductor substrate manufactured according to Example 4 of the present invention. (Strained silicon and circuit obtained by hydrogen annealing) When a circuit element is formed by the strained silicon layer 13, a device with high speed and low energy consumption can be obtained. The formation of the circuit element (the manufacture of a semiconductor device) will be described below. If necessary, the surface can be planarized by polishing or hydrogen annealing. (Example 5) Example 5-Method for Manufacturing Semiconductor Substrate (Part) According to the Invention The following will be described, and please refer to FIGS. 5A to 5F. If lattice relaxation has occurred on the surface of the porous SiGe layer of Example 4, a strained silicon layer 13 can be formed thereon without forming another SiGe layer. The remaining steps are the same as in Example 4. Fig. 5A is a sectional view for explaining the epitaxial step of the SiGe layer. Fig. 5B is a sectional view illustrating the joining step. A first substrate (part) 10 ... 'has a structure as shown in Fig. 5C. The structure shown in Fig. 5D is obtained by this joining step. After separation, the substrate is divided into two parts, as shown in Figure 5E, and a conversion step -30- (27) 200522161 is performed. Fig. 5F is a sectional view illustrating the semiconductor substrate manufactured according to Example 5 of the present invention. (Strained silicon and circuit obtained by hydrogen annealing) When a circuit element is formed by the strained silicon layer 13 ', a device with high speed and low energy consumption can be obtained. The formation of this circuit element (a manufacturing of a semiconductor device) will be described below. If necessary, the surface can be planarized by polishing or hydrogen annealing. (Example 6) According to Example 6 of the present invention-a method for manufacturing a semiconductor substrate (component), which will be described in the following I, and please refer to FIGS. 6A to 6E. (Semiconductor substrate) A semiconductor substrate made of the second material as described in Examples 4 and 5 and made of a material (eg, _, whose lattice constant is greater than the lattice constant of silicon) The substrate is used to replace a silicon substrate. Except germanium

Ten ", 亡 4 / 偕 1 j 26 is a lumpy crystal, and the crystal lattice is grown on the porous layer 26 (as shown in Fig. 31-200522161 (28) 6 B) . The structure is bonded to a second substrate (part) 30, as shown in FIG. 6C. Then, the portions are separated on the porous layer 26 (as shown in FIG. 6D). As in the above examples, the separation layer is removed so that a strained semiconductor substrate having the strained silicon layer 13 on the second substrate (component) 30 can be manufactured (as shown in FIG. 6E). Before the porous layer 26 is formed, a Si ^ Gex layer may be formed to reduce the difference in lattice constant from silicon. (Strained silicon and circuit obtained by hydrogen annealing) When a circuit element is formed by the strained silicon layer 13, a device with high speed and low energy consumption can be obtained. The formation of this circuit element (a manufacturing of a semiconductor device) will be described below. If necessary, the surface can be planarized by polishing or hydrogen annealing. In the above examples, a strained semiconductor layer is made of a material having a lattice constant greater than that of a single crystal semiconductor, and is used to form a strain sensing layer. The present invention can also be applied to another example, that is, a strained semiconductor layer is made of a material having a lattice constant smaller than that of a single crystal semiconductor, and is used to form a strain sensing layer. For example, in order to form a silicon strained semiconductor layer and its lattice constant is smaller than that of a single crystal silicon, silicon carbide or diamond can be used to form the strain sensing layer. In the above examples, the silicon strained semiconductor layer is directly formed on the silicon substrate and serves as the second substrate. However, the amorphous layer, -32- 200522161 (29) For example: a polycrystalline silicon (including microcrystalline silicon) or amorphous silicon can be used to form the strained semiconductor layer or the second substrate, and be bonded so that The strained semiconductor layer may be formed on the polycrystalline silicon layer or the amorphous silicon layer (formed on the silicon substrate. When annealing is performed to firmly couple the bonded substrate, the amorphous silicon layer is converted into a complex Crystal) on. The method for manufacturing a semiconductor substrate of the present invention also includes this form. The structure having a polycrystalline layer or other formed on the silicon substrate is also included in the semiconductor substrate of the present invention. The semiconductor substrate does not necessarily need to be a single crystal substrate. A polycrystalline substrate can also be used. The semiconductor substrate as the second substrate may have a densely doped impurity layer formed on the surface. Alternatively, the substrate itself may contain a high concentration of impurities. For example, when a P + substrate or a substrate with a P + layer is used as the semiconductor substrate of the second substrate, and a strained semiconductor layer is bonded to the substrate as the same P-layer, therefore a P + — / P + substrate can be manufactured. (Example of a semiconductor device) A semiconductor device using a semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate as in the above-mentioned examples, and a method of manufacturing the semiconductor device will be described below 'and please refer to Section 7A ~ Figure 7D. First, a semiconductor substrate is manufactured by using the semiconductor substrate (component) manufacturing method as in Examples 1 to 5 described above. The semiconductor substrate has a strained silicon layer on a silicon substrate, as described above. In the following description, the semiconductor substrate will be used as a strained silicon substrate. Compared with a normal silicon-33-200522161 (30) substrate, a strained silicon substrate can be used to obtain a device with a higher speed. This is because the strained silicon layer is better than a silicon layer without strain.

In the step shown in FIG. 7A, an active region 1 1 0 3 ^ is a transistor (for example, a field effect transistor, a metal-oxide semiconductor transistor, or a bipolar transistor) to be formed. , And a component insulating region 10 5 4 is formed on a pre-prepared strained sand substrate 10 2. In particular, the active region 丨 〇 03 and the element insulation region 10 5 4 can be formed by the following methods, for example: a method and region of patterning a strained silicon layer 1 105 into an island shape Oxidation barrier (LOCOS) oxidation method, or a trench method. A gate insulating film 105 is formed on the surface of the strained sand layer 105. As for the material of the gate insulating film 1 05 6, the following can be used, for example: oxide sand, nitride sand, oxynitride sand, oxide bromide, molybdenum oxide, oxide, titanium oxide, hafnium oxide, yttrium oxide, hafnium oxide , Lanthanum oxide, zirconia, or the above glass mixture. The gate insulating film 1 05 can be formed by, for example, the following method. For example, the surface of the strained silicon layer 1 1 05 is oxidized.

An insulating substance is deposited on the strained silicon layer 1105 by a chemical vapor deposition method or a physical vapor deposition method. The gate electrode 105 is formed on the gate insulating film 105. The gate electrode 1 05 5 may be made of the following materials, for example: rhenium doped with one or n-type impurities;-a metal 'for example: tungsten, molybdenum, titanium, tantalum, or copper' or at least one of the above-mentioned metals- -Metal shirts, such as: Molybdenum Shixihua, Tungsten Sand or Titanium; or-metal nitrogens such as hafnium nitride, crane nitride or nitrogen nitride. Stomach _ ^] 〇56 can be formed by forming a plurality of layers made of different materials, -34- 200522161 (31) the same polycide gate. The smell electrode 1055 can be formed by, for example, a method of self-asigned silicide (salicide), a method of damascene gate process, or any other method. By the above steps, a structure as shown in Fig. 7A can be obtained. In the step shown in FIG. 7B, an n-type impurity, such as: phosphorus, arsenic, antimony, or a p-type impurity, such as boron, is used by the active region 1 1 03 'to form a relative and This is a very lightweight doped source and drain region. This impurity can be used by ion implantation and annealing. An insulating film is formed to cover the gate electrode 105, and is etched back to form a side wall 1059 on the side of the gate electrode 105. An impurity having the same conductivity as the above-mentioned impurity is used by the active region 1 10 3 ′ to form a relatively densely doped source and drain region 1 0 5 7. By the above steps, the structure shown in Fig. 7B can be obtained. In the step shown in FIG. 7C, a metal silicide layer 1 060 is formed on the upper surface of the gate electrode] 05 5 and on the upper surface of the source and drain regions 10 5 7. As for the material of the metal silicide layer 1060, the following materials can be used, for example: nickel silicide, titanium silicide, cobalt silicide, molybdenum sand, or tungsten silicide. These silicides can be formed by depositing a metal to cover the upper surface of the gate electrode 105, the upper surface of the source and drain regions 1057, and performing an annealing process. This causes the metal to interact with the underlying silicon, and removes an unreacted portion of the metal with an etchant (eg, sulfuric acid). If required -35- 200522161 (32), the surface of the silicide layer may be nitride. By the above steps, the structure shown in Fig. 7C can be obtained. In the step shown in FIG. 7D, an insulating film 1 0 6 1 is formed to cover the upper surface of the gate electrode 1 0 5 5 converted into a silicide and the source and drain regions. 1057 of this upper surface. As for the material of the insulating film 1061, the following materials can be used, for example: silicon oxide containing scale and / or boron. If necessary, a contact hole is formed in the insulating film 1061 by a chemical mechanical honing method. When a yellow light process is used, it uses thorium fluoride excimer laser, argon fluoride excimer laser, fluorine excimer laser, electron beam or X-ray, and can be formed with one side shorter than 0.2 5 μηι A rectangular contact hole, or a circular contact hole with a diameter less than 0.25 μηι. The contact holes are filled with a conductor. As for a suitable conductor filling method, a thin film of a refractory metal or its nitride is formed on the inner surface of the contact hole as a barrier metal 1 062 (if necessary), and a conductor ] 063, for example: a tungsten alloy, aluminum, aluminum alloy, copper or copper alloy is deposited by chemical vapor deposition, physical vapor deposition or electroplating. The conductors deposited on the upper surface of the insulating film 1 06 1 are removed by back etching or chemical mechanical honing. Before the contact holes are filled with the conductor, the surface of the sand and the sand on the source and drain regions exposed to the bottom of the contact holes may be nitrided. Through the above steps, a transistor (for example, a field effect transistor) can be formed on the strained silicon layer, so that a semiconductor device having a transistor can be obtained, and the transistor has Figure D shows the structure. -36-200522161 (33) In order to form a complementary metal-oxide-semiconductor (CMOS), a p-type substrate is used as the strained silicon substrate, and an n-well is formed in the P-channel metal-oxide semiconductor (PMOS). ) Area on the substrate. 7A to 7D illustrate only a transistor region. In order to obtain a half-conductor device which can achieve the required function, a large number of transistors or other circuit elements can be formed on the strained silicon substrate, and interconnections therebetween can be formed. The present invention is used in a semiconductor substrate to form a circuit element, for example, a transistor on a strained semiconductor layer, a method for manufacturing the semiconductor substrate, and a semiconductor device for forming the circuit element. The present invention can provide a new technology, such as: forming a silicon wafer with a strained silicon layer. With the semiconductor substrate of the present invention, the channel migration rate can be increased by the strain without changing the process developed by the conventional silicon-mass integrated circuit technology. Although the present invention has been disclosed above in several preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. [Schematic description] Many aspects of the present invention can be more clearly understood with reference to the following drawings. The related drawings are not drawn to scale, and their role is only to express the relevant theorem of the present invention in a lucid way. In addition, use numbers to indicate the corresponding parts of the drawings. -37- 200522161 (34) Figure 1A illustrates a layered structure of a first substrate according to Example i of the present invention; Figure 1B illustrates a bonding step according to Example 丨 of the present invention; and Figure 1C FIG. 2 illustrates a removal step according to Example 1 of the present invention; FIG. 2A illustrates a layered structure of a first substrate according to Example 2 of the present invention; FIG. 2B illustrates a bonding step according to Example 2 of the present invention Figure 2C illustrates a separation step according to Example 2 of the present invention; and Figure 2D illustrates a removal step according to Example 2 of the present invention; Figure 3A illustrates a first step according to Example 3 of the present invention * The layered structure of the substrate; FIG. 3B illustrates a joining step according to Example 3 of the present invention; FIG. 3C illustrates a separation step according to Example 3 of the present invention; and FIG. A removal step of Example 3; FIG. 4A illustrates a growth step according to Example 4 of the present invention; FIG. 4B illustrates a plating step according to Example 4 of the present invention; and FIG. 4C illustrates a step according to Example 4 of the present invention. A layered structure of a first substrate; Figure 4D Fig. 4E illustrates a joining step according to Example 4 of the present invention; Fig. 4E illustrates a separation step according to Example 4 of the present invention; -38-200522161 (35) Fig. 4 F illustrates a removal step according to Example 4 of the present invention. Figure 5A illustrates a growth step according to Example 5 of the present invention; Figure 5B illustrates a plating step according to Example 5 of the present invention; Figure 5C illustrates a first substrate according to Example 5 of the present invention Hierarchical structure; FIG. 5D illustrates a joining step according to Example 5 of the present invention; FIG. 5E illustrates a separation step according to Example 5 of the present invention; and FIG. 5F illustrates a step according to Example 5 of the present invention. A removing step; FIG. 6A illustrates a plating step according to Example 6 of the present invention; FIG. 6B illustrates a layered structure of a first substrate according to Example 6 of the present invention; FIG. 6C illustrates according to the present invention; FIG. 6D illustrates a separation step according to Example 6 of the present invention; and FIG. 6E illustrates a removal step according to Example 6 of the present invention; FIGS. 7A to 7D illustrate a semiconductor substrate. And its manufacturing method FIG. 8 is a cross-sectional view illustrating a state in which a layer containing germanium (S i 1 · X G e x layer) is formed as the pore sealing portion of a porous surface layer. [Description of main component symbols] 10 First substrate 39- 200522161 (36) 10 'First substrate 10 ,, First substrate 10, " First ~~' substrate 10 ,,,, First substrate 11 Silicon substrate 12 Si xGex layer 13 strained silicon layer 14 porous silicon layer 141 porous silicon layer 14 of the rest, 'porous silicon layer 15 S i 1-y GC y 16 porous silicon layer 16' porous silicon layer 16 of the remaining, Part of the porous silicon layer 2 1 SiGe or germanium substrate 26 Porous layer 26! The rest of the porous layer 26, the rest of the porous layer 30 The second substrate 40 The porous layer 4 1 S i]-x G ex layer 1002 Strained silicon substrate 1054 Element insulation area 1055 Gate electrode -40- 200522161

(37) 1056 Gate insulating film 105 7 Source and drain regions 105 8 Source and drain 1059 Side wall 1060 Metal silicide layer 106 1 Insulating film 1062 Barrier metal 1063 Conductor 1 1 03f Active 1105 strain-varying silicon layer

-41-

Claims (1)

200522161 (1) X. Patent application scope 1. A semiconductor substrate comprising: an L semiconductor layer on the semiconductor substrate, wherein the bulk layer is made of the same material as the semiconductor substrate. Wherein, the semiconductor substrate described in item 1 of the application for patent | 围 G Sect. 1 The material of the semiconductor substrate and the strained semiconductor layer is silicon. 3. A method for manufacturing a semiconductor substrate, comprising: Step: forming a strained semiconductor layer made of a first material on a semiconductor substrate made of a first M 4, ff 4 ... ... to make a first substrate, and at least It can be used as a strain-sensitive material on the surface; step ~ step: bonding the strain semiconductor layer of the first substrate to a second substrate made of the first material; and step: removing the The first substrate except for a component of the strained semiconductor layer 4-side_h, and the strained semiconductor layer is left on the second substrate on. 4 The method for manufacturing a semiconductor substrate according to item 3 in the Weiweili range, wherein the ~~ material is silicon. 5 $ The method for manufacturing a semiconductor substrate as described in item 3 of the stomach and stomach benefit range ', wherein the first material is silicon and the second material is Sil_xGex, and the range of X is 0 < χ < == 1. The method for manufacturing a semiconductor substrate described in item 3 of the 6.% scope of the patent application ', wherein the semiconductor substrate is a substrate having a strain-sensitive layer formed on a surface. -42- 200522161 (2) 7. The method for manufacturing a semiconductor substrate as described in item 6 of the scope of patent application, wherein the semiconductor substrate is a substrate obtained by forming the strain sensing layer on a silicon substrate. 8. The method for manufacturing a semiconductor substrate according to item 6 of the patent application, wherein a separation layer is formed under the strain sensing layer. 9. The method for manufacturing a semiconductor substrate according to item 6 of the scope of patent application, wherein the strain sensing layer also serves as a separation layer. 1 0 · The method for manufacturing a semiconductor substrate as described in item 8 of the scope of patent application, wherein removing the component on the side of the first substrate in the third step includes a step of separating the component on the separation layer A part of the member on the side of the first substrate. 1 1 · The method for manufacturing a semiconductor substrate according to item 6 of the patent application, wherein the strain sensing layer is essentially made of silicon and an additional material. 1 2 · The method for manufacturing a semiconductor substrate according to item 11 of the scope of patent application, wherein the strain sensing layer is essentially made of SiGe. 1 3. The method for manufacturing a semiconductor substrate according to item 8 of the scope of patent application, wherein the separation layer is essentially made of a porous material. 1 4. The method for manufacturing a semiconductor substrate according to item 13 of the scope of patent application, wherein the porous material is one of porous silicon or porous SiGe. 15 · The method for manufacturing a semiconductor substrate according to item 9 of the scope of patent application, wherein the strain sensing layer, which can also be used as the separation layer, is essentially made of porous silicon. 16 · The method of manufacturing a semiconductor substrate 200522161 (3) as described in item 0 of the patent application scope, wherein in the third step, the member on the side of the first substrate except the strain sensing layer, It remains on one side of the second substrate and is removed after the separation step on the separation layer. 17. The method for manufacturing a semiconductor substrate according to item 3 of the scope of the patent application, wherein the third step includes a step of planarizing the strain-sensing layer only after the strain-sensing layer is left on the second substrate. A surface. 18 · The method for manufacturing a semiconductor substrate according to item 9 of the scope of the patent application, wherein the strain sensing layer, which can also be used as the separation layer, is a porous layer, and the strain sensing is introduced to seal at least the surface holes material. 19. A semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate as described in item 3 of the scope of patent application. 20. A semiconductor device having a transistor, wherein the transistor is formed on a strain-sensing layer of a semiconductor substrate as described in item 1 of the scope of patent application. -44-