WO2012163100A1 - 半导体芯片、存储设备 - Google Patents

半导体芯片、存储设备 Download PDF

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Publication number
WO2012163100A1
WO2012163100A1 PCT/CN2012/070966 CN2012070966W WO2012163100A1 WO 2012163100 A1 WO2012163100 A1 WO 2012163100A1 CN 2012070966 W CN2012070966 W CN 2012070966W WO 2012163100 A1 WO2012163100 A1 WO 2012163100A1
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pin
integrated circuit
circuit die
semiconductor chip
chip
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PCT/CN2012/070966
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English (en)
French (fr)
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李志雄
吴方
胡宏辉
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深圳市江波龙电子有限公司
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Priority claimed from CN201110143007.5A external-priority patent/CN102231371B/zh
Priority claimed from CN 201120178112 external-priority patent/CN202067792U/zh
Application filed by 深圳市江波龙电子有限公司 filed Critical 深圳市江波龙电子有限公司
Priority to CN201280003553.1A priority Critical patent/CN103348471B/zh
Priority to HK12105778.3A priority patent/HK1166933A2/xx
Publication of WO2012163100A1 publication Critical patent/WO2012163100A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor chip and a memory device.
  • a semiconductor chip comprising an encapsulant, a lead frame comprising a chip pin, wherein the semiconductor chip further comprises a control integrated circuit die, a memory integrated circuit die and at least one passive component;
  • the particles are electrically connected to the chip pin, the memory integrated circuit die, and the at least one passive component, respectively, the memory integrated circuit die being electrically connected to the chip pin and the at least one passive component;
  • An integrated circuit die, a memory integrated circuit die, and at least one passive component are encapsulated in the encapsulant; the chip pin is partially covered in the encapsulant and partially exposed outside the encapsulant.
  • the semiconductor chip further includes a printed circuit board encased in the encapsulant, the control integrated circuit die, the memory integrated circuit die, and the at least one passive component being fixed to the printed circuit On the board.
  • the lead frame further includes a chip socket covered in the encapsulant, and the printed circuit board is fixed on the chip holder.
  • the package structure of the semiconductor chip is in a TSOP package.
  • the number of chip pins is 48.
  • control integrated circuit die is an integrated circuit die including an SD interface control circuit, and the chip pins corresponding to the control integrated circuit die are defined according to an SD interface protocol.
  • the chip pins of the semiconductor chip include at least the following pins: a power line, a ground line, a command line, a clock line, and a data line.
  • control integrated circuit die is an integrated circuit die including an eMMC interface control circuit, and the chip pins corresponding to the control integrated circuit die are defined according to an eMMC interface protocol.
  • the chip pins of the semiconductor chip include at least the following pins: a clock line, a command line, a data line, a memory integrated circuit die power line, a control integrated circuit die power line, and a memory integrated circuit crystal. Ground wire, control integrated circuit die ground and passive component ground.
  • a memory device including the above semiconductor chip is also provided.
  • the semiconductor chip integrates the control integrated circuit die and the memory integrated circuit die.
  • the memory device including the semiconductor chip is produced when the semiconductor device is applied to the storage device, the corresponding control chip, the memory chip, and the like need not be selected.
  • Complex circuit design requires only simple circuit design and additional housing, which simplifies the production process of storage devices, saves production costs, and shortens the production cycle of storage devices.
  • FIG. 1 is a cross-sectional view showing a package structure of a semiconductor chip according to Embodiment 1;
  • FIG. 2 is a schematic view showing the outer shape and pin arrangement of the semiconductor chip provided in the first embodiment.
  • the semiconductor chip provided by the invention comprises an encapsulant, a lead frame including a chip pin, a control integrated circuit die, a memory integrated circuit die and at least one passive component, and the control integrated circuit die and the chip pin and the memory integrated circuit respectively
  • the die and the at least one passive component are electrically connected
  • the memory integrated circuit die is electrically connected to the chip pin and the at least one passive component, respectively
  • the control integrated circuit die, the memory integrated circuit die, and the at least one passive component are encapsulated in the package
  • the inside of the gel body, and the chip pin portion is covered in the encapsulant and partially exposed to the outside of the encapsulant.
  • the semiconductor chip integrates the control integrated circuit die and the memory integrated circuit die, when the application is applied to the storage device, the corresponding control chip and the memory chip do not need to be selected for complex circuit design, which simplifies the production process of the storage device. , saving production costs.
  • the semiconductor chip includes an encapsulant 10 , a lead frame 11 , and a printed circuit board 12 .
  • the lead frame 11 includes a chip pin 111 and a chip holder 112 .
  • the chip pin 111 is partially covered in the encapsulant 10 , and a part thereof Exposed to the outside of the encapsulant 10 .
  • the printed circuit board 12 is secured to the chip carrier 112 and encapsulated within the encapsulant 10.
  • the semiconductor chip further includes a control integrated circuit die 121, a memory integrated circuit die 122, and at least one passive component 123.
  • the control integrated circuit die 121, the memory integrated circuit die 122, and the at least one passive component 123 are packaged. It is covered in the encapsulant 10 and is fixed on the printed circuit board 12.
  • the control integrated circuit die 121 is electrically coupled to the chip pin 111, the memory integrated circuit die 122, and the at least one passive component 123, respectively, and the memory integrated circuit die 122 is electrically coupled to the chip pin 111 and the at least one passive component 123.
  • the package structure of the semiconductor chip adopts TSOP (Thin Small Outline). Package, thin small package) package.
  • the package structure of the semiconductor chip can also adopt SOP (Small Out-Line) Package, small package), SOJ (Small Out-Line J-lead, J-type small outline package), PLCC (Plastic leaded chip) Other package types such as Carrier, surface mount package).
  • the number of chip pins 111 is 48, which are respectively arranged on both sides of the semiconductor chip. In other embodiments, the number of chip pins 111 can also be adjusted up and down as needed, and is not intended to limit the present invention.
  • control integrated circuit die 121 is comprised of SD (Secure Digital Memory). Card Secure Digital Card) The integrated circuit die of the interface control circuit whose corresponding chip pin 111 is defined in accordance with the SD interface protocol. As shown in Table 1, the definition of each chip pin 111 of the semiconductor chip (SD memory chip) provided in this embodiment.
  • SD Secure Digital Memory
  • the chip pin 111 of the semiconductor chip may be defined in the manner of Table 1, or may be defined in other manners, but the following nine pins must be included regardless of the manner defined, namely: SDVDD (power supply line), SDVSS1 (ground line 1), SDVSS2 (ground line 2), SDCMD (command line), SDCLK (clock line), SDD0 (data line 0), SDD1 (data line 1), SDD2 (data line 2) ), SDD3 (data line 3).
  • the 26 pin can also be defined as SDCE.
  • SDCE serial information output pin
  • it can be used to output some debugging information, but this also has the same problem, that is, the capacitance near the 26 pin is easily damaged.
  • the chip pin 111 It can also be defined in the manner of Table 3. Therefore, when the semiconductor chip (SD memory chip) is produced by using the memory integrated circuit die F0, the chip pins of the F0 group are used; when the memory integrated circuit die F1 is used, the chip pins of the F1 group are used.
  • the control integrated circuit die 121 can also be an integrated circuit die including an eMMC interface control circuit, the corresponding chip pins 111 being defined in accordance with the eMMC interface protocol. As shown in Table 4, the definition of each chip pin 111 of the semiconductor chip (eMMC memory chip) provided in this embodiment.
  • the chip pin 111 of the semiconductor chip may be defined in the manner of Table 3, or may be defined in other manners, but no matter what manner is defined, the following 15 pins must be included, namely: CLK (clock line), CMD (command line), DAT0 (data line 0), DAT1 (data line 1) , DAT2 (data line 2), DAT3 (data line 3), DAT4 (data line 4), DAT5 (data line 5), DAT6 (data line 6), DAT7 (data line 7), VCC (memory integrated circuit die power line), VCCQ (control integrated circuit die power line), VSS (memory integrated circuit die ground), VSSQ (control integration Circuit die ground), VDDI (passive component ground).
  • CLK clock line
  • CMD command line
  • DAT0 data line 0
  • DAT1 data line 1
  • DAT2 data line 2
  • DAT3 data line 3
  • DAT4 data line 4
  • DAT5 data line 5
  • DAT6 data line 6
  • DAT7 data line
  • control integrated circuit die 121 can also be an integrated circuit die including other storage device interface control circuits.
  • the corresponding chip pins 111 can also be defined according to the interface protocol of each storage device, which will not be described herein.
  • the above semiconductor chip integrates the control integrated circuit die and the memory integrated circuit die.
  • the simple circuit design and the addition of the outer casing can be performed in the production process of the storage device, thereby simplifying the storage.
  • the production process of the equipment saves costs.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

一种半导体芯片，包括封装胶体（10）、包含芯片管脚（111）的导线架（11），其特征在于，所述半导体芯片还包括控制集成电路晶粒（121）、存储集成电路晶粒（122）和至少一个被动元件（123）；所述控制集成电路晶粒（121）分别与所述芯片管脚（111）、所述存储集成电路晶粒（122）和所述至少一个被动元件（123）电连接，所述存储集成电路晶粒（122）与所述至少一个被动元件（123）电连接；所述控制集成电路晶粒（121）、存储集成电路晶粒（122）和至少一个被动元件（123）包覆在所述封装胶体（10）内；所述芯片管脚（111）部分包覆在所述封装胶体（10）内，部分露于所述封装胶体（10）外。采用该半导体芯片的存储设备在生产过程时不需要做复杂的电路设计，节省了生产成本，缩短了生产周期。此外，还提供一种包含所述半导体芯片的存储设备。

Description

半导体芯片、存储设备 技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体芯片及存储设备。
 背景技术
传统的半导体芯片，在单个半导体芯片里面只封装了一个集成电路晶粒，这将给半导体芯片应用厂商带来一定的不便。以存储设备的生产为例，生产存储设备时，首先需要根据存储设备的性能选择相应的存储芯片、控制芯片等电子元器件设计电路原理图，并根据电路原理图布线、制作印刷电路板，并将控制芯片、存储芯片以及一些被动元件固定到印刷电路板上，然后再定制外壳，组装成存储设备成品。然而，这一过程非常复杂，生产周期长，且存储设备生产厂商还需配备相应的电路设计人员，增加了生产成本。
 技术问题
基于此，有必要提供一种高度集成的半导体芯片，能够简化存储设备的生产过程，节约生产成本。
 技术解决方案
一种半导体芯片，包括封装胶体、包含芯片管脚的导线架，其特征在于，所述半导体芯片还包括控制集成电路晶粒、存储集成电路晶粒和至少一个被动元件；所述控制集成电路晶粒分别与所述芯片管脚、所述存储集成电路晶粒和所述至少一个被动元件电连接，所述存储集成电路晶粒与所述芯片管脚和至少一个被动元件电连接；所述控制集成电路晶粒、存储集成电路晶粒和至少一个被动元件包覆在所述封装胶体内；所述芯片管脚部分包覆在所述封装胶体内，部分露于所述封装胶体外。
在优选的实施例中，所述半导体芯片还包括包覆在所述封装胶体内的印刷电路板，所述控制集成电路晶粒、存储集成电路晶粒和至少一个被动元件固定在所述印刷电路板上。
在优选的实施例中，所述导线架还包括包覆于所述封装胶体内的芯片承座，所述印刷电路板固定在所述芯片承座上。
在优选的实施例中，所述半导体芯片的封装结构采用TSOP封装。
在优选的实施例中，所述芯片管脚的数目为48。
在优选的实施例中，所述控制集成电路晶粒为包含SD接口控制电路的集成电路晶粒，所述控制集成电路晶粒对应的芯片管脚根据SD接口协议定义。
在优选的实施例中，所述半导体芯片的芯片管脚至少包括以下管脚：电源线、地线、命令线、时钟线和数据线。
在优选的实施例中，所述控制集成电路晶粒为包含eMMC接口控制电路的集成电路晶粒，所述控制集成电路晶粒对应的芯片管脚根据eMMC接口协议定义。
在优选的实施例中，所述半导体芯片的芯片管脚至少包括以下管脚：时钟线、命令线、数据线、存储集成电路晶粒电源线、控制集成电路晶粒电源线、存储集成电路晶粒地线、控制集成电路晶粒地线和被动元件地线。
此外，还提供了一种包括上述半导体芯片的存储设备。
 有益效果
上述半导体芯片集成了控制集成电路晶粒和存储集成电路晶粒，在应用在存储设备上时，生产包含该半导体芯片的存储设备时，不需要再去选择相应的控制芯片、存储芯片等来进行复杂的电路设计，只需做简单的电路设计以及增加外壳即可，因此能有效简化存储设备的生产过程，节省了生产成本，缩短了存储设备的生产周期。
 附图说明
图1为实施例一提供的半导体芯片的封装结构的剖面示意图；
图2为实施例一提供的半导体芯片的外部形状及管脚排列的示意图。
 本发明的实施方式
本发明提供的半导体芯片，包括封装胶体、包含芯片管脚的导线架、控制集成电路晶粒、存储集成电路晶粒和至少一个被动元件，控制集成电路晶粒分别与芯片管脚、存储集成电路晶粒和至少一个被动元件电连接，存储集成电路晶粒分别与所述芯片管脚和至少一个被动元件电连接，控制集成电路晶粒、存储集成电路晶粒和至少一个被动元件包覆在封装胶体内，而芯片管脚部分包覆在封装胶体内，部分露于封装胶体外。由于该半导体芯片集成了控制集成电路晶粒和存储集成电路晶粒，在应用在存储设备上时，不需要选择相应的控制芯片、存储芯片来进行复杂的电路设计，简化了存储设备的生产过程，节省了生产成本。
实施例一
如图1所示，半导体芯片包括封装胶体10、导线架11、印刷电路板12，导线架11包括芯片管脚111和芯片承座112，芯片管脚111部分包覆在封装胶体10内，部分露于封装胶体10外。印刷电路板12固定在芯片承座112上，并包覆在封装胶体10内。
该实施例中，半导体芯片还包括控制集成电路晶粒121、存储集成电路晶粒122和至少一个被动元件123，控制集成电路晶粒121、存储集成电路晶粒122和至少一个被动元件123都包覆在封装胶体10内，并都固定在印刷电路板12上。控制集成电路晶粒121分别与芯片管脚111、存储集成电路晶粒122和至少一个被动元件123电连接，存储集成电路晶粒122与芯片管脚111和至少一个被动元件123电连接。
该实施例中，半导体芯片的封装结构采用TSOP（Thin Small Outline Package，薄型小尺寸封装）封装。在其他实施例中，半导体芯片的封装结构也可以采用SOP（ Small Out-Line Package，小尺寸封装）、SOJ（Small Out-Line J-lead，J型引脚小外形封装）、PLCC（Plastic leaded Chip Carrier，表面贴装型封装）等其他封装形式。如图2所示，芯片管脚111的数目为48，分别排列在半导体芯片的两侧。在其他实施例中，芯片管脚111的数目也可以根据需要上下调整，在此并不用以限制本发明。
该实施例中，控制集成电路晶粒121为包含SD（Secure Digital Memory Card安全数码卡）接口控制电路的集成电路晶粒，其相应的芯片管脚111根据SD接口协议进行定义。如表1所示，为该实施例提供的半导体芯片（SD存储芯片）的各芯片管脚111的定义。
表1
管脚序号 管脚定义 管脚序号 管脚定义
1 NC 25 NC
2 NC 26 SDVSS2
3 NC 27 SDD3
4 NC 28 SDV33
5 NC 29 NC
6 NC 30 NC
7 NC 31 NC
8 NC 32 NC
9 NC 33 SDCMD
10 NC 34 NC
11 NC 35 NC
12 NC 36 SDVSS1
13 NC 37 NC
14 NC 38 NC
15 NC 39 NC
16 NC 40 SDCLK
17 NC 41 NC
18 NC 42 NC
19 NC 43 NC
20 NC 44 NC
21 NC 45 SDD2
22 NC 46 SDD1
23 NC 47 SDD0
24 NC 48 NC
所述半导体芯片（SD存储芯片）的所述芯片管脚111可以按表1的方式定义，也可以采用其他方式定义，但不论采用什么方式定义，都必须包含以下9个管脚，即：SDVDD（电源线）、SDVSS1（地线1）、SDVSS2（地线2）、SDCMD（命令线）、SDCLK（时钟线）、SDD0（数据线0）、SDD1（数据线1）、SDD2（数据线2）、SDD3（数据线3）。
进一步的，在采用表1的芯片管脚定义对本发明实施例提供的半导体芯片进行封装时，我们发现26管脚（一般在26管脚附近设注塑口，注入封装胶体对半导体芯片进行封装）附近位于印刷电路板12上的电容容易与空气接触从而损坏电容，因此我们采用以下新的定义，如表2所示：
表2
管脚序号 管脚定义 管脚序号 管脚定义
1 NC 25 NC
2 NC 26 SDIP
3 NC 27 SDD3
4 NC 28 SDV33
5 NC 29 NC
6 NC 30 NC
7 NC 31 NC
8 NC 32 NC
9 NC 33 SDCMD
10 NC 34 NC
11 NC 35 NC
12 NC 36 SDVSS1
13 NC 37 NC
14 NC 38 NC
15 NC 39 NC
16 NC 40 SDCLK
17 NC 41 NC
18 NC 42 NC
19 NC 43 NC
20 NC 44 NC
21 NC 45 SDD2
22 NC 46 SDD1
23 NC 47 SDD0
24 NC 48 NC
上表中，将26管脚的定义更改为SDIP（SD Internal Power），该管脚用于将内部电源引出，并外接电容到地，以提高系统的稳定性。
当然，也可以将26管脚定义为SDCE，作为串口信息输出管脚，可以用于输出一些调试信息，不过这也存在同样问题，即26管脚附近处的电容容易损坏。
为了使所述半导体芯片（SD存储芯片）能够适应不同种类的存储集成电路晶粒，比如说，市场上存在三种不同种类的存储集成电路晶粒F0、F1、F2，所述芯片管脚111还可以采用表3的方式定义。因此当所述半导体芯片（SD存储芯片）采用存储集成电路晶粒F0生产，则使用F0组的芯片管脚；采用存储集成电路晶粒F1生产，则使用F1组的芯片管脚。
表3
管脚序号 管脚定义 管脚序号 管脚定义
1 NC 25 F2-SDVSS
2 F0-SDD3 26 F2-SDD2
3 NC 27 F2-SDVDD
4 F0-SDCMD 28 F2-SDD1
5 NC 29 F2-SDD0
6 F0-VSS1 30 F2-SDCLK
7 NC 31 F2-SDVDD
8 F0-SDVDD 32 F2-SDVDD
9 NC 33 F2-SDVSS1
10 F0-SDCLK 34 F2-SDCMD
11 NC 35 F2-SDD3
12 NC 36 F1/F2-SDVSS2
13 F0-VSS2 37 F1-SDD2
14 NC 38 F1-SDD1
15 F0-SDVDD 39 F1-SDVSS1
16 NC 40 F1-SDD0
17 F0-SDVSS1 41 F1-SDCLK
18 NC 42 F1-SDVSS1
19 F0-SDD0 43 F1-SDVSS1
20 F0-SDVDD 44 F1-SDCMD
21 F0-SDD1 45 F1-SDD3
22 NC 46 NC
23 F0-SDD2 47 F1-SDVSS1
24 F0-SDVSS1 48 F1-SDVDD
实施例二
控制集成电路晶粒121也可以为包含eMMC接口控制电路的集成电路晶粒，其相应的芯片管脚111根据eMMC接口协议进行定义。如表4所示，为该实施例提供的半导体芯片（eMMC存储芯片）的各芯片管脚111的定义。
表4
管脚序号 管脚定义 管脚序号 管脚定义
1 NC 25 VCC
2 NC 26 NC
3 NC 27 NC
4 NC 28 NC
5 NC 29 DAT0
6 NC 30 DAT1
7 CMD 31 DAT2
8 VDDI 32 DAT3
9 CLK 33 NC
10 NC 34 NC
11 NC 35 NC
12 VCCQ 36 VSSQ
13 VSSQ 37 VCCQ
14 NC 38 NC
15 NC 39 NC
16 NC 40 NC
17 VSS 41 DAT4
18 NC 42 DAT5
19 VSSQ 43 DAT6
20 NC 44 DAT7
21 NC 45 NC
22 NC 46 NC
23 NC 47 NC
24 NC 48 VCC
所述半导体芯片（eMMC存储芯片）的所述芯片管脚111可以按表3的方式定义，也可以采用其他方式定义，但不论采用什么方式定义，都必须包含以下15个管脚，即：CLK（时钟线）、CMD（命令线）、DAT0（数据线0）、DAT1（数据线1） 、DAT2（数据线2） 、DAT3（数据线3） 、DAT4（数据线4）、 DAT5 （数据线5）、DAT6 （数据线6）、DAT7（数据线7）、VCC（存储集成电路晶粒电源线）、VCCQ（控制集成电路晶粒电源线）、VSS（存储集成电路晶粒地线）、VSSQ（控制集成电路晶粒地线）、VDDI（被动元件地线）。
当然，控制集成电路晶粒121还可以是包含其他存储设备接口控制电路的集成电路晶粒，相应的芯片管脚111也可根据各存储设备的接口协议进行定义，在此不一一赘述。
上述半导体芯片集成了控制集成电路晶粒和存储集成电路晶粒，该半导体芯片应用在存储设备上时，在存储设备的生产过程中只需做简单的电路设计以及增加外壳即可，简化了存储设备的生产过程，节省了成本。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (14)

  1. 一种半导体芯片，包括封装胶体、包含芯片管脚的导线架，其特征在于，所述半导体芯片还包括控制集成电路晶粒、存储集成电路晶粒和至少一个被动元件；
    所述控制集成电路晶粒分别与所述芯片管脚、所述存储集成电路晶粒和所述至少一个被动元件电连接，所述存储集成电路晶粒与所述芯片管脚和至少一个被动元件电连接；
    所述控制集成电路晶粒、存储集成电路晶粒和至少一个被动元件包覆在所述封装胶体内；
    所述芯片管脚部分包覆在所述封装胶体内，部分露于所述封装胶体外。
  2. 根据权利要求1所述的半导体芯片，其特征在于，所述半导体芯片还包括包覆在所述封装胶体内的印刷电路板，所述控制集成电路晶粒、存储集成电路晶粒和至少一个被动元件固定在所述印刷电路板上。
  3. 根据权利要求2所述的半导体芯片，其特征在于，所述导线架还包括包覆于所述封装胶体内的芯片承座，所述印刷电路板固定在所述芯片承座上。
  4. 根据权利要求1至3中任意一项所述的半导体芯片，其特征在于，所述半导体芯片的封装结构采用TSOP封装。
  5. 根据权利要求4所述的半导体芯片，其特征在于，所述芯片管脚的数目为48。
  6. 根据权利要求5所述的半导体芯片，其特征在于，所述控制集成电路晶粒为包含SD接口控制电路的集成电路晶粒，所述控制集成电路晶粒对应的芯片管脚根据SD接口协议定义。
  7. 根据权利要求6所述的半导体芯片，其特征在于，所述半导体芯片的芯片管脚至少包括以下管脚：电源线、地线、命令线、时钟线和数据线。
  8. 根据权利要求7所述的半导体芯片，其特征在于，第26管脚为地线2管脚，第27管脚为数据线3管脚、第28管脚为电源线管脚，第33管脚为命令线管脚，第36管脚为地线1管脚，第40管脚为时钟线管脚，第45管脚为数据线2管脚，第46管脚为数据线1管脚，第47管脚为数据线0管脚，其它管脚空接。
  9. 根据权利要求8所述的半导体芯片，其特征在于，第26管脚通过外接电容后接地。
  10. 根据权利要求7所述的半导体芯片，其特征在于，所述半导体芯片包含不同种类的存储集成电路晶粒，且所述半导体芯片为每种存储集成电路晶粒对应地设置一组芯片管脚。
  11. 根据权利要求5所述的半导体芯片，其特征在于，所述控制集成电路晶粒为包含eMMC接口控制电路的集成电路晶粒，所述控制集成电路晶粒对应的芯片管脚根据eMMC接口协议定义。
  12. 根据权利要求11所述的半导体芯片，其特征在于，所述半导体芯片的芯片管脚至少包括以下管脚：时钟线、命令线、数据线、存储集成电路晶粒电源线、控制集成电路晶粒电源线、存储集成电路晶粒地线、控制集成电路晶粒地线和被动元件地线。
  13. 根据权利要求12所述的半导体芯片，其特征在于，第7管脚为命令线管脚，第8管脚为被动元件地线管脚，第9管脚为时钟线管脚，第12、37管脚为控制集成电路晶粒电源线管脚，第13、19、36管脚为控制集成电路晶粒地线管脚，第17管脚为存储集成电路晶粒地线管脚，第25、48管脚为存储集成电路晶粒电源线管脚，第29至32、41至44管脚为数据线0至7管脚，其它管脚空接。
  14. 一种存储设备，其特征在于，包括如权利要求1至13中任意一项所述的半导体芯片。
PCT/CN2012/070966 2011-05-30 2012-02-08 半导体芯片、存储设备 WO2012163100A1 (zh)

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