TWM310443U - Structure of semiconductor package having opening windows - Google Patents

Structure of semiconductor package having opening windows Download PDF

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Publication number
TWM310443U
TWM310443U TW095218331U TW95218331U TWM310443U TW M310443 U TWM310443 U TW M310443U TW 095218331 U TW095218331 U TW 095218331U TW 95218331 U TW95218331 U TW 95218331U TW M310443 U TWM310443 U TW M310443U
Authority
TW
Taiwan
Prior art keywords
memory card
open
electronic memory
semiconductor package
type semiconductor
Prior art date
Application number
TW095218331U
Other languages
Chinese (zh)
Inventor
En-Min Jow
Original Assignee
En-Min Jow
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by En-Min Jow filed Critical En-Min Jow
Priority to TW095218331U priority Critical patent/TWM310443U/en
Priority to US11/592,214 priority patent/US20080067641A1/en
Priority to JP2007000071U priority patent/JP3130639U/en
Publication of TWM310443U publication Critical patent/TWM310443U/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Description

M310443 八、新型說明： 【新型所屬之技術領域】 本創作係有關一種半導體封裝結構，特別是一種具有開孔之 半導體封裝結構。 【先前技術】 一般產業界半導體封裝的方式如薄型小尺寸封裝(TSOP)型式、微 蜇小尺寸封裝(MSOP)及1/4小尺寸封裝(QS0P)等封裝技術常應用於消 費性電子產品内之記憶裝置或製成記憶卡等，如第i圖所示為習 知具記憶功能的封裝體之結構剖視圖，導線架1〇〇依序裝設控制 元件（controller component)200 ' 快閃記憶晶片（flash mem〇ry)3〇〇 及被動元件400元件，再利用封膠體5〇〇密封形成單一之封裝體， 封裝體最後經由電性測試，分類良品及不良品。 上述之封裝體因密封成一體成型之結構，封膠體將控制元件 2〇〇、快閃記憶晶片300及被動元件400包覆在一起，再進行電性 剎忒，方面，封裝過程中無法瞭解先行得知各IC元件或製程所 造成電性不良的原因’而只能於封裝完後進行電性測試，若電性 t 則各IC疋件及其封裝材料必須要報廢造成生產成本及 :二“：不L:方面’在檢驗電性不良的封裝體時，因封膠後 ' 易松視得知封裝體内部電性不良之原因，進而 艮率無法提高，目此如何克服上述問題是目前業界所急迫需要的。。 【新型内容】 為了角午決上诚卩q日^丄 成開孔用於置人被動 '創作目的之―’係糊封膠體於封膠時形 測試後再妓是否置人、_且於未置人被動元件時，封裝體前可先行電性 置入破動元件，避免電性不良切裝體置人被動元件。 5M310443 VIII. New Description: [New Technology Field] This creation is about a semiconductor package structure, especially a semiconductor package structure with openings. [Prior Art] General industrial semiconductor packaging methods such as thin small package (TSOP) type, micro small package (MSOP) and 1/4 small package (QS0P) are commonly used in consumer electronics. The memory device or the memory card, etc., as shown in the figure i is a structural cross-sectional view of the conventional memory function package, the lead frame 1 is sequentially equipped with a controller component 200 'flash memory chip (flash mem〇ry) 3 〇〇 and passive components 400 components, and then sealed with a sealant 5 形成 to form a single package, the package finally through electrical testing, classification of good and defective products. The above-mentioned package is sealed into an integrally formed structure, and the sealant encapsulates the control element 2, the flash memory chip 300 and the passive component 400 together, and then performs electrical braking, and the packaging process cannot be understood first. Knowing the cause of electrical defects caused by various IC components or processes' can only be electrically tested after packaging. If the electrical property is t, the IC components and their packaging materials must be scrapped to cause production costs and: : No L: Aspect 'When testing a poorly-performing package, it is easy to understand the cause of poor electrical conductivity inside the package after sealing, so how to overcome the above problem is the current industry. Urgently needed. [New content] For the corner of the afternoon, the sincerity of the day q 丄 开 开 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 用于 被动 被动 被动 被动 被动 被动 系 系 系When the passive component is not placed, the capacitor can be placed into the broken component before the package to prevent the passive component from being placed into the passive component.

Claims (1)

M310443 九、申請專利範圍： 月· 1 一種開孔財導體封裝結構，包含： —— 至少其係由複數個㈣腳、複數個外引腳及至少—承載座所組成； 阳片，其係設置於該導線架之該承載座； 一控制元件，其係設置_導_之該承載座； ^膠體，其係包覆於該導線架' 該晶片、該内引腳及該控制元件； $ I開孔’设置於該封膠體任一位置並曝露出部分該導線架表面；及 接該導^被動A件’設置於該開孔内之鱗_表面且該被動元件電性連 ^曰曰^求項1所述之開孔型半導體封裝結構，其中該晶片係為快閃記 導體封1結構’其中該封膠體係由環氧樹 3·如請求項1所述之開孔型半 脂所構成。 屬材 5. 抖！項1所述之開孔型半導體封裝結構，其中該些外引腳露出該 "體外。M310443 IX. Patent application scope: Month · 1 An open-hole financial conductor package structure, comprising: —— at least consisting of a plurality of (four) feet, a plurality of outer pins and at least a carrier; a positive film, the system is set a carrier for the lead frame; a control element for the carrier; a colloid covering the lead frame 'the wafer, the inner lead and the control element; $ I The opening ' is disposed at any position of the sealing body and exposes a part of the surface of the lead frame; and the conductive member A is disposed on the scale surface of the opening and the passive component is electrically connected The open-cell type semiconductor package structure according to Item 1, wherein the wafer is a structure of a flash-sound conductor package 1 wherein the sealant system is composed of an epoxy tree 3 and an open-cell type semi-fat as described in claim 1. . Attributes 5. Shake! The open-cell type semiconductor package structure of item 1, wherein the outer leads are exposed to the outside of the body. •如明求項丨所述之·型半導體封裝結構，其中該承載座設置複 個丨線分別電性連接該些内引腳、該晶片及該控制元件。 7·如明求項1所述之開孔型半導體封裝結構，其中該開孔型半導體 封裝結構結構適詩_電子產品之—儲存媒介，該電子產品之該储 存媒^包含數位相機(DC)、個人數位助理(pDA)及行動電話。 8·如1求項1所述之開孔型半導體封裝結構，該開孔型半導體封裝 、、、口 1適用;^ f;子δ己憶卡’ t亥電子記憶卡包含安全數位(sd)電子記憶 卡、多媒體(MMC)電子記憶卡、壓縮快閃(CF)電子記憶卡 、記憶體條(MS)電 子德卡、智慧媒體(SM)電子記憶卡、尖端數位㈣)電子記憶卡、迷你多 媒體(RS MMC)!： 卡、迷你安全數位(mini_sD)電子記憶卡及迷你快閃 (Trans Flash)電子記憶卡。 M310443 9.-種開孔型半導體封裝結構，包含: \ ^ - ·τ„] 一基板； f Λ I丨 . .... . ΤΤ-_-- ·ί ' .:--,,5 ^ “.： ' -："： ：Γ^_— · ; ., Γ.. .. J 晶片’其係設置於該基板； 至少一控制元件，其係設置於該基板； 封膠體，其係包覆於該絲、該晶片及該控制元件； ^二孔’妓於該封雜任-位置麵露出部分該基板表面；及 該基^動^件，設置於關孔内之該基板表面·被動元件電性連接 求項9所述之開孔型半導體封裝結構，其中該晶片係為快閃記 9觸德科㈣咖構當娜體係由環氧 個項9所述之開孔型半導體封裝結構，其中該基板設置複數 個引線刀別電性連接該晶片及該控制元件。 貝9所述之開孔型半導體封裝結構’其中該開孔型半導體 入適用於-電子產品之—儲存媒介，該電子產品之該儲存媒 w包^數位相機(DC)、個人數位助理(pDA)及行動電話。 H·如明求項9所述之開孔型半導體封裝結構，該開孔型半導體封褒 、、σ構適用於-電子d憶卡，該電子記憶卡包含安全數位㈣電子記憶 卡、多媒體_〇)電子記憶卡、壓縮快閃(CF)電子記憶卡、記憶體條(MS)電 子δ己憶卡、智慧媒體(SM)電子記憶卡、央端數位(奶)電子記憶卡、迷你多 媒體(RS_譲C)電子記憶卡、迷你安全數位㈣⑸删電子記憶卡及迷你快閃 (Trans Flash)電子記憶卡。The semiconductor package structure of the type described in the specification, wherein the carrier is provided with a plurality of turns, respectively electrically connecting the inner leads, the wafer and the control element. The open-cell type semiconductor package structure according to claim 1, wherein the open-cell type semiconductor package structure is suitable for a storage medium, and the storage medium of the electronic product comprises a digital camera (DC) , personal digital assistant (pDA) and mobile phone. 8. The open-hole type semiconductor package structure according to claim 1, wherein the open-hole type semiconductor package, and the port 1 are applied; wherein the sub-δ recall card 'thai electronic memory card includes a security digit (sd) Electronic memory card, multimedia (MMC) electronic memory card, compressed flash (CF) electronic memory card, memory stick (MS) electronic card, smart media (SM) electronic memory card, sophisticated digital (four)) electronic memory card, mini Multimedia (RS MMC)!: Card, mini secure digital (mini_sD) electronic memory card and mini flash (Trans Flash) electronic memory card. M310443 9.-Open-cell type semiconductor package structure, including: \ ^ - · τ„] a substrate; f Λ I丨. .... . ΤΤ-_-- · ί ' .:--,,5 ^ ".: ' -:": :Γ^_— · ; . . . . . . . J. The wafer 'is disposed on the substrate; at least one control element is disposed on the substrate; the sealant, the system Covering the wire, the wafer and the control element; the second hole 'exposed on the surface of the substrate where the sealing-position surface is exposed; and the substrate, the surface of the substrate disposed in the closing hole The passive component is electrically connected to the open-cell type semiconductor package structure according to Item 9, wherein the chip is an open-cell type semiconductor package structure according to the epoxy item 9 in the flash memory. Wherein the substrate is provided with a plurality of lead knives to electrically connect the wafer and the control element. The open-cell type semiconductor package structure described in the above, wherein the open-cell type semiconductor is suitable for a storage medium for an electronic product, and the storage medium of the electronic product includes a digital camera (DC) and a personal digital assistant (pDA). ) and mobile phone. The open-cell type semiconductor package structure according to claim 9, wherein the open-cell type semiconductor package and the sigma structure are applied to an electronic memory card, and the electronic memory card comprises a secure digital (four) electronic memory card and a multimedia _ 〇) Electronic memory card, compressed flash (CF) electronic memory card, memory stick (MS) electronic δ recall card, smart media (SM) electronic memory card, central digital (milk) electronic memory card, mini multimedia ( RS_譲C) Electronic memory card, mini security digital (4) (5) Delete electronic memory card and Mini Flash (Trans Flash) electronic memory card.
TW095218331U 2006-09-15 2006-10-17 Structure of semiconductor package having opening windows TWM310443U (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW095218331U TWM310443U (en) 2006-10-17 2006-10-17 Structure of semiconductor package having opening windows
US11/592,214 US20080067641A1 (en) 2006-09-15 2006-11-03 Package semiconductor and fabrication method thereof
JP2007000071U JP3130639U (en) 2006-10-17 2007-01-10 Semiconductor package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095218331U TWM310443U (en) 2006-10-17 2006-10-17 Structure of semiconductor package having opening windows

Publications (1)

Publication Number Publication Date
TWM310443U true TWM310443U (en) 2007-04-21

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI460829B (en) * 2011-05-30 2014-11-11 Shenzhen Netcom Elect Co Ltd Semiconductor wafers and their storage devices

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015103790A (en) * 2013-11-28 2015-06-04 株式会社東海理化電機製作所 Lead frame structure and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI460829B (en) * 2011-05-30 2014-11-11 Shenzhen Netcom Elect Co Ltd Semiconductor wafers and their storage devices

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