WO2012162867A1 - 一种采用电场增强层的阻变存储器结构及其制备方法 - Google Patents

一种采用电场增强层的阻变存储器结构及其制备方法 Download PDF

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Publication number
WO2012162867A1
WO2012162867A1 PCT/CN2011/002090 CN2011002090W WO2012162867A1 WO 2012162867 A1 WO2012162867 A1 WO 2012162867A1 CN 2011002090 W CN2011002090 W CN 2011002090W WO 2012162867 A1 WO2012162867 A1 WO 2012162867A1
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layer
electric field
resistive memory
resistance
field enhancement
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PCT/CN2011/002090
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English (en)
French (fr)
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张卫
陈琳
周鹏
孙清清
王鹏飞
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复旦大学
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Priority to US13/457,035 priority Critical patent/US9099178B2/en
Publication of WO2012162867A1 publication Critical patent/WO2012162867A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/023—Formation of switching materials, e.g. deposition of layers by chemical vapor deposition, e.g. MOCVD, ALD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/55—Structure including two electrodes, a memory active layer and at least two other layers which can be a passive or source or reservoir layer or a less doped memory active layer

Definitions

  • the present invention relates to the field of non-volatile memory technology, and in particular to a resistive memory structure and a method of fabricating the same, and more particularly to a resistive memory structure using an electric field enhancement layer and a method of fabricating the same. Background technique
  • Flash memory Volatile Memory
  • FRAM ferroelectric memory
  • MRAM magnetic memory
  • PRAM phase change memory
  • RRAM resistive memory
  • a typical resistive material has two states of high resistance and low resistance.
  • the resistive memory relies on the change of the high resistance and low resistance of the material itself to store information.
  • 1 is a cross-sectional view of a typical resistive memory cell in which a resistive transition memory layer 102 is located between a top electrode 101 and a bottom electrode 103.
  • the top electrode 101 and the bottom electrode 103 generally use a metal material having a relatively stable chemical property such as Pt and Ti, and the resistance change memory layer 102 is usually a binary or ternary metal oxide such as Ti0 2 , ZrO > Cu 2 0 and SrTiO 3 .
  • the resistance value of the resistance change storage layer 102 can have two states of high resistance and low resistance under the action of an applied voltage, which can be used to characterize "0" and " ⁇ " respectively. In different applied voltage conditions.
  • the resistance value of the resistive memory can be reversibly converted between the high resistance state and the low resistance state, thereby realizing the storage of information.
  • resistive memory is greatly improved because of its advantages such as simple preparation, high memory density, low operating voltage, fast read/write speed, long retention time, non-destructive reading, low power consumption, and good compatibility with traditional CMOS processes.
  • the emphasis is considered to be one of the strong candidates for the next generation of "universal" memory.
  • the stability of the performance including the stability of the write, erase voltage stability, high and low resistance signal ratio is a key issue in the practical application of resistive memory.
  • the main problem of resistive memory is usually Unstable erase voltage and erase current.
  • the preparation of high-stability resistive memories with optimized performance is a key issue for industrial applications of resistive memory devices. Disclosure of invention
  • the object of the present invention is to provide a high stability resistive memory with optimized performance and a manufacturing method thereof for solving the problems in the industrial application of a resistive memory device.
  • the present invention proposes a resistive memory, which is formed by using a resistive functional material of different dielectric constants as a resistive transition memory layer, the structure comprising a top electrode, a bottom electrode and a top electrode and a Between the bottom electrodes
  • a stack consisting of a first resistive transition layer and a second resistive transition layer and an electric field enhancement layer; the second resistive transition layer and the electric field enhancement layer are adjacent to the first resistive transition layer, and have a ratio
  • the low dielectric constant of the first resistive transition layer is described.
  • the second layer of the resistance change layer and the electric field enhancement layer may be made of a lower dielectric constant material, such as
  • the first layer of the resistance change layer may be a higher dielectric constant material such as Hf0 2 , 21"0 2 or 1 ⁇ 2 0 5 , or a mixed dielectric material thereof.
  • the present invention also provides a method for manufacturing the resistive memory, specifically comprising: forming a bottom electrode of the resistive memory on the substrate;
  • a top electrode of the resistive memory is formed on the resistance change and electric field enhancement layer.
  • the bottom electrode is a metal material such as Pt/Ti, Au/Ti, TiN, Ru or Cu.
  • the first layer of the resistance change layer is formed of a high dielectric constant material such as Hf0 2 , Zr0 2 , Nb 2 0 5 or a mixed dielectric material thereof.
  • the second layer of resistance change and electric field enhancement layer is formed of a low dielectric constant material such as SiO 2 or Al 2 2 3 .
  • the top electrode is a metal material such as Al, Pt, Ru, TiN or TaN.
  • Conventional resistive memories typically include an upper electrode, a resistive layer, and a lower electrode.
  • a resistive transition and electric field enhancement layer is further added to the upper and lower electrodes to enhance the electric field in the resistive layer.
  • the dielectric layers of the dielectric layers having different dielectric constants have different partial pressures, which causes the electric field to be in the respective dielectric layers. : ⁇ Sex.
  • the electric field distribution in the structure of the stacked memory device is formed by using a resistive functional material with different dielectric constants to realize the structure and quantity control of the conductive channel formed by the resistive memory during the resistive process.
  • the dielectric constant of the second layer resistance change and electric field enhancement layer is lower than the dielectric constant of the first layer resistance change layer, the electric field in the second layer resistance change layer (resistive layer) can be enhanced. Therefore, the electric field in the second resistive layer can be adjusted by the dielectric constant and thickness between the different layers.
  • the invention combines the traditional film preparation method to realize the preparation of the resistive memory device structure with adjustable electric field distribution, thereby completely solving the disadvantages of unstable performance of the resistive memory on the practical road in experiments and theory.
  • the barrel of the drawing is to be explained
  • FIG. 1 is a cross-sectional view showing a conventional resistive memory structure.
  • FIG. 2 is a cross-sectional view showing a structure of a performance controllable resistive memory device according to the present invention.
  • FIG. 3 to FIG. 7 are flowcharts showing a process of preparing a resistive memory device as shown in FIG. 2 in the MOSFET back-end interconnection process as an embodiment.
  • the resistive memory includes a top electrode 201, a bottom electrode 203, and a top electrode 201 and a bottom electrode 203.
  • the composite dielectric layer 202 includes a first resistive transition layer (typically a high dielectric constant (high k) material) 202b and a second resistive transition layer and an electric field enhancement layer (usually a low dielectric Electrical constant (low k) material) 202a.
  • the so-called high dielectric constant and low dielectric constant are relative to silicon dioxide.
  • the dielectric constant is higher than that of silicon dioxide as a high dielectric constant material, and the dielectric constant is lower than that of silicon dioxide.
  • silica is classified as a low dielectric constant material.
  • the resistive memory provided by the present invention can be integrated into semiconductor devices of different structures.
  • the following describes a manufacturing process flow in which an integrated resistive memory is integrated in a conventional MOSFET back-channel interconnect process.
  • a silicon substrate 300 is provided, and then a standard CMOS process is used to complete the fabrication of the front CMOS device.
  • the specific processes include: 1. Using a diffusion process or an ion implantation process on the silicon substrate 300. A source region 301 and a drain region 302 are formed therein. 2. Forming a gate oxide layer 303, a gate electrode 304, and an insulating layer 305 of the device on the substrate 300 by using an oxidation process, a thin film deposition process, and a photolithography process and an etching process, the insulating layer 305 and the gate region and the device. The conductor layer is isolated.
  • a SiOC low-k dielectric material is deposited by a chemical vapor deposition (CVD) method to form an interlayer isolation layer 306, and then photolithography and etching are used to define interconnection via locations, and a layer of TiN is sputtered by reactive ions.
  • CVD chemical vapor deposition
  • a Ru layer is then grown on the TiN by an atomic layer deposition (ALD) technique to form a Ru/TiN structure 307.
  • a copper wire 308 is then formed by electroplating and the wafer surface is planarized by chemical mechanical polishing (CMP) techniques, as shown in FIG.
  • CMP chemical mechanical polishing
  • a silicon nitride etch stop layer 309 is deposited, and the SiOC interlayer isolation layer 310 is deposited again, and then the second layer interconnection position is defined by photolithography and etching, and then deposited to form Ru/TiN diffusion.
  • Barrier layer 311, and electroplated copper interconnect 312, is then polished using CMP techniques, as shown in FIG.
  • the sample was placed in an atomic layer deposition apparatus, and the wafer was heated to about 300 ° C before the first pulse in the pulse period. This temperature is maintained throughout the ALD growth.
  • the reaction chamber was brought to a pressure of about 1 Torr prior to the first pulse in the pulse cycle and this pressure was maintained throughout the process.
  • a gas volatilized from the ruthenium organic reaction precursor (tetraethylmethylamino) ruthenium (TEMAH) heated to 70 ° C was introduced into the reaction chamber in a pulsed manner as a carrier gas stream with a pulse time of 2 seconds.
  • An inert gas is introduced into the reaction chamber in a pulsed manner to remove unreacted metal organic precursors and by-products from the reaction chamber.
  • the inactive purge gas includes nitrogen, argon and helium with a pulse time of 3 seconds.
  • Water vapor pulses are typically introduced into the reaction chamber during pulse times ranging from about 1 to about 2 seconds. Unreacted water vapor and by-products were removed from the reaction chamber for a pulse time of 3 seconds. This step was cycled 100 times to obtain a 10 nm thick Hf ⁇ 2 high k material resistance transition layer 313.
  • a gas volatilized from the liquid precursor trimethylamine (TMA) was introduced into the reaction chamber in pulses, with a pulse time of 1 second.
  • An inert gas is introduced into the reaction chamber in a pulsed manner to remove unreacted metal organic precursors and by-products from the reaction chamber.
  • the inactive purge gas including nitrogen, argon and helium, was pulsed for 3 seconds.
  • Water vapor was introduced into the reaction chamber with a pulse time of 1 second. Unreacted water vapor and by-products were purged from the reaction chamber with a pulse of inert gas for a pulse time of 3 seconds. This step was cycled 15 times to obtain a 1 nm thick A1 2 0 3 low k material electric field enhancement layer 314.
  • TiN is grown as a top electrode 315 by a physical vapor deposition method on the above-mentioned high-k material and low-k material stack, as shown in Fig. 6.
  • a resistive memory device pattern is defined by photolithography, and then the desired resistive memory device structure is etched, and then the insulating isolation layer 316 is grown by CVD again, as shown in FIG.
  • the invention combines the traditional film preparation method to realize the preparation of the resistive memory device structure with adjustable electric field distribution, thereby completely solving the disadvantages of unstable performance of the resistive memory on the practical road in experiments and theory.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

提供了一种采用电场增强层的阻变存储器，包括：顶电极（201）、底电极（203）以及位于顶电极（201）和底电极（203）之间的由第一层电阻转变层（202b）和第二层电阻转变层兼电场增强层（202a）组成的叠层；第二层电阻转变层兼电场增强层（202a）和第一层电阻转变层（202b）相邻，并具有比第一层电阻转变层（202b）低的介电常数。本发明还提供了一种采用电场增强层的阻变存储器的制造方法。本发明选用不同介电常数的阻变功能材料组成叠层结构来调节阻变存储器单元中的电场分布，进而通过控制阻变存储器器件结构中的电场分布来实现阻变存储器在阻变过程中所形成的导电通道结构和数量上的控制。本发明的阻变存储器性能稳定可控。

Description

一种采用电场增强层的阻变存储器结构及其制备方法 技术领域
本发明属于不挥发存储器技术领域， 具体涉及一种阻变存储器结构及其 制造方法， 尤其涉及一种采用电场增强层的阻变存储器结构及其制造方法。 背景技术
随着集成电路工艺技术节点的不断缩小， 传统的闪存（Flash )非挥发性 存储器由于其浮栅不能随着集成电路工艺的发展而无限制地减薄， 闪存也就 很难突破 45纳米的工艺瓶颈， 此外， 动、 静态存储器断电后易丢失数据。 近 年来， 各种新型的非挥发性存储器得到了迅速发展,如铁电存储器 （FRAM)、 磁存储器 (MRAM) 、 相变存储器 (PRAM)和阻变存储器 (RRAM：)。
在这些存储器当中， 阻变存储器的信息读写是依靠读取或者改变阻变材 料的电阻来实现的。 通常的阻变材料具有高阻和低阻两种状态。 阻变存储器 就是依靠材料本身高阻和低阻两种状态的改变来存储信息的。 图 1为一个典 型阻变存储器单元的剖面图， 在该阻变存储器单元 100中， 电阻转变存储层 102位于顶电极 101和底电极 103之间。 顶电极 101和底电极 103通常使用 Pt和 Ti等化学性质较稳定的金属材料， 电阻转变存储层 102通常为 Ti02、 ZrO> Cu20和 SrTi03等二元或三元金属氧化物。 电阻转变存储层 102的电阻 值在外加电压作用下可以具有高阻态和低阻态两种不用的状态， 其可以分别 用来表征 "0"和 "Γ 两种状态。 在不同的外加电压条件下， 阻变存储器的 电阻值在高阻态和低阻态之间可以实现可逆转换， 以此来实现信息的存储。
随着集成电路技术的进一步发展，大量具有阻变特性的材料相继被报道， 例如 Si02、 NiO、 CuxO、 Ti02、 HfOx、 ZrOx。 阻变存储器因为其具有制备简 单、 存储密度高、 操作电压低、 读写速度快、 保持时间长、 非破坏性读取、 低功耗、 与传统 CMOS工艺兼容性好等优势而得到了很大的重视， 被认为是 成为下一代"通用"存储器的强有力候选者之一。 ' 在电阻式存储器件中， 工作性能的稳定性， 包括写入、擦除电压稳定性、 高低阻的信号比值的稳定性是电阻式存储器实用化的关键问题， 通常阻变存 储器的主要问题是不稳定的擦除电压和擦除电流。 寻求性能可优化的高稳定 性电阻式存储器的制备方法成为阻变存储器件走向工业应用的关键性课题。 发明的公开
本发明的目的在于提出一种性能可优化的高稳定性阻变存储器及其制造 方法， 以解决阻变存储器器件走向工业应用中出现的问题。
本发明提出阻变存储器， 选用不同介电常数的阻变功能材料组成叠层来 作为电阻转变存储层， 其结构包括顶电极、 底电极以及位于所述顶电极与所 述底电极之间的由
由第一层电阻转变层和第二层电阻转变层兼电场增强层组成的叠层； 所述的第二层电阻转变层兼电场增强层和第一层电阻转变层相邻， 并具 有比所述第一层电阻转变层低的介电常数。
所述的第二层电阻转变层兼电场增强层可采用较低介电常数材料， 如
Si02、 A1203等， 所述第一层电阻转变层可采用较高介电常数材料， 如 Hf02、 21"02或1^205, 或者其混合介质材料等。
同时， 本发明还提出了上述阻变存储器的制造方法， 具体包括： 在基底上形成阻变存储器的底电极；
在所述底电极上形成第一层电阻转变层；
在所述电阻转变层上形成作为调节电场用的第二层电阻转变兼电场增强 层；
在所述电阻转变兼电场增强层上形成阻变存储器的顶电极。
进一步地， 所述的底电极为 Pt/Ti、 Au/Ti、 TiN、 Ru或 Cu等金属材料。 所述的第一层电阻转变层由 Hf02、 Zr02、 Nb205或者其混合介质材料等高介 电常数材料形成。 所述的第二层电阻转变兼电场增强层由 Si02、 A1203等低 介电常数材料形成。 所述的顶电极为 Al、 Pt、 Ru、 TiN、 TaN等金属材料。
在传统的阻变存储器通常包括上电极、 阻变层和下电极。 在本发明中， 在上电极和下电极中还加入了一层电阻转变兼电场增强层来增强该阻变层 内的电场。
由于不同介电常数的氧化物材料的叠层结构在两端施加电压的情况下， 具有不同介电常数的介质层的分压能力有所差别， 这样导致电场会在各个介 质层 ^布，差: ^性。 ，此， 通:^选用不同介电常数的阻变功能材料组成叠 阻变存储器器件结构中的电场分布来实现阻变存储器在阻变过程中所形成 的导电通道结构和数量上的控制。 当第二层电阻转变兼电场增强层的介电常 数较第一层电阻转变层的介电常数低时， 第二层电阻转变层 （阻变层） 内电 场可以得到增强。 因此， 第二层阻变层内的电场可以通过不同层之间的介电 常数和厚度来进行调节。
本发明结合传统的薄膜制备方法来实现电场分布可调节的阻变存储器器 件结构的制备， 从而在实验和理论上彻底解决阻变存储器在实用化道路上所 遇到性能不稳定的弊病。 附图的筒要说明
图 1为一种传统技术的阻变存储器结构的截面图。
图 2为本发明所提出的一种性能可控型阻变存储器结构的截面图。
图 3至图 7为本发明所提出的以在 MOSFET后道互连工艺中集成如图 2 所示阻变存储器为实施例的制备工艺流程图。
实现本发明的最佳方式
下面结合附图与具体实施方式对本发明作进一步详细的说明， 在图中， 为了方便说明，放大或缩小了层和区域的厚度，所示大小并不代表实际尺寸。 尽管这些图并不能完全准确的反映出器件的实际尺寸， 但是它们还是完整的 反映了区域和组成结构之间的相互位置， 特别是组成结构之间的上下和相邻 关系。
图 2为本发明所提供的一个性能可控型阻变存储器的实施例的截面图， 如图 2所示，该阻变存储器包括顶电极 201、底电极 203以及位于顶电极 201 与底电极 203之间的复合介质层 202， 复合介质层 202包括第一层电阻转变 层（通常为高介电常数（高 k )材料） 202b和和第二层电阻转变层兼电场增 强层（通常为低介电常数（低 k )材料） 202a。 所谓高介电常数和低介电常 数是相对二氧化硅而言的。 介电常数高于二氧化硅为高介电常数材料， 介电 常数低于二氧化硅则为低介电常数。 在本发明中， 二氧化硅被归为低介电常 数材料中。
本发明所提出的阻变存储器可以集成于不同结构的半导体器件中， 以下 所述叙述的是，以在传统 MOSFET后道互连工艺中集成阻变存储器为实施例 的制造工艺流程。
首先，提供一个硅衬底 300，然后采用标准 CMOS工艺，完成前道 CMOS 器件的制备， 如图 3所示， 其具体的工艺包括有： 1、 采用扩散工艺或者离子 注入工艺在硅衬底 300内形成源区 301和漏区 302。 2、 采用氧化工艺、 薄膜 淀积工艺以及光刻工艺和刻蚀工艺，在衬底 300上形成器件的栅氧化层 303、 栅电极 304和绝缘层 305 , 绝缘层 305将栅区与器件的其它导体层隔离。
接下来， 利用化学气相沉积（CVD )方法淀积 SiOC低 k介质材料来形 成层间隔离层 306, 然后光刻、 刻蚀定义出互连通孔位置， 并利用反应离子 溅射一层 TiN来作为铜的扩散阻挡层， 然后利用原子层淀积（ALD )技术在 TiN上生长 Ru层形成 Ru/TiN结构 307。 接着采用电镀方法形成铜连线 308 , 并用化学机械抛光（CMP )技术平整化 wafer表面，如图 4所示。
接下来，淀积一层氮化硅刻蚀阻挡层 309，并再次淀积 SiOC层间隔离层 310, 然后光刻、 刻蚀定义出第二层互连位置， 再淀积形成 Ru/TiN扩散阻挡 层 311， 并电镀铜互连线 312, 之后采用 CMP技术抛光， 如图 5所示。 接下来，将样品放入原子层淀积设备中，在脉冲周期中的第一脉冲之前， 将晶片加热到约 300°C。在整个 ALD生长期间保持这一温度。 在脉冲周期中 的第一脉冲之前， 使反应室达到约 ITorr的压力， 并且在整个工艺期间也保 持这一压力。
将加热到 70°C的铪的有机物反应前躯体 (四乙基甲胺基）铪（ TEMAH ) 挥发出的气体在氮气作为载体气体流以脉冲形式引入到反应室中 , 脉冲时间 为 2秒。 将非活性气体以脉冲形式引入反应腔， 从反应腔中清除未反应的金 属有机前驱体和副产物。 非活性清除气体包括氮、 氩气和氦气， 脉冲时间为 3秒。通常在约 1至约 2秒范围内的脉冲时间将水蒸气脉冲引入到反应室中。 从反应室中清除未反应的水蒸气和副产物， 脉冲时间为 3秒。 将此步骤循环 100次， 得到 10纳米厚的 Hf〇2高 k材料电阻转变层 313。
将液态前躯体三甲胺（ TMA )挥发出的气体以脉冲形式引入到反应室中， 脉冲时间为 1秒。 将非活性气体以脉冲形式引入反应腔， 从反应腔中清除未 反应的金属有机前驱体和副产物。 非活性清除气体包括氮、 氩和氦气脉冲时 间为 3秒。 以 1秒的脉冲时间将水蒸气引入到反应腔体中。 用非活性气体脉 冲从反应腔体中清除未反应的水蒸气和副产物， 脉冲时间为 3秒。 将此步骤 循环 15次， 得到 1纳米厚的 A1203低 k材料电场增强层 314。
接着， 在以上长好的高 k材料与低 k材料叠层上利用物理气相淀积方法 生长 TiN作为顶电极 315, 如图 6所示。
最后， 利用光刻技术定义出阻变存储器器件图形， 接着刻蚀出所需的阻 变存储器器件结构， 然后再次利用 CVD方法生长绝缘隔离层 316, 如图 7所 示
工业应用性
本发明结合传统的薄膜制备方法来实现电场分布可调节的阻变存储器器 件结构的制备， 从而在实验和理论上彻底解决阻变存储器在实用化道路上所 遇到性能不稳定的弊病。
如上所述， 在不偏离本发明精神和范围的情况下， 还可以构成许多有很 大差别的实施例。 应当理解， 除了如所附的权利要求所限定的， 本发明不限 于在说明书中所述的具体实例。 -

Claims

权利要求
1、 一种阻变存储器， 其特征在于， 所述的阻变存储器包括顶电极、底电 极以及位于所述顶电极与所述底电极之间的由第一层电阻转变层和第二层电 阻转变层兼电场增强层组成的叠层；
所述的第二层电阻转变层兼电场增强层和第一层电阻转变层相邻， 并具 有比所述第一层电阻转变层低的介电常数。
2、根据权利要求 1所述的阻变存储器， 其特征在于， 所述的第二层电阻 转变层兼电场增强层的材料为 Si02或 A1203。
3、根据权利要求 1所述的阻变存储器， 其特征在于， 所述的第一层电阻 转变层材料为 Hf02、 Zr02、 Nb205中的至少一种。
4、根据权利要求 1所述的阻变存储器， 其特征在于， 所述的底电极材料 为 Pt/Ti、 Au/Ti、 TiN、 Ru或 Cu。
5、才^据权利要求 1所述的阻变存储器， 其特征在于， 所述的顶电极材料 为 Al、 Pt、 Ru、 TiN或 TaN。
6、 一种阻变存储器的制造方法， 其特征在于具体步骤包括：
在基底上形成阻变存储器的底电极；
在所述底电极上形成第一层电阻转变层；
在所述一层电阻转变层上形成第二层电阻转变层， 该层兼电场增强层； 在所述电阻转变层兼电场增强层上形成阻变存储器的顶电极。
7、根据权利要求 6所述的阻变存储器的制造方法， 其特征在于， 所述的 底电极由 Pt/Ti、 Au/Ti、 TiN、 Ru或 Cu材料制备。
8、根据权利要求 6所述的阻变存储器的制造方法， 其特征在于， 所述的 第一层电阻转变层材料为 Hf02、 Zr02、 Nb205中的至少一种。
9、根据权利要求 6所述的阻变存储器的制造方法， 其特征在于， 所述的 电阻转变层兼电场增强层由 Si02、 A1203等低介电常数材料形成。
10、 根据权利要求 6所述的阻变存储器的制造方法， 其特征在于， 所述 的顶电极由 Al、 Pt、 Ru、 TiN或 TaN材料制备。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140302659A1 (en) * 2011-10-06 2014-10-09 Intermolecular, Inc. Method for Reducing Forming Voltage in Resistive Random Access Memory

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248814A (ja) * 2011-05-31 2012-12-13 Toshiba Corp 半導体装置およびその製造方法
CN102222763A (zh) * 2011-06-03 2011-10-19 复旦大学 一种采用电场增强层的阻变存储器结构及其制备方法
CN102593351A (zh) * 2012-01-20 2012-07-18 北京大学 一种低功耗阻变存储器结构及制备方法
CN103378103B (zh) * 2012-04-24 2016-08-03 华邦电子股份有限公司 非挥发性存储器及其制造方法
CN102709192A (zh) * 2012-06-21 2012-10-03 复旦大学 一种集成阻变存储器的mos晶体管结构的制造方法
CN102709308A (zh) * 2012-06-21 2012-10-03 复旦大学 一种集成阻变存储器的mos晶体管结构及其制造方法
CN102751437B (zh) * 2012-07-03 2014-11-05 北京有色金属研究总院 一种免电激活的阻变存储器及其制备方法
US9000407B2 (en) * 2013-05-28 2015-04-07 Intermolecular, Inc. ReRAM materials stack for low-operating-power and high-density applications
WO2015012839A1 (en) * 2013-07-25 2015-01-29 Hewlett-Packard Development Company, L.P. Resistive memory device having field enhanced features
CN104617218B (zh) * 2013-11-04 2018-12-11 华邦电子股份有限公司 电阻式存储装置及其制作方法
US9178144B1 (en) * 2014-04-14 2015-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. RRAM cell with bottom electrode
US9502647B2 (en) * 2014-05-28 2016-11-22 Taiwan Semiconductor Manufacturing Company Limited Resistive random-access memory (RRAM) with a low-K porous layer
US9431609B2 (en) * 2014-08-14 2016-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Oxide film scheme for RRAM structure
CN105514263A (zh) * 2014-09-23 2016-04-20 中芯国际集成电路制造(北京)有限公司 阻变式存储器单元及其制造方法和阻变式存储器
TWI556245B (zh) * 2015-02-16 2016-11-01 國立中山大學 電阻式記憶體
TWI605622B (zh) * 2016-04-27 2017-11-11 國立中山大學 電阻式記憶體
TWI699914B (zh) 2016-09-08 2020-07-21 聯華電子股份有限公司 半導體元件及其製作方法
KR20180134123A (ko) * 2017-06-08 2018-12-18 에스케이하이닉스 주식회사 저항 변화 메모리 소자
CN110379920A (zh) * 2019-06-13 2019-10-25 北京航空航天大学 一种基于熔洞状分级多孔氧化物忆阻器
CN111933795A (zh) * 2020-08-19 2020-11-13 惠科股份有限公司 记忆体单元及其制造方法、记忆体阵列
CN112510147B (zh) * 2020-12-04 2022-05-20 武汉理工大学 一种全无机量子点基阻变存储器及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1832176A (zh) * 2005-02-28 2006-09-13 株式会社半导体能源研究所 半导体器件及其操作方法
CN101765914A (zh) * 2007-08-06 2010-06-30 索尼公司 存储元件和存储装置
CN102017145A (zh) * 2008-12-04 2011-04-13 松下电器产业株式会社 非易失性存储元件以及非易失性存储装置
CN102222763A (zh) * 2011-06-03 2011-10-19 复旦大学 一种采用电场增强层的阻变存储器结构及其制备方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080151466A1 (en) * 2006-12-26 2008-06-26 Saint-Gobain Ceramics & Plastics, Inc. Electrostatic chuck and method of forming
US8183553B2 (en) * 2009-04-10 2012-05-22 Intermolecular, Inc. Resistive switching memory element including doped silicon electrode
US8343813B2 (en) * 2009-04-10 2013-01-01 Intermolecular, Inc. Resistive-switching memory elements having improved switching characteristics
US8129704B2 (en) * 2008-05-01 2012-03-06 Intermolecular, Inc. Non-volatile resistive-switching memories
US7977152B2 (en) * 2008-05-10 2011-07-12 Intermolecular, Inc. Non-volatile resistive-switching memories formed using anodization
US20100052072A1 (en) * 2008-08-28 2010-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Dual gate structure on a same chip for high-k metal gate technology
US8049305B1 (en) * 2008-10-16 2011-11-01 Intermolecular, Inc. Stress-engineered resistance-change memory device
CN102574876A (zh) * 2009-07-06 2012-07-11 琳德股份公司 溶液基前体
US8675381B2 (en) * 2010-07-20 2014-03-18 Macronix International Co., Ltd. Transistor having an adjustable gate resistance and semiconductor device comprising the same
DE102010040058A1 (de) * 2010-08-31 2012-03-01 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Polysiliziumwiderstände, die in einem Halbleiterbauelement mit Metallgateelektrodenstrukturen mit großem ε hergestellt sind
US20120181584A1 (en) * 2011-01-19 2012-07-19 Ru Huang Resistive Field Effect Transistor Having an Ultra-Steep Subthreshold Slope and Method for Fabricating the Same
CN102208532A (zh) * 2011-05-27 2011-10-05 复旦大学 一种采用电场增强层的阻变存储器及其制备方法
US8288297B1 (en) * 2011-09-01 2012-10-16 Intermolecular, Inc. Atomic layer deposition of metal oxide materials for memory applications

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1832176A (zh) * 2005-02-28 2006-09-13 株式会社半导体能源研究所 半导体器件及其操作方法
CN101765914A (zh) * 2007-08-06 2010-06-30 索尼公司 存储元件和存储装置
CN102017145A (zh) * 2008-12-04 2011-04-13 松下电器产业株式会社 非易失性存储元件以及非易失性存储装置
CN102222763A (zh) * 2011-06-03 2011-10-19 复旦大学 一种采用电场增强层的阻变存储器结构及其制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140302659A1 (en) * 2011-10-06 2014-10-09 Intermolecular, Inc. Method for Reducing Forming Voltage in Resistive Random Access Memory
US9761800B2 (en) * 2011-10-06 2017-09-12 Intermolecular, Inc. Method for reducing forming voltage in resistive random access memory

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