Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
  • G06F12/023—Free address space management
  • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
  • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5628—Programming or writing circuits; Data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
  • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
  • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
  • G06F2212/72—Details relating to flash memory management
  • G06F2212/7206—Reconfiguration of flash memory system
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
  • G11C2211/564—Miscellaneous aspects
  • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Definitions

• the present invention relates to the field of semiconductor memory, and more particularly to a programming method for improving the reliability of a multi-layer memory flash memory device in a case where a flash memory device is used as a storage medium for a solid state hard disk controller, a flash memory controller, or the like. Background technique
• the storage unit of multi-layer storage flash memory device can save multiple bits of logic information by setting multiple sets of threshold voltages, thereby significantly improving the storage of flash memory devices without increasing hardware overhead. capacity.
• Multi-layered memory flash devices have become the mainstream of flash memory devices due to their high integration and low cost.
• the memory cells in the multi-level memory flash need to be programmed multiple times, as shown in Figure 1.
• the multi-layered flash memory is directly transferred from the erased state "E” to the second programmed state "D2", which requires minimal programming time.
• the multi-layered flash memory jumps from the erased state "E” to the first programmed state "D1".
• the programming operation is completed by two rounds of operations: The first round of operation first jumps from the erased state "E” to the first programmed state "D1", the second The wheel operation is then jumped from the first programming state "D1" to the third programming state "D3".
• the array structure inside the multi-layer storage flash memory is shown in Figure 2.
• the MSB and LSB bits of the physical unit in the multi-level memory are mapped to the MSB page and the LSB page, respectively.
• the physical units on the WL0 line are mapped to pages 0, 1, 4, and 5, respectively.
• page 0 and page 1 are MSB pages
• pages 4 and 5 are LSB pages.
• the physical units on the WL 1 line are mapped to pages 2, 3, 8, and 9, respectively, where pages 2 and 3 are MSB pages, and pages 8 and 9 are LSB pages.
• page 250 and page 251 are MSB pages
• pages 254 and 255 are LSB pages.
• the technical problem to be solved by the present invention is to provide a programming method for improving the reliability of a multi-layered memory flash memory device, reducing the error rate of the multi-layered memory flash memory during use, prolonging the service life of the device, and improving the overall reliability of the system. Sex.
• the technical idea of improving the reliability of the multi-layer storage flash memory device and reducing the error rate of the multi-layer storage flash memory is to reduce the floating gate by skipping some specific logical pages during the programming process.
• the effect of the coupling effect on the flash operation is to reduce the floating gate by skipping some specific logical pages during the programming process.
• the present invention proposes a programming method of three specific multi-layered memory flash arrays, which are operated by a flash controller, characterized in that the flash controller performs a programming process on the flash memory. Select to skip some of the logical pages for programming, and you can choose to skip the LSB pages in different directions, including at least three programming methods:
• the second programming method is a method of further improving on the basis of programming mode one.
• the second programming mode is to skip the two sets of LSB pages in the diagonal direction of the physical page of the multi-layer memory flash during the programming process, and reduce the number of programming of the multi-layer memory flash array in the diagonal direction to obtain lower
• the error rate reduces the interference between flash memory cells during programming.
• Programming mode 3 In the programming process, select the number of the logical page that needs to be skipped N pass % '.
• the third way of programming is to improve on the basis of programming mode 2 to reduce the mutual interference in the vertical direction of the memory cell array.
• Program mode 3 skips the adjacent two sets of LSB pages of the physical row in the physical page of the multi-level memory flash during programming, reducing the number of programming times of the multi-layer memory flash array in the vertical direction to obtain lower errors. Rate, which reduces interference between flash memory cells during programming.
• the above three different programming methods significantly reduce the error rate of the flash block and improve the reliability of the flash array.
• the present invention further provides a switching control method for the programming mode of the multi-layer memory flash array, comprising the following steps:
• three levels of thresholds are set in order from small to large, respectively being the first threshold, the second threshold, and the third threshold;
• the normal normal programming mode is adopted, that is, programming. Write all logical pages in the multi-layer storage flash block at the same time, and monitor the number of errors during use;
• the controller When the error of the block reaches the first threshold during use, the controller will programmatically program a pair of multi-level memory flashes while continuing to monitor the number of errors in the multi-layer memory flash; During the process, when the error of the block increases to the second threshold during use, the programming mode of the controller is switched from the programming mode to the programming mode 2, and the error condition of the flash memory is continuously monitored;
• the controller will programmatically three, that is, operate the multi-layer memory flash memory in an optimized manner.
• the controller can balance the programming times of each physical storage unit and obtain the lowest error rate, thereby achieving a balance between capacity and error rate, effectively extending the service life of the multi-layer storage flash memory.
• Figure 1 State transition diagram of a multi-layered storage flash device.
• Figure 2 Storage array diagram of a multi-tiered storage flash device.
• Figure 3 Floating gate coupling effect of a multi-layered memory flash device.
• FIG. 9 Flow chart of the switching control of the programming mode of a multi-layered memory flash device.
• Multi-layered storage flash memory is programmed in physical blocks as part of the programming process.
• This floating gate coupling effect interferes with adjacent memory cells in the horizontal, diagonal, and vertical directions in the memory array, respectively.
• the present invention designs three programming modes to reduce floating gates in horizontal, diagonal and vertical directions by skipping special programming pages of adjacent memory cells during programming.
• the coupling effect uses a variety of programming methods to balance the loss, further extending the life of the flash memory device.
• One way of programming is to skip some logic pages of the blocks in the multi-layer memory flash during programming to improve the floating gate coupling effect in the horizontal direction.
• the specific programming mode of programming mode one is shown in Figure 4. After the programming starts, the programming mode first programs pages 0, 1, 2, 3 in sequence, then skips page 4; then programs pages 5, 6, and 7, then skips page 8; then page 9, 10, 1 1 programming, then skip page 12; and so on, at the end of the block, programmatically program a pair of pages 249, 250, 251, skip page 252; finally program page 253 and page 255, skip page 254 , thus completing the entire programming process for the multi-layer storage flash memory.
• programming mode 1 the number of logical pages that need to be skipped is:
• i is a natural number and li 64.
• the second programming method is further improved on the basis of programming mode one.
• Programming mode 2 mainly achieves a lower error rate by reducing the number of times the multi-layer memory flash is programmed in the diagonal direction. The specific process is shown in FIG. 5.
• programming mode 2 After programming begins, programming mode 2 first programs pages 0, 1, 2, 3 in sequence, then skips page 4; then programs pages 5, 6, 7, 8 and then skips page 9; 10, 1 1 programming, then skip page 12; and so on, at the end of the block, programming mode two pages 249, 250, 251 programming, skip page 252; finally page 253 and page 254 programming, skip page 255 , thus completing the entire programming process for the multi-layer storage flash block.
• the programming between mode 2 further reduces the interference between flash memory cells during programming.
• the third way of programming is to improve the mutual interference in the vertical direction of the memory cell array based on the second programming mode.
• the specific programming mode of programming mode 3 is shown in Figure 6. After programming begins, programming mode 3 first programs pages 0, 1, 2, 3 in sequence, then skips pages 4, 5; then pages 6, 7, 8, 9, 10, 11 and then skips Pages 12, 13; and so on, at the end of the block, programming three pairs of pages 249, 250, 251 programming, skipping pages 252, 253; finally programming page 254 and page 255, thus completing the entire pair of multi-layer storage flash Programming process.
• programming mode three the logical pages that need to be skipped are:
• Programming mode 3 further reduces the floating gate coupling effect of the multi-layer memory flash during programming by jumping these pages, thereby reducing the error rate.
• the programming page in the flash memory is as shown in FIG.
• Programming mode skips a set of LSB pages on the same physical line in the flash block; programming mode 2 skips two sets of LSB pages in the diagonal direction of the flash block; programming mode three skips two sets of spaced physical lines in the flash block Adjacent LSB page.
• the flash block with the normal mode programming After 30,000 cycles of erasing, the flash block with the normal mode programming has the highest error rate, and the error rate of the flash block using the programming mode is significantly lower than that of the normal programming mode, while the flash block of the programming mode 2 is used.
• the error rate is lower than the programming mode one, and the flash block with the programming mode three has the lowest error rate.
• the present invention adopts a plurality of programming mode switching control methods to balance the loss of the flash memory device, and the control flow thereof is as shown in FIG.
• the flash controller According to the number of flash errors, in the flash controller, three levels of thresholds are set in order from small to large, respectively being the first threshold, the second threshold, and the third threshold; these three thresholds
• the setting can be performed by the technician in advance by performing pressure experiments on the flash memory device and based on the life of the test flash memory device.
• the first threshold value is set in the error rate of 2.5x 10
• the second threshold value is set in the error rate 5 ⁇ 10- 5
• the third threshold value is set in the error rate 8xl (r 5.
• the controller When the block is in use error When the first threshold is reached, the controller will programmatically program a pair of multi-level memory flashes while continuing to monitor the number of errors in the multi-layered flash memory. During the next use, when the block is in use When the error in the second threshold is reached, the programming mode of the controller is switched from programming mode to programming mode 2 and continues to monitor the error condition of the flash memory. After continuing to increase and reach the third threshold, the controller will programmatically three, that is, operate the multi-layer memory flash memory in an optimized manner. Through such a switching method, the controller can balance the programming times of each physical storage unit and obtain the lowest error rate, thereby achieving a balance between capacity and error rate, effectively extending the service life of the multi-layer storage flash memory.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Techniques For Improving Reliability Of Storages (AREA)
• Read Only Memory (AREA)
• For Increasing The Reliability Of Semiconductor Memories (AREA)

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• 2011
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• 2012
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