WO2012157284A1 - 並列ビットインターリーバ - Google Patents
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- WO2012157284A1 WO2012157284A1 PCT/JP2012/003264 JP2012003264W WO2012157284A1 WO 2012157284 A1 WO2012157284 A1 WO 2012157284A1 JP 2012003264 W JP2012003264 W JP 2012003264W WO 2012157284 A1 WO2012157284 A1 WO 2012157284A1
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1168—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices
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- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
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- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
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- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
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- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
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- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
- H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
- H04L1/0618—Space-time coding
Definitions
- the present invention relates to the field of digital communications, and more particularly to a bit interleaver for bit interleaved coded modulation systems using pseudo-cyclic low density parity check codes.
- Non-Patent Document 1 a bit-interleaved coding and modulation (BICM) system has been used in the digital communication field (see, for example, Non-Patent Document 1).
- BICM bit-interleaved coding and modulation
- the BICM system generally performs the following three steps:
- An object of the present invention is to provide an interleaving method capable of realizing the efficiency of interleaving applied to a codeword of a pseudo-cyclic low density parity check code.
- the bit interleaving method of the present invention is a bit interleaving method in a communication system using a pseudo-cyclic low density parity check code, wherein the bit interleaving method comprises N pieces each consisting of Q bits
- the code word of the pseudo cyclic low density parity check code which is composed of cyclic blocks, and a bit permutation process of changing the arrangement order of the bits of the code word with respect to the bits of the code word
- the bit permutation step and the codeword subjected to the bit permutation process are each composed of M bits, each of which indicates any one of 2 M predetermined constellation points.
- M / F different from the M blocks of each of the F bits of each of the different cyclic blocks, and each of the sections All bits of such mapped only into Q of the constellation words associated with the corresponding section, and performs the bit permutation process.
- bit interleaving method of the present invention it is possible to realize the efficiency of interleaving to be applied to the code word of the pseudo-cyclic low density parity check code.
- FIG. 1 is a block diagram showing the configuration of a transmitter including a general BICM encoder.
- FIG. 7 shows a parity check matrix of the RA QC LDPC code of FIG. 3 after row permutation.
- (A) It is a figure which shows the write-in process of the bit of the code word of 16K code (LDPC code whose LDPC code word length is 16200 bits) performed by 12 column-row interleavers, (b) is column-row. The figure which shows the read-out process of the bit of the code word written in (a) performed by the interleaver.
- (A) It is a figure which shows the write-in process of the bit of the code word of 16K code performed by 8 column-row interleavers, (b) is the code written by (a) performed by column-row interleaver
- FIG. 6 illustrates a potential problem for a 16K code in an 8 column DVB-T 2 bit interleaver.
- FIG. 6 illustrates a potential problem for a 16K code in a 12-sequence DVB-T 2 bit interleaver.
- FIG. 7 illustrates a potential problem when applying column twist processing to a 16K code in an 8-row DVB-T 2 bit interleaver.
- FIG. 7 illustrates a potential problem when applying column twist processing to a 16K code in a 12-column DVB-T 2 bit interleaver.
- (A) is a figure explaining the 1st condition which enables provision of the highly efficient interleaver which was found as a result of inventor's earnest research
- (b) demonstrates the 2nd condition Figure.
- FIG. 5 is a diagram showing a function of mapping by an interleaver according to an embodiment of the present invention. The block diagram which shows the structure of the interleaver which concerns on one Embodiment of this invention.
- FIG. 20 is a block diagram which shows the example of 1 structure of the section permutation unit which implements the section permutation of FIG. 20, (b) is a figure which shows the function of the mapping by the section permutation unit of (a).
- (A) is a block diagram which shows the other structural example of the section permutation unit which implements the section permutation of FIG. 20, (b) shows the function of the mapping by the section permutation unit of (a).
- Figure. The block diagram which shows the structure of the interleaver which concerns on other embodiment of this invention.
- FIG. 24 is a block diagram showing a configuration example of the bit interleaver of FIG. 23; The block diagram which shows one structural example of the transmitter which concerns on other embodiment of this invention.
- FIG. 24 is a block diagram showing a configuration example of the bit interleaver of FIG. 23; The block diagram which shows one structural example of the transmitter which concerns on other embodiment of this invention.
- FIG. 7 is a block diagram illustrating an example implementation of a BICM encoder according to yet another embodiment of the present invention.
- FIG. 7 is a block diagram illustrating an example configuration of a receiver having a non-iterative BICM decoder according to still another embodiment of the present invention.
- FIG. 10 is a block diagram illustrating an example configuration of a receiver having an iterative BICM decoder according to yet another embodiment of the present invention.
- FIG. 7 is a block diagram illustrating an example implementation of an iterative BICM decoder according to yet another embodiment of the invention. The figure which shows an example of the cyclic block of object of a parallel interleaver, and the cyclic block of non object.
- (A) is a figure explaining the 1st condition which enables provision of the highly efficient interleaver which was found as a result of inventor's earnest research
- (b) demonstrates the 2nd condition Figure.
- the block diagram which shows the structure of the interleaver which concerns on the further another embodiment of this invention.
- the block diagram which shows one structural example of a folding section permutation unit.
- FIG. 36 is a block diagram showing a configuration example of the interleaver of FIG. 35.
- the block diagram which shows one structural example of the transmitter which concerns on other embodiment of this invention.
- FIG. 7 is a block diagram illustrating an example configuration of a receiver having a non-iterative BICM decoder according to still another embodiment of the present invention.
- FIG. 10 is a block diagram illustrating an example configuration of a receiver having an iterative BICM decoder according to yet another embodiment of the present invention.
- FIG. 1 is a block diagram showing the configuration of a transmitter including a general bit-interleaved coding and modulation (BICM) encoder.
- the transmitter 100 shown in FIG. 1 comprises an input processing unit 110, a BICM encoder (including a low-density parity check (LDPC) encoder 120, a bit interleaver 130, a constellation mapper 140), and a modulator 150.
- a BICM encoder including a low-density parity check (LDPC) encoder 120, a bit interleaver 130, a constellation mapper 140
- LDPC low-density parity check
- the input processing unit 110 converts the input bit stream into multiple blocks of a predetermined length.
- the LDPC encoder 120 encodes the block into a codeword using an LDPC code and transmits the codeword to the bit interleaver 130.
- the bit interleaver 130 interleaves the LDPC code word, performs interleaving processing, and then divides it into a cell word (constellation word) sequence.
- Constellation mapper 140 maps each cell word (constellation word) to a sequence of constellations (eg, QAM).
- a general modulator 150 at the output end includes all processing blocks from the output of the BICM encoder to a Radio Frequency (RF) power amplifier.
- RF Radio Frequency
- An LDPC code is a linear error correction code which is completely defined by a parity check matrix (PCM).
- PCM is a binary sparse matrix and indicates a connection of codeword bits (also referred to as variable node) and parity check (also referred to as check node).
- the PCM columns and rows correspond to variable nodes and check nodes, respectively.
- the combination of the variable node and the check node is indicated by an element "1" in the PCM.
- the QC LDPC code has a configuration particularly suitable for hardware implementation. In fact, QC LDPC codes are used in most of today's standards.
- the PCM of the QC LDPC code has a special configuration having a plurality of cyclic matrices.
- a circulant matrix is a square matrix in which each row is in the form of one cyclic shift of elements in the row immediately before it, and one, two, or more folded diagonal columns May exist.
- the size of each circulant matrix is Q ⁇ Q.
- Q is referred to as a cyclic factor of the QC LDPC code.
- the pseudo-cyclic structure as described above allows Q check nodes to be processed in parallel, and QC LDPC codes are clearly advantageous codes for efficient hardware implementation.
- one of the smallest squares represents one element of the PCM, and of these, the black square elements are “1”, and the other elements are “0”. It is.
- This PCM has a circulant matrix with one or two superimposed diagonal columns.
- the codeword bits are divided into blocks with Q bits.
- a block of cyclic coefficient Q bits is referred to herein as a cyclic block (or cyclic group).
- RA QC LDPC repeat-accumulate quasi-cyclic low-density parity check
- RA QC LDPC codes are known for their ease of coding and are adopted in a number of standards (eg, second generation DVB standards such as DVB-S2 standard, DVB-T2 standard, DVB-C2 standard) There is.
- the right side of the PCM corresponds to a parity bit, and the arrangement of the “1” element in that portion has a step structure.
- FIG. 3 exemplifies the PCM of the RA QC LDPC code whose coding rate is 2/3.
- DVB-T stands for Digital Video Broadcasting-Terrestrial
- DVB-S2 stands for Digital Video Broadcasting-Second Generation Satellite
- DVB-T2 stands for Digital Video Broadcasting-Second Generation Terrestrial
- DVB- C2 is an abbreviation of Digital Video Broadcasting-Second Generation Cable.
- the parity part of the PCM By performing appropriate permutation to change the order of bits only to the parity bits of the PCM shown in FIG. 4 subjected to the row permutation, the parity part of the PCM also has a pseudo cyclic structure.
- This technique is well known in the art, and is used under the name of parity interleaving or parity permutation in the DVB-T2 standard or the like.
- the PCM obtained as a result of applying parity permutation to the PCM shown in FIG. 4 is shown in FIG.
- LDPC codewords differ in significance from bit to bit, and constellations differ in robustness from bit to bit. Mapping the bits of the LDPC codeword directly to the constellation, ie without interleaving, does not lead to optimum performance. For this reason, the bits of the LDPC code word need to be interleaved before mapping the bits of the LDPC code word to the constellation.
- a bit interleaver 130 is provided between the LDPC encoder 120 and the constellation mapper 140. Careful design of the bit interleaver 130 improves the relevancy between bits of the LDPC codeword and bits encoded by the constellation, leading to improved reception performance. Its performance is usually measured using Bit Error Rate (BER) as a function of Signal to Noise Ratio (SNR).
- BER Bit Error Rate
- SNR Signal to Noise Ratio
- a complex quadrature amplitude modulation (QAM) constellation consists of two independent pulse amplitude modulation (PAM) symbols, one corresponding to the real part and one to the imaginary part. It corresponds.
- the two PAM symbols each encode the same number M of bits.
- FIG. 6 which shows 8 PAM symbols using Gray codes
- the robustness levels of the bits encoded in one PAM symbol are different from each other.
- the reason why the robustness levels are different from one another is that the distance between two subsets defined by each bit (0 or 1) is different for each bit. The larger this distance, the higher the robustness level or reliability of the bit.
- the robust level of bit b3 is the highest and the robust level of bit b1 is the lowest.
- a 16 QAM constellation encodes 4 bits and has 2 robust levels.
- the 64 QAM constellation encodes 6 bits and has 3 robust levels.
- a 256 QAM constellation encodes 8 bits and has 4 robust levels.
- FIG. 7 is a block diagram showing the configuration of a general interleaver corresponding to the above parameters.
- QB1, ..., QB12 are 12 cyclic blocks
- C1, ..., C24 are 24 constellation words.
- bit interleaver 710 interleaves the 96 bits of the LDPC codeword.
- DVB-T2 As a conventional bit interleaver, one of the DVB-T2 standard (ETSI EN 302 755) is known.
- the DVB-T2 standard is an improvement on the DVB-T standard which is a television standard, and describes a second generation baseline transmission system for digital terrestrial television broadcasting.
- the DVB-T2 standard details channel coding modulation systems for transmitting digital television services and general data.
- FIG. 8A is a block diagram showing the configuration of a modulator (DVB-T2 modulator) used in the DVB-T2 standard.
- the DVB-T2 modulator 800 shown in FIG. 8 (a) comprises an input processing unit 810, a BICM encoder 820, a frame builder 830 and an OFDM generator 840.
- the input processing unit 810 converts the input bit stream into blocks of a predetermined length.
- the BICM encoder 820 performs BICM processing on the input.
- the frame builder 830 generates a DVB-T2 transmission frame configuration using inputs from the BICM encoder 820 and the like.
- the OFDM generator 840 performs pilot addition, high-speed inverse Fourier transform, guard interval insertion, and the like on the transmission frame configuration of the DVB-T2 system, and outputs a transmission signal of the DVB-T2 system.
- FIG. 8B is a block diagram showing the configuration of the BICM encoder 820 of the DVB-T2 modulator shown in FIG. 8A. However, in FIG. 8B, BCH outer coding, constellation rotation, cell interleaver, time interleaver and the like are omitted.
- the BICM encoder 820 includes an LDPC encoder 821, a bit interleaver (including a parity interleaver 822 and a column-row interleaver 823), a bit-cell demultiplexer 824, and a QAM mapper 825.
- the LDPC encoder 821 encodes a block into a codeword using an LDPC code.
- the bit interleaver (parity interleaver 822 and column-row interleaver 823) performs interleaving processing to change the order of the bits of the code word.
- the bit-cell demultiplexer 824 demultiplexes the interleaved codeword bits into cell words (constellation words).
- the QAM mapper 825 maps cell words (constellation words) to complex QAM symbols.
- the complex QAM symbol is also referred to as a cell.
- the bit-cell demultiplexer 824 may be considered to be part of a bit interleaver.
- a BICM encoder based on the DVB-T2 standard can be regarded as having the standard configuration shown in FIG.
- two codewords of 16200 bits and 64800 bits are defined.
- An LDPC code having a codeword length of 16200 bits and an LDPC code having a codeword length of 64800 bits are referred to herein as a 16K code (or 16K LDPC code) and a 64K code (or 64K LDPC code).
- the number of cyclic blocks included in one code word is 45 for the 16K code and 180 for the 64K code.
- the usable codes corresponding to these two block lengths (code word lengths) are listed in Table A.1 of ETSI EN 302 755, which is a DVB-T2 standard. 1 to Table A. 6 listed.
- the bit interleaver is used only for constellations larger than QPSK and comprises a parity interleaver 822, a column-row interleaver 823 and a bit-cell demultiplexer 824. Note that, in the definition of the DVB-T2 standard, the bit-cell demultiplexer 824 is not included in the bit interleaver. However, since the present invention relates to interleaving applied to an LDPC code before constellation mapping, the bit-cell demultiplexer 824 is also treated as part of bit interleaving.
- the parity interleaver 822 performs parity permutation to change the order of parity bits of the codeword in order to clarify the pseudo-cyclic structure of parity bits.
- the column-row interleaver 823 works conceptually by writing the bits of the LDPC codeword along the columns of the interleaver matrix and reading them along the rows. The first bit contained in the LDPC code word is written first and read first. The column-row interleaver 823 shifts the bits cyclically by a predetermined number of positions with respect to the column after writing the bits of the LDPC code word and before starting reading the bits. This is called column twisting in the DVB-T2 standard. The number of columns Nc and the number of rows Nr of the interleaver matrix corresponding to the above two LDPC codeword lengths and various constellation sizes are shown in Table 1 below.
- the number of columns Nc is twice the number of bits of one constellation, except in the case of a 16K code in a 256 QAM constellation.
- the reason for this exception is that the LDPC codeword length of 16200 is not a multiple of 16, ie twice the number of bits in the 256 QAM constellation.
- bit-cell demultiplexer 824 demultiplexes each LDPC codeword to obtain multiple parallel bit streams.
- the number of streams is twice that of the number M of bits encoded in one QAM constellation, ie 2 ⁇ M, except in the case of a 16K LDPC code in a 256 QAM constellation.
- the number of streams is M, the number of bits encoded in one QAM constellation.
- M bits encoded in one constellation are referred to as cell words (or constellation words). As described below, in a 16K LDPC code, the number of cell words obtained from one code word is 16200 / M.
- the bit-cell demultiplexer comprises a simple demultiplexer 1110 (1210, 1310) and a demultiplexing permutation unit 1120 (1220, 1320), as shown in FIG. 11 (FIGS. 12, 13).
- bit-cell demultiplexer in addition to simply demultiplexing the interleaved LDPC codeword by the simple demultiplexer 1110 (1210, 1310), by the demultiplexing unit 1120 (1220, 1220) Permutation processing is performed on the demultiplexed parallel bit stream to change its order.
- bit interleaver used in the DVB-T2 standard comes with two problems.
- the first problem is that parallelism is lost when the number of cyclic blocks in an LDPC codeword is not a multiple of the number of columns of the bit interleaver matrix. Latency increases as parallelism decreases. This is particularly a problem when iterative BICM decoding is used at the receiver. This situation occurs with some of the combinations of LDPC codeword length and constellation size for the DVB-T2 standard.
- FIGS. 14 and 15 are diagrams showing the above-mentioned situation which occurs when the number of columns of the interleaver matrix is 8 and 12, respectively, in the 16K LDPC code.
- 16 QAM and 256 QAM constellations an 8-row interleaver matrix is used.
- 64 QAM constellation a 12-column interleaver matrix is used.
- a grid represents an LDPC code word
- a small square represents one bit of the LDPC code word
- a row corresponds to a cyclic block
- a column corresponds to a bit having the same bit index as each other in a plurality of cyclic blocks.
- Filled squares represent 8 bits and 12 bits in the first row of the interleaver matrix.
- the second problem is that in the DVB-T2 standard, the number of possible bit interleaver configurations is limited by the number of columns of the bit interleaver matrix.
- FIGS. 16 and 17 show the same situation as in FIGS. 14 and 15, respectively, except that column twist processing is applied.
- the column twist value for each column used in the DVB-T 2-bit interleaver is (0, 0, 0, 1, 7, 20, 20, 21).
- the column twist value for each column used in the DVB-T 2-bit interleaver is (0, 0, 0, 2, 2, 2, 3, 3, 3, 6, 7, 7).
- Embodiment (Part 1) ⁇ Embodiment (Part 1) >>
- bit interleaver parallel bit interleaver
- the same reference numerals are given to constituent units that perform substantially the same processing content and the same processing content.
- each of a group of M cyclic blocks or each of a group of Q constellation words is called a section (or an interleaver section).
- It is a block diagram which shows one structural example of a figure and the said bit interleaver.
- the section permutation units (2021, 2022, 2023) are independent of each other (independently of each other), and each of eight constellation words (C1 to C8, C9 to C16, C17 to C24) is 4 Section per order to change the order of a total of 32 bits of 4 cyclic blocks so that 1 bit is mapped from each of 2 cyclic blocks (QB1 to QB4, QB5 to QB8, QB9 to QB12) Perform a mutation process.
- the two conditions 1 and 2 described above are merely to ensure that the bit interleaver is divided into N / M parallel sections.
- the same permutation rule may be applied to the section permutation processing applied to these parallel sections, or different permutation rules may be applied, or only some of them may be identical to each other. Mutation rules may be applied.
- the section permutation unit maps Q bits of a cyclic block (equal in importance in the LDPC decoding process) to bits of the same bit index of Q constellation words (robust levels are equal to one another). You may do it.
- the Q bits can be arranged sequentially or in permutation order. The latter will be described using FIGS. 21 (a) and 21 (b) and the former using FIGS. 22 (a) and 22 (b).
- FIG. 21A shows an example of the configuration of the section permutation unit shown in FIG.
- Section permutation unit 2101 includes intra-cyclic block permutation units 2111-2114 and column-row permutation unit 2131. It should be noted that instead of providing four intra-cyclic block permutation units, for example, four intra-cyclic block permutations to be described later while switching processing targets in time series using one intra-cyclic block permutation unit. Processing may be performed.
- the intra-cyclic block permutation unit (2111 to 2114) performs intra-cyclic block permutation processing for changing the order of the Q (8) bits of the cyclic blocks (QB1 to QB4).
- the same permutation rule may be applied to the intra-cyclic block permutation processing applied to cyclic blocks in one section, or different permutation rules may be applied. Only part of the permutation rules may be applied to each other.
- the column-row permutation unit 2131 performs column-row permutation processing to change the order of M ⁇ Q (32) bits. Specifically, the column-row permutation unit 2131 writes M ⁇ Q (32 bits) in the row direction of a matrix of Q columns and M rows (8 columns and 4 rows), and writes M ⁇ Q pieces Column-row permutation processing equivalent to reading (32) bits in the column direction is performed. In the column-row permutation processing by the column-row permutation unit 2131, the 12th row 1350 rows in FIGS. 9A and 9B are replaced with the Q row M row, and the write processing is from the column direction to the row direction In addition, the reading process is changed from the row direction to the column direction.
- FIG. 21 (b) is a view showing the function of mapping by the section permutation unit of FIG. 21 (a).
- M 4 bits of each constellation word are indicated by b1 to b4.
- intra-cyclic block permutation processing may not be performed in the section permutation processing.
- FIG. 22 (b) Another example of the section permutation in FIG. 20, one configuration example of the section permutation unit not carrying out the intra-cyclic block permutation processing and the function of the mapping by this section permutation unit are shown in FIG. And FIG. 22 (b).
- the section permutation unit 2201 has a column-row permutation unit 2131 and performs only column-row permutation processing.
- M 4 bits of each constellation word are indicated by b1 to b4.
- section permutation described in FIGS. 21 and 22 may be performed on cyclic blocks QB5 to QB8 and QB9 to QB12.
- the bit interleaver additionally performs cyclic block permutation processing to rearrange the order of N cyclic blocks before performing section permutation processing.
- One configuration example of a bit interleaver that additionally performs cyclic block permutation processing is shown in FIG.
- the cyclic block permutation here plays the same role as the permutation by the bit-cell demultiplexer in the DVB-T2 standard.
- the bit interleaver 2300 shown in FIG. 23 includes a cyclic block permutation unit 2310 and a bit permutation unit 2010 (including section permutation units 2021 to 2023).
- the cyclic block permutation unit 2310 performs cyclic block permutation processing 2311 to 2318 for changing the order of the cyclic blocks QB1 to QB12. Note that permutation rules used in cyclic block permutation processing 2311 to 2318 are the same as one another.
- Cyclic block permutation applied to N cyclic blocks is particularly useful because it enables optimal mapping of bits of an LDPC codeword to bits of a constellation, leading to optimization of reception performance. is there.
- FIG. 24 is a block diagram showing one configuration example of the bit interleaver of FIG.
- the bit interleaver 2400 of FIG. 24 performs the following three permutation processes of stages A, B and C.
- Stage A cyclic block (inter) permutation
- Stage B intra-cyclic block permutation
- Stage C column-row permutation
- the cyclic block (inter) permutation is N cycles constituting a codeword Permutation to change the order of blocks
- in-block permutation is permutation to change the order of Q bits that make up a cyclic block
- column-row permutation forms sections It is a permutation that changes the order of M ⁇ Q bits to be processed.
- the bit interleaver 2400 shown in FIG. 24 includes a cyclic block permutation unit 2310 and a bit permutation unit 2010 (section permutation units 2101 to 2103).
- the section permutation unit 2101 (2102, 2103) includes intra-cyclic block permutation units 2111 to 2114 (2115 to 2118, 2119 to 2122) and column-row permutation units 2131 (2132, 2133).
- the bit interleaver 2400 performs cyclic block (interleave) permutation by the cyclic block permutation unit 2310 (stage A), and performs intra cyclic block permutation by the intra cyclic block permutation units 2111 to 2122 (stage B) Column-row permutation is performed by column-row permutation units 2131 to 2133) (stage C).
- the intra-cyclic block permutation units 2111 to 2122 may be removed from the bit interleaver shown in FIG. 24 so that the intra-cyclic block permutation is not performed. Also, the bit interleaver may perform intra-cyclic block permutations before cyclic block (inter) block permutations instead of performing after cyclic block (inter-block) permutations; Between) may be performed before and after the permutation.
- the plurality of intra-cyclic block permutation units may have the same configuration. Therefore, a plurality of intra-cyclic block permutation units can be implemented by the same functional resource (such as a hardware block). Also, the plurality of intra-cyclic block permutations may consist of cyclic shift processing, in which case efficient hardware implementation using a barrel shifter is possible. It is also possible to implement using the barrel shifter used for the LDPC decoder.
- FIG. 25 is a block diagram showing an exemplary configuration of a transmitter according to still another embodiment of the present invention.
- the transmitter 2500 shown in FIG. 25 includes a BICM encoder (including an LDPC encoder 2510, a bit interleaver 2520, and a constellation mapper 2530) and a modulator 2540.
- the LDPC encoder 2510 encodes the input block into a codeword using a QC-LDPC code, and outputs the codeword to the bit interleaver 2520.
- bit interleaver 2520 additionally performs cyclic block permutation processing described, for example, in FIGS. 23 to 24 or as a modification thereof in addition to bit permutation processing as bit interleaving processing. May be
- Constellation mapper 2530 receives a constellation word from bit interleaver 2520 and performs constellation mapping processing on the received constellation word.
- the modulator 2740 performs orthogonal frequency division multiplexing (OFDM) modulation or the like to generate a transmission signal.
- OFDM orthogonal frequency division multiplexing
- FIG. 26 is a block diagram showing an implementation example of a BICM encoder according to still another embodiment of the present invention.
- the BICM encoder 2600 shown in FIG. 26 includes a main memory 2601, an LDPC controller 2611, a rotator 2612, a check node processor group 2613, a derotator 2614, a QB counter 2631, a table 2632, an interleaver 2633, a register group 2634, an interleaver 2635, and a mapper.
- a group 2651 is provided.
- the main memory 2601 receives a bit string to be transmitted, for example, from an input processing unit (not shown), and holds the received bit string.
- the LDPC controller 2611 outputs a read address to the main memory 2601, whereby the main memory 2601 outputs eight bits from the beginning of the bit string to the rotator 2612.
- the rotator 2612 cyclically shifts the predetermined number of 8 bits supplied from the main memory 2601 under the control of the LDPC controller 2611, and shifts the eight bits after cyclic shift to each check node processor of the check node processor group 2613. Output bit by bit.
- Each check node processor of each check node processor group 2613 performs check node processing on the input 1 bit under the control of the LDPC controller 2611, and outputs the 1 bit processing result to the derotator 2614.
- Derotator 2614 cyclically shifts the eight bits received from check node processor group 2613 a predetermined number so as to cancel the cyclic shift by rotator 2612 under the control of LDPC controller 2611, and sends the eight bits after cyclic shift to main memory 2601. Output.
- the LDPC controller 2611 outputs a write address to the main memory 2601, whereby the main memory 2601 holds 8 bits supplied from the derotator 2614.
- the LDPC controller 2611, the rotator 2612, the check node processor group 2613, and the derotator 2614 constitute an LDPC encoder 2510 of the BICM encoder in FIG.
- the QB counter 2631 counts from 0 to 11, and outputs the counter value to the table 2632.
- the read address is output.
- the main memory 2601 outputs, to the interleaver 2633, bits for one cyclic block corresponding to the counter value of the QB counter 2631.
- the cyclic block permutation (stage A) is realized by the processing of this table 2632.
- the interleaver 2633 cyclically shifts the bits for one cyclic block supplied from the main memory 2601 by a predetermined number and outputs the result to the first stage register of the register group 2634.
- intra-cyclic block permutation stage B is realized by the processing of the interleaver 2633.
- each register of the register group 2634 holds the bits for one cyclic block at the timing when the control pulse is received, and continues to output the held bits for one cyclic block until the control pulse is next received.
- the bits (32 bits) for 4 cyclic blocks are input to the interleaver 2635.
- M 4 bits
- the QB counter 2631, the table 2632, the interleaver 2633, the register group 2634, and the interleaver 2635 constitute a bit interleaver 2520 of the BICM encoder in FIG.
- mapper group 2651 maps the 4 bits supplied from the interleaver 2635 into a constellation, and outputs the mapping result.
- mapper group 2651 constitutes constellation mapper 2530 of the BICM encoder in FIG.
- the above series of processing is performed three times for one code word, in total, from the counter values “0” to “3”, “4” to “7”, and “8” to “11” of the QB counter 2631.
- FIG. 26 includes Q mappers operating in parallel
- Q mappers operating in parallel
- the parallelism can be easily increased by increasing the number of parallel interleaver sections in the bit interleaver, ie N / M.
- parallelization can be maximized by parallelizing Q ⁇ N / M mappers.
- Bit interleavers have the advantage that such parallelism can be realized without any obstacles.
- FIG. 27 is a block diagram showing an example configuration of a receiver having a non-iterative BICM decoder according to still another embodiment of the present invention. The receiver operates in reverse to the transmitter.
- the receiver 2700 shown in FIG. 27 comprises a modulator 2710 and a non-iterative BICM decoder (including constellation demapper 2720 and bit deinterleaver 2730, LDPC decoder 2740).
- the demodulator 2710 performs demodulation processing using OFDM or the like, and outputs the demodulation processing result.
- Constellation demapper 2720 of the non-repetitive BICM decoder demaps the input from modulator 2710 to generate a so-called soft bit string, and outputs the generated soft bit string to constellation demapper 2730.
- Each soft bit is a measure of the probability that each bit will be 0 or 1.
- soft bits are represented by log likelihood ratios (LLRs) and defined as follows.
- the bit deinterleaver 2730 interleaves the soft bit sequence output from the constellation demapper 2720 by the bit interleaver in the transmitter of FIG. (Bit de-interleaving processing) is performed.
- the LDPC decoder 2740 receives the soft bit sequence subjected to bit deinterleaving from the bit deinterleaver 2730, and performs an LDPC decoding process using the received soft bit sequence.
- FIG. 28 is a block diagram showing an example of configuration of a receiver having an iterative BICM decoder according to still another embodiment of the present invention. The receiver operates in reverse to the transmitter.
- the receiver 2800 shown in FIG. 28 includes a modulator 2710 and an iterative BICM decoder (constellation demapper 2720, bit deinterleaver 2730, LDPC decoder 2740, subtraction unit 2760, bit interleaver 2750).
- BICM decoder castellation demapper 2720, bit deinterleaver 2730, LDPC decoder 2740, subtraction unit 2760, bit interleaver 2750.
- the receiver 2800 in FIG. 28 performs constellation demapping processing by the constellation demapper 2720, bit deinterleaving processing by the bit deinterleaving 2730, and LDPC decoding processing by the LDPC decoder 2740.
- a subtraction unit 2760 subtracts the input of the LDPC decoder 2740 from the output of the LDPC decoder 2740, and extrinsic information obtained as a result of the subtraction is bit interleaver Output to 2750.
- the bit interleaver 2750 performs interleaving on the external information in the same interleaving rule as the bit interleaving performed on the bit sequence by the bit interleaver in the transmitter of FIG. Then, bit interleaver 2750 feeds back the interleaved external information to constellation demapper 2720. Constellation demapper 2720 uses the fed-back external information as a-priori information to calculate a more reliable LLR value.
- bit deinterleaver 2730 cancels the bit interleaving processing applied to the bit string by the bit interleaver in the transmitter of FIG. 25 to the newly calculated LLR value and restores the original order (bit deinterleaver Interleave processing).
- the LDPC decoder 2740 performs an LDPC decoding process using the LLR value subjected to the bit deinterleaving process.
- the iterative decoding loop consists of four elements: constellation demapper 2720, bit deinterleaver 2730, LDPC decoder 2740, and bit interleaver 2750.
- the bit deinterleaver 2730 and the bit interleaver 2750 have very low latency, ideally zero, and a simple configuration allows efficient implementation of the receiver.
- the above-described bit deinterleaver 2730 and bit interleaver 2750 satisfy both conditions.
- FIG. 1 One implementation of the iterative BICM decoder that implements a very efficient parallel implementation is described using FIG.
- FIG. 29 is a block diagram showing an implementation example of a BICM decoder according to still another embodiment of the present invention.
- the BICM decoder 2900 shown in FIG. 29 includes a main LLR memory 2901, a buffer LLR memory 2902, an LDPC controller 2911, a rotator 2912, a check node processor group 2913, a derotator 2914, a QB counter 2931, a table 2932, a subtraction unit 2933, an interleaver 2934, A register group 2935, an interleaver 2936, a demapper group 2937, a deinterleaver 2938, a register group 2939, a deinterleaver 2940, and a delay unit 2941 are provided.
- demapper of the demapper group 2937 performs demapping processing using the output of the demodulator (not shown), and outputs the LLR value obtained thereby to the deinterleaver 2938.
- demapper group 2937 constitutes constellation demapper 2720 of the iterative BICM decoder in FIG.
- the deinterleaver 2938 performs deinterleaving processing (interleaving processing to cancel interleaving by the stage C by the transmitter) on the LLR value, and outputs the LLR value after deinterleaving to each register of the register group 2939.
- LLR values (eight LLR values) for one circulating block are stored in each of the registers.
- the LLR values for one cyclic block held in the registers are sequentially output to the subsequent stage, and the held contents of the respective registers are sequentially updated.
- the deinterleaver 2940 performs interleaving processing (interleaving processing to cancel interleaving by the stage B by the transmitter) on the LLR values (eight LLR values) for one cyclic block to be supplied, and stores the contents of the table 2932 ( The main LLR memory 2901 and the buffer LLR memory 2902 are written according to the following description). Note that, by writing to the main LLR memory 2901 and the buffer LLR memory 2902 in accordance with the contents held in the table 2932, interleaving processing to cancel interleaving by the stage A by the transmitter is realized.
- the main LLR memory 2901 stores the LLR value after the de-interleaving process, and is also used by the LDPC decoder (LDPC controller 2911, rotator 2912, check node processor group 2913, derotator 2914).
- the LDPC decoding process is an iterative process consisting of one or more iterations. At each iteration of the LDPC decoding process, the LLR values in the main LLR memory 2901 are updated. The old LLR values are held in the buffer LLR memory 2902 to calculate the extrinsic information needed for the iterative BICM decoding process.
- the LDPC controller 2911 outputs the read address to the main LLR memory 2901 according to the parity check matrix of the LDPC code, whereby the main LLR memory 2901 sequentially outputs LLR values to the rotator 2912 for each one of the cyclic blocks.
- the rotator 2912 cyclically shifts the LLR values for one cyclic block sequentially supplied from the main LLR memory 2901 by a predetermined number under the control of the LDPC controller 2911, and the LLR values after cyclic shift are of the check node processor group 2913. Output one by one to each check node processor.
- Each check node processor of each check node processor group 2913 performs check node processing on a series of LLR values sequentially input under control of the LDPC controller 2911.
- each check node processor of the check node processor group 2913 receives control of the LDPC controller 2911 and sequentially outputs a series of LLR values as a result of check node processing.
- the derotator 2914 cyclically shifts the processing result for one cyclic block sequentially received from the check node processor group 2913 by a predetermined number so as to cancel the cyclic shift by the rotator 2912 under the control of the LDPC controller 2911 and cyclic shift
- the processing results are sequentially output to the main LLR memory 2901.
- the LDPC controller 2911 outputs a write address to the main LLR memory 2901 according to the parity check matrix of the LDPC code, whereby the main LLR memory 2901 holds the processing result for one cyclic block sequentially supplied from the derotator 2914. .
- the LDPC controller 2911 repeatedly executes the above processing in accordance with the parity check matrix of the LDPC code.
- BICM iterations are performed.
- LDPC and BICM iterative processes are also referred to as internal and external iterative processes, respectively.
- the BICM and LDPC decoding processes are well known in the art and will not be described in detail.
- the QB counter 2931 counts from 0 to 11, and outputs the counter value to the table 2932.
- the main LLR memory 2901 is supplied so that LLR values for one cyclic block corresponding to the counter value supplied from the QB counter 2931 are supplied from the main LLR memory 2901 and the buffer LLR memory 2902 to the subtraction unit group 2933. And outputs the read address to the buffer LLR memory 2902.
- main LLR memory 2901 and buffer LLR memory 2902 each output LLR values for one cyclic block corresponding to the counter value of QB counter 2931 to subtraction unit 2934.
- the delay position by the delay unit 2941 is set so that the reading position of the LLR value from the main LLR memory 2901 and the buffer LLR memory 2902 and the writing position of the LLR value to the main LLR memory 2901 and the buffer LLR memory 2902 coincide with each other. Adjustments will be made. Note that the permutation corresponding to the cyclic block permutation (stage A) is realized by the processing of the table 2932.
- Each subtraction unit 2933 of the subtraction unit group subtracts the output of the buffer LLR memory 2902 from the output of the main LLR memory 2901 and obtains external information (eight external information) for one cyclic block obtained as a result of subtraction. Output to interleaver 2934.
- the interleaver 2934 cyclically shifts the external information for one cyclic block supplied from the subtraction unit 2933 by a predetermined number and outputs the information to the first stage register of the register group 2935.
- the processing corresponding to the intra-cyclic block permutation (stage B) is realized by the processing of the interleaver 2934.
- each register of the register group 2935 receives a control pulse and holds 8 bits, and keeps holding the held 8 bits until the next control pulse is received.
- the interleaver 2936 receives external information (32 external information) for 4 cyclic blocks. .
- M 4 for each demapper of the demapper group 2937
- the QB counter 2931, the table 2932, the interleaver 2934, the register group 2935, and the interleaver 2936 constitute a bit interleaver 2750 of the BICM decoder in FIG.
- Each demapper of the demapper group 2937 performs demapping processing using the four pieces of external information supplied from the interleaver 2936 as prior information, and outputs a new LLR value to the deinterleaver 2938.
- the deinterleaver 2938 performs deinterleaving processing (interleaving processing to cancel interleaving by the stage C by the transmitter) on the LLR value, and outputs the LLR value after deinterleaving to each register of the register group 2939.
- LLR values (eight LLR values) for one circulating block are stored in each of the registers.
- the LLR values for one cyclic block held in the registers are sequentially output to the subsequent stage, and the held contents of the respective registers are sequentially updated.
- the deinterleaver 2940 performs deinterleaving processing (interleaving processing to cancel interleaving by the stage B by the transmitter) on the LLR values (eight LLR values) for one cyclic block to be supplied, and the main LLR memory 2901 and Output to buffer LLR memory 2902.
- the main LLR memory 2901 and the buffer LLR memory 2902 receive the write address from the table 2932 via the delay unit 2941, and according to the received write address, the LLR values for one cyclic block received from the deinterleaver 2940 (eight Hold LLR value).
- the write processing according to the table 2932 realizes interleaving processing (de-interleaving processing) that cancels interleaving by the stage A by the transmitter.
- the above series of processing is performed three times for one code word, in total, from the counter values “0” to “3”, “4” to “7”, and “8” to “11” of the QB counter 2931.
- the QB counter 2931, the table 2932, the deinterleaver 2938, the register group 2939, and the deinterleaver 2940 constitute a bit deinterleaver 2730 of the BICM decoder in FIG. 28.
- Interleaver 2934 and de-interleaver 2940 are reconfigurable and have a constant hardware cost, but the cost can be minimized by careful design.
- Interleaver 2936 and de-interleaver 2938 implement column-row permutation, which is constant for a given constellation size. Therefore, the implementation cost is small.
- FIG. 29 includes Q demappers operating in parallel
- the parallelism can be easily increased by increasing the number of parallel interleaver sections in the bit interleaver, ie N / M.
- parallelization can be maximized by parallelizing Q ⁇ N / M demappers.
- the bit interleaver described above has the advantage that such parallelism can be realized without any obstacles.
- the bit interleaver selects N ′ cyclic blocks that are multiples of the number M of bits of the constellation word among the N cyclic blocks.
- the bit interleaver divides the selected N ′ cyclic blocks into N ′ / M sections so that each includes M cyclic blocks, and performs section permutation on each section.
- the bits of the excluded (not selected) cyclic block may not be interleaved or may be interleaved.
- a bit interleaving method is a bit interleaving method in a communication system using a pseudo-cyclic low density parity check code, and the bit interleaving method includes N cycles each consisting of Q bits.
- a receiving step of receiving a codeword of the pseudo-cyclic low density parity check code composed of blocks, and a bit permutation process of performing bit permutation processing of changing the order of bits of the codeword to the bits of the codeword A plurality of constellations, each of which consists of M bits, each of which represents one of 2 M predetermined constellation points, each of which has been subjected to a mutation step and the bit permutation process.
- Dividing into words, and N cyclic blocks A selection step of selecting a subset of N 'cyclic blocks which is a multiple of M (M is the number of bits per constellation word) from among the bits, and the bit permutation process is performed
- M is the number of bits per constellation word
- the previous codeword is divided into N '/ M sections, each said section consists of M said cyclic blocks, and each said constellation word is one of said N' / M sections
- the bit permutation step is associated with each of the constellation words from a total of M bits consisting of one bit of each of the M different cyclic blocks in the associated section. Configured, and only to the Q constellation words associated with the section, all bits of each said section The bit permutation process is performed to be mapped.
- a bit interleaver is a bit interleaver in a communication system using a pseudo-cyclic low density parity check code, wherein the bit interleaver is configured to generate N cyclic circuits each consisting of Q bits.
- a codeword of the pseudo cyclic low density parity check code composed of blocks is received, and bit permutation processing is performed on the bits of the codeword to change the order of bits of the codeword, and the bit permutation is performed.
- Output the codeword subjected to the notation processing so as to be divided into a plurality of constellation words, each of which consists of M bits, each of which represents any one of 2 M predetermined constellation points.
- each of the constellation words is composed of a total of M bits consisting of one bit of each of the M different cyclic blocks in the associated section, and The bit pass so that all bits are mapped only to the Q constellation words associated with the section.
- -It is characterized by performing a mutation process.
- the bits of the code word are not included in the subset of the selected N ′ cyclic blocks, and a group of bits to be left as targets for changing the order of bits, or the selected N It does not matter if it includes a group of bits which are targets of changing the order of bits independent of the bit permutation process, which is applied only to the cyclic blocks which are not included in the cyclic block and not selected. .
- the excluded cyclic block may be the one with the smallest variable node weight.
- the excluded cyclic block may be a cyclic block of the parity part (having a variable node of weight 2), in this case, for example, from the end of the codeword It may be one or more cyclic blocks.
- the selecting step may select the cyclic block based on the degree of importance of bits included in each cyclic block.
- the importance of the bits included in each cyclic block may be determined based on the number of associated parity bits.
- the code word may be a repeat accumulated pseudo cyclic low density parity check code, and the non-selected cyclic block may correspond to a parity section of the code word.
- the selected subset of N ′ cyclic blocks may be configured by N ′ blocks that are continuous from the cyclic block having the first bit of the codeword.
- FIG. 30 is a diagram illustrating a cyclic block to which the interleaving method described in the embodiment is applied (the cyclic block to be excluded) and a cyclic block to which the interleaving method is applied is not applied.
- FIG. 30 is a diagram for the case where the code is a 16K LDPC code defined in the DVB-T2 standard and the constellation is a 16 QAM constellation. In the example of FIG.
- the cyclic block to be applied is 44 cyclic blocks (1,..., 44), and the cyclic blocks not to be applied (cyclic blocks to be excluded) are one in the last row. This is only the cyclic block 45. Also, four black squares represent four bits of the first constellation word.
- the number of interleaver sections is floor (N / M), and the number of cyclic blocks excluded is rem (N, M).
- floor (N / M) is a function that returns the largest integer value of N / M or less
- rem (N, M) is a function that returns a remainder value obtained by dividing N by M.
- each constellation word is mapped to M cyclic blocks.
- a very large number of delay registers are required (FIGS. 26 and 29). See the implementation example described in The use of very large delay registers leads to increased circuit area and power consumption.
- reducing the number of cyclic blocks to which the constellation word is mapped is beneficial to increase the overlap between the outer (BICM) and inner (LDPC) iterations, and the overall BICM Reduce decoding latency.
- the number of cyclic blocks to which the constellation word is mapped can be reduced.
- the number of bits of the constellation word mapped to the same cyclic block is referred to as a folding coefficient and denoted as F.
- F the folding coefficient
- the constellation word is mapped to only 2 cyclic blocks instead of 4 cyclic blocks.
- Complex QAM constellation symbols can be separated into two equal real pulse-amplitude modulation (PAM) symbols.
- PAM pulse-amplitude modulation
- the M bits of the QAM constellation can be divided into a set of M / 2 bits of two equal real PAM symbols, and the bits of the constellation word can be mapped to the same M / 2 cyclic blocks .
- the folding factor where F 2 is a useful value for QAM constellations.
- Folding has the added benefit of reducing the number of excluded cyclic blocks or zeroing out the number of excluded cyclic blocks.
- the inventor has found that it is necessary to change the conditions 1 and 2 to the following conditions 1A and 2A in order to perform folding (F is an integer of 2 or more).
- F 1 means no folding, and conditions 1A and 2A are the same as conditions 1 and 2.
- each of a group of M / F cyclic blocks or each of a group of Q / F constellation words is referred to as a folding section (or a folding interleaver section).
- the folding interleaver section matches the interleaver section, and the bit interleaver has the same configuration as the bit interleaver of the embodiment (part 1).
- the folding section permutation units (2021A, 2022A, 2023A, 2024A, 2025A, 2026A) are independent of one another (independently of one another) and four constellation words (C1-C4, C5-C8, C9).
- M / F 2 cyclic blocks (QB1 to QB2, QB3 to QB4, QB5 to QB6, QB7 to QB8, QB9 to QB10, QB11) for each of C12 to C12, C13 to C16, C17 to C20, and C21 to C24).
- the above two conditions 1A and 2A are merely to ensure that the bit interleaver is divided into F ⁇ N / M parallel folding sections.
- the same permutation rules may be applied to the folding section permutation processing applied to these parallel folding sections, or different permutation rules may be applied, or only some of them may be applied.
- the same permutation rules may be applied to each other.
- the constellation is a 16 QAM constellation. Therefore, there are two robust levels in the bits of the constellation, and the bits b1 and b3 are the same robust level, and the bits b2 and b4 are the same robust level.
- the folding section permutation unit 2201A (2202A) has a column-row permutation unit 2131A (2132A).
- folding of the folding coefficient F reduces the number of cyclic blocks mapped to one constellation word. This reduces the number of matrix rows in column-row permutation from M to M / F.
- FIG.33 (a) is a figure which shows the function of the mapping by the (folding) section permutation unit of Fig.34 (a)
- FIG.33 (b) is two folding sections of FIG.34 (a). It is a figure which shows the function of the mapping by a permutation unit.
- M 4 bits of each constellation word are indicated by b1 to b4.
- the portions surrounded by thick lines represent the mapping for the constellation word C1.
- eight bits (having the same importance) of one cyclic block are bits having the same bit index of eight constellation words (having the same robustness level). Is mapped to). Also, in the example of FIGS. 33 (b) and 34 (b), 8 bits (having the same importance) of one cyclic block are mapped to bits of the same robust level of 4 constellation words. .
- folding section permutation described in FIG. 34B may be performed on the cyclic blocks QB5 to QB6, QB7 to QB8, QB9 to QB10, and QB11 to QB12.
- the bit interleaver performs cyclic block permutation processing to additionally change the order of N cyclic blocks before performing folding section permutation processing. I do.
- An exemplary configuration of a bit interleaver that additionally performs cyclic block permutation processing is shown in FIG.
- the bit interleaver 2300A shown in FIG. 35 includes a cyclic block permutation unit 2310 and a bit permutation unit 2010A (including folding section permutation units 2021A to 2026A).
- FIG. 36 is a block diagram showing a configuration example of the bit interleaver of FIG.
- Bit interleaver 2400A in FIG. 36 includes cyclic block permutation unit 2310 and bit permutation unit 2200A (including folding section permutation units 2201A to 2206A).
- the folding section permutation units 2201A to 2206A respectively include column-row permutation units 2131A to 2136A.
- the column-row permutation units 2133A to 2136A perform substantially the same permutation processing as the column-row permutation units 2133A to 2132A.
- a unit performing permutation in a cyclic block to change the order of bits in cyclic blocks QB1 to QB12 is added to the previous or subsequent stage of cyclic block permutation. May be
- FIG. 37 is a block diagram showing an exemplary configuration of a transmitter according to still another embodiment of the present invention.
- Transmitter 2500A shown in FIG. 37 has a configuration in which bit interleaver 2520 of transmitter 2500 in FIG. 25 is replaced with bit interleaver 2520A.
- FIG. 38 is a block diagram showing an example of configuration of a receiver having a non-iterative BICM decoder according to still another embodiment of the present invention.
- the receiver operates in reverse to the transmitter.
- Receiver 2700A shown in FIG. 38 has a configuration in which bit deinterleaver 2730 of receiver 2700 in FIG. 27 is replaced with bit deinterleaver 2730A.
- the bit deinterleaver 2730A cancels the bit interleaving processing applied to the bit string by the bit interleaver 2520A in the transmitter 2500A to the soft bit string output from the constellation demapper 2720 to restore the original assortment ( Perform bit de-interleaving processing).
- FIG. 39 is a block diagram showing an example of configuration of a receiver having a non-iterative BICM decoder according to still another embodiment of the present invention.
- the receiver operates in reverse to the transmitter.
- Receiver 2800A shown in FIG. 39 has a configuration in which bit deinterleaver 2730 and bit interleaver 2750 of receiver 2800 in FIG. 28 are replaced with bit deinterleaver 2730A and bit deinterleaver 2750A.
- Bit interleaver 2750A performs interleaving on the external information (extrinsic information) in the same interleaving rule as bit interleaving performed on bit strings by bit interleaver 2520A in transmitter 2500A.
- folding may be such that bits of one constellation word are placed in fewer LLR memory locations.
- the LLR memory in the decoder has G ⁇ N addressable locations, each location being capable of holding Q / G LLR values.
- G is an implementation parameter that is a divisor of Q and is referred to as memory granularity.
- the number of LLR values in the memory location ie Q / G, needs to be a multiple of F, and the LLR values of each constellation are stored at the same location in all locations of memory. This ensures that LLR values in any constellation word are stored in M / F memory locations.
- the LLR values of the second and fifth constellation words are held in four memory locations instead of two memory locations.
- folding is very useful when two or more constellation symbols are jointly decoded.
- Joint decoding is required, for example, for maximum likelihood decoding of block codes (space-time codes, frequency-space codes, etc.) or rotational constellations of two or more dimensions.
- a block code encodes two or more input symbols (x 1 ,..., X K ) into two or more output symbols (y 1 ,..., Y L ).
- L is less than or equal to K.
- the block code is modeled by an L-by-K generator matrix.
- the elements of the input signal vector X and the output signal vector Y can be real or complex numbers.
- the output signal vector Y may be transmitted in different time slots or different frequency slots, transmitted using different antennas, or transmitted using different time slots or different frequency slots and different antennas There is.
- Block codes for multiple-input multiple-output (MIMO) communication systems include Alamouti code, Golden code, and spatial multiplexing.
- the folding coefficients can be used up to K if K symbols are encoded in the same block. Furthermore, if the symbol is a QAM symbol (including two separable PAM symbols), the usable folding factor may be increased to 2 ⁇ K.
- the two constellations have different robustness levels from each other. For example, the cyclic block mapped to the bit of one constellation word and the cyclic block mapped to the bit of the other constellation word are made to be different from each other.
- a code space multiplexing MIMO system using two transmit antennas will be described as an example.
- X [x 1 x 2 ] be the complex signal before encoding.
- x 1 is a signal subjected to QPSK
- x 2 is a signal subjected to 16 QAM.
- y 1 and y 2 are signals transmitted by the first antenna and the second antenna, respectively.
- FIG. 41 shows only the first seven bits in the cyclic block.
- the two complex symbols x 1 and x 2 have the following structure:
- x 1 is a QPSK symbol given by the real part b 1 and the imaginary part b 2.
- x 2 is the real part is b3, b4, a 16QAM symbol imaginary part is given by b5, b6.
- the two symbols are jointly decoded at the receiver, thereby creating a so-called constellation block or a generated block.
- the entire 6-bit constellation block will have 3 robust levels.
- Level 1 b1 and b2 of QPSK are mapped to QB1.
- Level 2 16QAM b3 and b5 are mapped to QB2.
- Level 3 16QAM b4 and b6 are mapped to QB3.
- N cyclic groups are one or more groups of M1 cyclic blocks and M2 cyclic blocks. It divides into one or more groups which consist of, and performs bit interleaving processing.
- FIG. 42 is a diagram for the case where the code is a 16K LDPC code defined in the DVB-T2 standard and the constellation is a 16 QAM constellation.
- the cyclic block to be applied is 44 cyclic blocks (1,..., 44), and the cyclic blocks not to be applied (cyclic blocks to be excluded) are one in the last row. This is only the cyclic block 45.
- four black squares represent four bits of the first constellation word.
- FIG. 43 is a block diagram showing a configuration example of a bit interleaver in the case where folding is performed when N is not a multiple of M.
- the bit interleaver 4400A selects 44 cyclic blocks QB1 to QB44 out of the 45 cyclic blocks QB1 to QB45 and sets them as a subset.
- section 1 is composed of cyclic blocks QB1 to QB4
- section 11 is composed of cyclic blocks QB41 to QB44.
- the 11 section permutation units (4401,..., 4411) in the bit interleaver 4400A perform the permutation process described using FIG. 32 for each of the four cyclic blocks.
- the bit interleaver 4400B selects 44 cyclic blocks QB1 to QB44 out of the 45 cyclic blocks QB1 to QB45 and sets them as a subset.
- the subset is divided into 22 sections of sections 1 to 22 each consisting of 2 cyclic blocks.
- the 22 section permutation units (4421, 4422,..., 4442) in the bit interleaver 4400B perform the permutation processing described using FIG. 32 for each two cyclic blocks. .
- bits of cyclic block QB 45 are mapped to constellation words without being interleaved.
- the bit interleaver 4500A selects 42 cyclic blocks QB1 to QB42 out of the 45 cyclic blocks QB1 to QB45 as subsets.
- section 1 is composed of cyclic blocks QB1 to QB6, and section 7 is composed of cyclic blocks QB37 to QB42.
- the seven section permutation units (4501,..., 4507) in the bit interleaver 4500A perform the permutation process described using FIG. 32 for each of the six cyclic blocks.
- Cyclic blocks QB43 to QB45 are cyclic blocks not included in the subset.
- bits of the cyclic blocks QB43 and QB44 are mapped to constellation words without being interleaved.
- bits in cyclic block QB 45 are subjected to in-cyclic block permutation processing for changing the order of arrangement.
- bits of the cyclic blocks QB43 and QB44 are not included in the subset, and are left as targets for changing the order of bits.
- the bits of cyclic block QB45 are not included in the subset, but are separate from intra-cyclic block permutation units that are separate from section permutation units (4501, ..., 4507). By 4545, the order is changed.
- cyclic block QB45 is rearranged among the cyclic blocks QB43 to QB45, but permutation may be performed on all bits of the cyclic blocks QB43 to QB45. . Further, in the cyclic blocks QB43 to QB45, permutation in the cyclic block may be performed.
- Bit interleaver 4500 B selects all 45 cyclic blocks QB 1 to QB 45 and configures them as a subset.
- the subset is divided into 15 sections of sections 1-15, each consisting of 3 cyclic blocks.
- the 15 section permutation units (4511,..., 4526) in the bit interleaver 4500B perform the permutation process described using FIG. 32 for each of the three cyclic blocks.
- the values of the parameters N, M and Q and the value of the folding coefficient F are not limited to this.
- F may be a divisor of M and Q, respectively, and N may be a multiple of M / F.
- the value of F is described as “2”, which is the number of bits having the same robustness level of the 16 QAM constellation, but is not limited thereto.
- the value of F may be the number of bits having the same robust level of constellation, or the value of F may be other than the number of bits of the same robust level of constellation.
- the QAM constellation may be a QAM constellation other than a 16 QAM constellation (e.g., a 64 QAM constellation, a 256 QAM constellation), or the like.
- the method or apparatus described in each of the above embodiments may be realized by software or hardware, and is not limited to a specific form.
- the above embodiments have computer executable instructions on a computer readable medium such that a computer, microprocessor, microcontroller etc. can perform all the steps of the method and apparatus described in the above embodiments. It may be implemented in the form embodied in FIG. Also, the above embodiments may be implemented in the form of an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA).
- ASIC application-specific integrated circuit
- FPGA field programmable gate array
- a first bit interleaving method is a bit interleaving method in a communication system using a pseudo-cyclic low density parity check code, and the bit interleaving method includes N pieces of Q bits each.
- the code word of the pseudo cyclic low density parity check code which is composed of cyclic blocks, and a bit permutation process of changing the arrangement order of the bits of the code word with respect to the bits of the code word
- the bit permutation step and the codeword subjected to the bit permutation process are each composed of M bits, each of which indicates any one of 2 M predetermined constellation points.
- a first bit interleaver is a bit interleaver in a communication system using a pseudo-cyclic low density parity check code, said bit interleaver comprising N N bits each consisting of Q bits A codeword of the pseudo-cyclic low density parity check code composed of cyclic blocks, and performing bit permutation processing for changing the order of bits of the codeword to the bits of the codeword;
- the permutation-processed code word is divided into a plurality of constellation words, each of which consists of M bits, each of which indicates any one of 2 M predetermined constellation points.
- M / F (M is a constant) from the bit permutation unit to output and N cyclic blocks.
- the codeword is divided into F ⁇ N ′ / M folding sections, each folding section consists of M / F cyclic blocks, and each constellation word is the F ⁇ N.
- the bit permutation unit is associated with one of '/ M folding sections, and the bit permutation unit is configured to generate M / F different cyclic blocks in the section to which each of the constellation words is associated.
- M bits consisting of F bits of each of all the bits of each said section being associated with that section
- the Q as the mapped only to the constellation word that, and performs the bit permutation process.
- a second bit interleaving method is a method according to the first bit interleaving method, wherein the bits of the codeword are not included in the subset of the selected N ′ cyclic blocks, and the bit sequence is arranged.
- a third bit interleaving method is the first bit interleaving method, wherein the number N ′ of the selected cyclic blocks is M / F equal to a maximum integer multiple of F ⁇ N / M or less. It does not matter if it is a fixed number.
- a fourth bit interleaving method is the first bit interleaving method, wherein the selecting step selects the cyclic block based on the importance of bits included in each cyclic block. I do not care.
- a fifth bit interleaving method is as described in the fourth bit interleaving method, wherein the importance of bits included in each cyclic block is determined based on the number of associated parity bits. I do not care. .
- a sixth bit interleaving method which is an aspect of the present invention is the first bit interleaving method, wherein the codeword is a repeat accumulated pseudo cyclic low density parity check code, and the unselected cyclic block is , May correspond to the parity section of the code word.
- a selected subset of N ′ cyclic blocks is N consecutive from the cyclic block having the first bit of the codeword. It does not matter if it is composed of 'pieces of blocks.
- the eighth bit interleaving method is the first bit interleaving method according to the first aspect, wherein in the section permutation step, Q folding of the cyclic block corresponds to the cyclic block.
- the section permutation process may be performed so as to be mapped to the bits having the same bit index of the Q constellation words associated with the section.
- the bits having the same importance of the code word are mapped to the same bits of the robust level of the constellation word, and a match between the importance and the robustness level is obtained.
- the most significant bits of the code word may be mapped to the most robust bits of the constellation word, in which case there is a high confidence for the bits of high importance of the code word upon reception. Degree and high reception performance can be obtained.
- a first bit de-interleaving method is a de-interleaving method for de-interleaving bit streams in a communication system using a pseudo-cyclic low density parity check code, comprising: N ⁇ Q bit sequence And reverse bit permutation processing for changing the order of bits of the bit string received to the bits of the bit string received to restore the code word of the pseudo cyclic low density parity check code.
- the reverse bit permutation process is a process of restoring the order of arrangement changed in the bit permutation process in the bit interleaving method.
- a first bit deinterleaver which is an aspect of the present invention, is a deinterleaver that deinterleaves a bitstream in a communication system using a pseudo-cyclic low density parity check code, and is a bit string consisting of N ⁇ Q bits.
- Reverse bit permuting processing for reverse bit permutation processing for changing the order of bits of the received bit string to the bits of the received bit string in order to receive and restore the codeword of the pseudo cyclic low density parity check code
- the inverse bit permutation process is a process of restoring a sequence order changed in the bit permutation process performed by the bit interleaver.
- a first decoder which is an aspect of the present invention, is a decoder for a bit-interleaved coded modulation system using a pseudo-cyclic low density parity check code, and the probability that the corresponding bit is 0 or 1
- a constellation demapper for generating a soft bit sequence shown, a deinterleaver for deinterleaving the soft bit sequence, and a low density parity check decoder for decoding the deinterleaved soft bit sequence.
- a second decoder is a first decoder that subtracts the input of the low density parity check decoder from the output of the low density parity check decoder, and the subtraction result of the subtractor And the bit interleaver feeding back to the constellation demapper.
- the present invention can be applied to a bit interleaver in a bit interleaved coded modulation system using a pseudo-cyclic low density parity code and a bit deinterleaver corresponding to the bit interleaver.
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Abstract
Description
図1は、一般的なビットインターリーブ符号化変調(bit-interleaved coding and modulation:BICM)エンコーダを含むトランスミッタの構成を示すブロック図である。図1に示すトランスミッタ100は、入力プロセシングユニット110、BICMエンコーダ(低密度パリティチェック(low-density parity check:LDPC)エンコーダ120、ビットインターリーバ130、コンステレーションマッパ140を含む)、およびモジュレータ150を備える。
1つのLDPC符号語の巡回ブロック数:N=12
1つのコンステレーションのビット数:M=4、即ち16QAM
上記パラメータでは、1つのLDPC符号語がマッピングされるコンステレーション数はQ×N/M=24である。通常、パラメータQおよびNの選択は、システムがサポートする全てのコンステレーションについて、Q×NがMの倍数となるように行われなければならない。
16QAMの場合、4050セル
64QAMの場合、2700セル
256QAMの場合、2025セル
上記の表1によると、QPSKより大きなコンステレーションについては、並列ストリームの数はカラム‐ロウインターリーバの列数に等しい。16K LDPC符号について、16QAMコンステレーション、64QAMコンステレーション、256QAMコンステレーションに対応するビット‐セルデマルチプレクサを、それぞれ、図11、図12、図13に示す。なお、ビットの表記はDVB-T2規格で用いられているものである。
発明者は、鋭意研究を行った結果、以下の2つの条件が満たされるとき、非常に効率的なインターリーバが提供できるという知見を得た。
各コンステレーション語のM個のビットが、LDPC符号語のM個の異なる巡回ブロックにマッピングされる。これは、LDPC符号語のM個の異なる巡回ブロックから1ビットずつコンステレーション語にマッピングする、ことと等価である。この概要を図18(a)に示す。
M個の巡回ブロックにマッピングされるすべてのコンステレーション語が、当該M個の巡回ブロックのみにマッピングされる。これは、QビットからなるM個の異なる巡回ブロックのM×Q個のビットの全ては、Q個のコンステレーション語にのみマッピングされる、ことと等価である。この概要を図18(b)に示す。
以下、上記の条件1、条件2を満たすビットインターリーバ(並列ビットインターリーバ)の詳細について説明する。なお、以下において、実質的に同じ処理内容、および、同じ処理内容を行う構成ユニットには同じ符号を付す。
ステージB:巡回ブロック内パーミュテーション
ステージC:カラム‐ロウパーミュテーション
ここで、巡回ブロック(間)パーミュテーションは符号語を構成するN個の巡回ブロックの並び順を換えるパーミュテーションであり、巡回ブロック内パーミュテーションは巡回ブロックを構成するQ個のビットの並び順を換えるパーミュテーションであり、カラム‐ロウパーミュテーションは、セクションを構成するM×Q個のビットの並び順を換えるパーミュテーションである。
p(b=0)はビットbが0である確率を示し、p(b=1)はビットbが1である確率を示す。ただし、p(b=0)+p(b=1)=1が成り立つ。
≪発明者によるさらなる検討≫
上述した条件1、条件2を満たすインターリーバ(並列インターリーバ)では、コンステレーション語のビット数Mが巡回ブロック数Nの約数になることを前提としている。しかしながら、常に、MがNの約数になるとは限らない。例として、DVB-T2規格で使用される16K LDPC符号を挙げることができ、16K LDPC符号の符号語はN=45個の巡回ブロックを有する。MがNの約数にならない場合、Mが偶数であるQAMコンステレーションなどの正方形コンステレーションに対するマッピングは容易ではない。
特に、実施の形態に係るビットインターリーブ方法は、疑似巡回低密度パリティチェック符号を用いた通信システムにおけるビットインターリーブ方法であって、前記ビットインターリーブ方法は、それぞれがQ個のビットからなるN個の巡回ブロックで構成される前記疑似巡回低密度パリティチェック符号の符号語を受信する受信ステップと、前記符号語のビットに対して当該符号語のビットの並び順を換えるビットパーミュテーション処理を施すビットパーミュテーションステップと、前記ビットパーミュテーション処理が施された符号語を、それぞれがM個のビットよりなり、それぞれが2M個の所定のコンステレーションポイントのいずれか1つを示す複数のコンステレーション語に分割する分割ステップと、を有し、N個の巡回ブロックの中から、M(Mはコンステレーション語あたりのビット数である。)の倍数となるN’個の巡回ブロックのサブセットを選択する選択ステップと、前記ビットパーミュテーション処理が施される前の前記符号語はN’/M個のセクションに分割され、各前記セクションはM個の前記巡回ブロックからなり、各前記コンステレーション語は、前記N’/M個のセクションのうちの一つと関連付けられており、前記ビットパーミュテーションステップは、各前記コンステレーション語が、関連付けられている前記セクション中のM個の異なる前記巡回ブロックのそれぞれの1個のビットからなる計M個のビットから構成され、各前記セクションのすべてのビットが当該セクションに関連付けられているQ個の前記コンステレーション語にのみにマッピングされるように、前記ビットパーミュテーション処理を行うことを特徴とする。
同様に、実施の形態に係るビットインターリーバは、疑似巡回低密度パリティチェック符号を用いる通信システムにおけるビットインターリーバであって、前記ビットインターリーバは、それぞれがQ個のビットからなるN個の巡回ブロックで構成される前記疑似巡回低密度パリティチェック符号の符号語を受信し、前記符号語のビットに対して当該符号語のビットの並び順を換えるビットパーミュテーション処理を施し、前記ビットパーミュテーション処理が施された符号語を、それぞれがM個のビットよりなり、それぞれが2M個の所定のコンステレーションポイントのいずれか1つを示す複数のコンステレーション語に分割されるように出力するビットパーミュテーション部と、N個の巡回ブロックの中から、M(Mはコンステレーション語あたりのビット数である。)の倍数となるN’個の巡回ブロックのサブセットを選択する選択部と、を備え、前記ビットパーミュテーション処理が施される前の前記符号語はN’/M個のセクションに分割され、各前記セクションはM個の前記巡回ブロックからなり、各前記コンステレーション語はN’/M個の前記セクションのうちのいずれか1つと関連付けられており、前記ビットパーミュテーション部は、各前記コンステレーション語が、関連付けられている前記セクション中のM個の異なる前記巡回ブロックのそれぞれの1個のビットからなる計M個のビットから構成され、各前記セクションのすべてのビットが当該セクションに関連付けられているQ個の前記コンステレーション語にのみにマッピングされるように、前記ビットパーミュテーション処理を行うことを特徴とする。
また、前記符号語のビットは、前記選択された前記N’個の巡回ブロックのサブセットに含まれず、ビットの並び順を換える対象とされないままにされるビット群、または、前記選択された前記N’個の巡回ブロックのサブセットに含まれず、選択されなかった巡回ブロックのみに適用される、前記ビットパーミュテーション処理からは独立したビットの並び順を換える対象となるビット群を含むとしても構わない。
例えば、除外される巡回ブロックは、変数ノードの重みが最も小さい巡回ブロックであってもよい。RA QC LDPC符号(図5参照)の場合、例えば、除外される巡回ブロックは、バリティ部分(重み2の変数ノードを有する)の巡回ブロックであってもよく、この場合、例えば符号語の最後から1以上の巡回ブロックであってもよい。
また、前記選択ステップは、各巡回ブロックに含まれるビットの重要度に基づいて、前記巡回ブロックを選択するとしても構わない。
また、選択されたN’個の巡回ブロックのサブセットは、符号語の最初のビットを有する巡回ブロックから連続するN’個のブロックにより構成されるとしても構わない。
図30は、実施の形態(その1)で説明したインターリーブ方法を適用する適用対象の巡回ブロックと適用しない適用対象外の巡回ブロック(除外される巡回ブロック)を示す図である。但し、図30は、符号がDVB-T2規格で定義されている16K LDPC符号であり、コンステレーションが16QAMコンステレーションである場合に対する図である。図30の例では、適用対象の巡回ブロックは44個の巡回ブロック(1、・・・、44)であり、適用対象外の巡回ブロック(除外される巡回ブロック)はその最終行の1個の巡回ブロック45のみである。また、4個の黒四角が1番目のコンステレーション語の4ビットを表す。
各コンステレーション語のM個のビットが、LDPC符号語のM/F個の異なる巡回ブロックにマッピングされる。これは、LDPC符号語のM/F個の異なる巡回ブロックからF個のビットずつコンステレーション語にマッピングする、ことと等価である。この概要を図31(a)に示す。
M/F個の巡回ブロックにマッピングされるすべてのコンステレーション語が、当該M/F個の巡回ブロックのみにマッピングされる。これは、QビットからなるM/F個の異なる巡回ブロックのM×Q/F個のビットの全ては、Q/F個のコンステレーション語にのみマッピングされる、ことと等価である。この概要を図31(b)に示す。
以下、上記の条件1A、条件2Aを満たすビットインターリーバ(並列ビットインターリーバ)の詳細について説明する。なお、以下において、実質的に同じ処理内容、および、同じ処理内容を行う構成ユニットには同じ符号を付す。
以下、NがMの倍数ではなく、フォルディングを行う場合のインターリーバの一例について記載する。
以下、表3で説明したDVB-T2規格で用いられるLDPC符号に対する、セクションパーミュテーションの具体例について説明する。
(例1A)N=45,Q=360,M=4,フォルディングなし(F=1)の場合
図44(a)は、N=45,Q=360,M=4でフォルディングなし(F=1)の場合の、セクションパーミュテーションの構造を示す図である。
(例1B)N=45,Q=360,M=4でフォルディングあり(F=2)の場合
図44(b)は、N=45,Q=360,M=4でフォルディングあり(F=2)の場合の、セクションパーミュテーションの構造を示す図である。
図45(a)は、N=45,Q=360,M=6でフォルディングなし(F=1)の場合の、セクションパーミュテーションの構造を示す図である。
図45(b)は、N=45,Q=360,M=6でフォルディングあり(F=2)の場合の、セクションパーミュテーションの構造を示す図である。
本発明は上記の実施の形態で説明した内容に限定されず、本発明の目的とそれに関連又は付随する目的を達成するためのいかなる形態においても実施可能であり、例えば、以下であってもよい。
本発明に係るインターリーブ方法、インターリーバ、デインターリーブ方法、デインターリーバ、およびデコーダとその効果について説明する。
2010A ビットパーミュテーションユニット
2021A フォルディングセクションパーミュテーションユニット
2131A、2132A カラム‐ロウパーミュテーションユニット
2500A トランスミッタ
2510 LDPCエンコーダ
2520A ビットインターリーバ
2530 コンステレーションマッパ
2700A、2800A レシーバ
2710 コンステレーションデマッパ
2720A ビットデインターリーバ
2730 LDPCデコーダ
2740 減算ユニット
2750A ビットインターリーバ
Claims (13)
- 疑似巡回低密度パリティチェック符号を用いる通信システムにおけるビットインターリーブ方法であって、
前記ビットインターリーブ方法は、
それぞれがQ個のビットからなるN個の巡回ブロックで構成される前記疑似巡回低密度パリティチェック符号の符号語を受信する受信ステップと、
前記符号語のビットに対して当該符号語のビットの並び順を換えるビットパーミュテーション処理を施すビットパーミュテーションステップと、
前記ビットパーミュテーション処理が施された符号語を、それぞれがM個のビットよりなり、それぞれが2M個の所定のコンステレーションポイントのいずれか1つを示す複数のコンステレーション語に分割する分割ステップと、
を有し、
N個の巡回ブロックの中から、M/F(Mはコンステレーション語あたりのビット数であり、FはMの約数である。)の倍数となるN’個の巡回ブロックのサブセットを選択する選択ステップと、
前記ビットパーミュテーション処理が施される前の前記符号語はF×N’/M個のフォルディングセクションに分割され、各前記フォルディングセクションはM/F個の前記巡回ブロックからなり、各前記コンステレーション語は、前記F×N’/M個のフォルディングセクションのうちの一つと関連付けられており、
前記ビットパーミュテーションステップは、各前記コンステレーション語が、関連付けられている前記フォルディングセクション中のM/F個の異なる前記巡回ブロックのそれぞれのF個のビットからなる計M個のビットから構成され、各前記フォルディングセクションのすべてのビットが当該フォルディングセクションに関連付けられているQ個の前記コンステレーション語にのみにマッピングされるように、前記ビットパーミュテーション処理を行うことを特徴とするビットインターリーブ方法。
- 前記符号語のビットは、
前記選択された前記N’個の巡回ブロックのサブセットに含まれず、ビットの並び順を換える対象とされないままにされるビット群、
または、
前記選択された前記N’個の巡回ブロックのサブセットに含まれず、選択されなかった巡回ブロックのみに適用される、前記ビットパーミュテーション処理からは独立したビットの並び順を換える対象となるビット群
を含むことを特徴とする請求項1に記載のビットインターリーブ方法。
- 前記選択された巡回ブロックの個数N’は、M/FをF×N/M以下の最大の整数倍した数である
ことを特徴とする請求項1に記載のビットインターリーブ方法。
- 前記選択ステップは、各巡回ブロックに含まれるビットの重要度に基づいて、前記巡回ブロックを選択する
ことを特徴とする請求項1に記載のビットインターリーブ方法。
- 前記各巡回ブロックに含まれるビットの重要度は、関連するパリティビットの数に基づいて決定される
ことを特徴とする請求項4に記載のビットインターリーブ方法。
- 前記符号語は、リピートアキュミュレート疑似巡回低密度パリティチェック符号であって、前記選択されなかった巡回ブロックは、符号語のパリティセクションに対応する
ことを特徴とする請求項1に記載のビットインターリーブ方法。
- 選択されたN’個の巡回ブロックのサブセットは、符号語の最初のビットを有する巡回ブロックから連続するN’個のブロックにより構成される
ことを特徴とする請求項1に記載のビットインターリーブ方法。
- 前記セクションパーミュテーションステップは、前記巡回ブロックのQ個のビットが、当該巡回ブロックに対応する前記フォルディングセクションに関連付けられているQ個の前記コンステレーション語の同一のビットインデックスを有するビットにマッピングされるように、前記セクションパーミュテーション処理を行う
ことを特徴とする請求項1に記載のビットインターリーブ方法。
- 疑似巡回低密度パリティチェック符号を用いる通信システムにおいてビットストリームをデインターリーブするデインターリーブ方法であって、
N×Q個のビットからなるビット列を受信する受信ステップと、
前記疑似巡回低密度パリティチェック符号の符号語を復元するために、受信した前記ビット列のビットに対して当該ビット列のビットの並び順を換える逆ビットパーミュテーション処理を施す逆ビットパーミュテーションステップと、
を有し、
前記逆ビットパーミュテーション処理は、請求項1に記載のビットインターリーブ方法における前記ビットパーミュテーション処理で換えられた並び順を元に戻す処理である
ことを特徴とするデインターリーブ方法。
- 疑似巡回低密度パリティチェック符号を用いる通信システムにおけるビットインターリーバであって、
前記ビットインターリーバは、
それぞれがQ個のビットからなるN個の巡回ブロックで構成される前記疑似巡回低密度パリティチェック符号の符号語を受信し、前記符号語のビットに対して当該符号語のビットの並び順を換えるビットパーミュテーション処理を施し、前記ビットパーミュテーション処理が施された符号語を、それぞれがM個のビットよりなり、それぞれが2M個の所定のコンステレーションポイントのいずれか1つを示す複数のコンステレーション語に分割されるように出力するビットパーミュテーション部と、
N個の巡回ブロックの中から、M/F(Mはコンステレーション語あたりのビット数であり、FはMの約数である。)の倍数となるN’個の巡回ブロックのサブセットを選択する選択部と、
を備え、
前記ビットパーミュテーション処理が施される前の前記符号語はF×N’/M個のフォルディングセクションに分割され、各前記フォルディングセクションはM/F個の前記巡回ブロックからなり、各前記コンステレーション語はF×N’/M個の前記フォルディングセクションのうちのいずれか1つと関連付けられており、
前記ビットパーミュテーション部は、各前記コンステレーション語が、関連付けられている前記フォルディングセクション中のM/F個の異なる前記巡回ブロックのそれぞれのF個のビットからなる計M個のビットから構成され、各前記フォルディングセクションのすべてのビットが当該フォルディングセクションに関連付けられているQ個の前記コンステレーション語にのみにマッピングされるように、前記ビットパーミュテーション処理を行う
ことを特徴とするビットインターリーバ。
- 疑似巡回低密度パリティチェック符号を用いる通信システムにおいてビットストリームをデインターリーブするデインターリーバであって、
N×Q個のビットからなるビット列を受信し、前記疑似巡回低密度パリティチェック符号の符号語を復元するために、受信した前記ビット列のビットに対して当該ビット列のビットの並び順を換える逆ビットパーミュテーション処理を施す逆ビットパーミュテーション部を備え、
前記逆ビットパーミュテーション処理は、請求項10に記載のビットインターリーバによって実施される前記ビットパーミュテーション処理で換えられた並び順を元に戻す処理である
ことを特徴とするデインターリーバ。
- 疑似巡回低密度パリティチェック符号を用いるビットインターリーブ符号化変調システム用のデコーダであって、
対応するビットが0であるか1であるかの確率を示すソフトビット列を生成するコンステレーションデマッパと、
前記ソフトビット列をデインターリーブする請求項11に記載のデインターリーバと、
デインターリーブされた前記ソフトビット列をデコードする低密度パリティチェックデコーダと、
を備えることを特徴とするデコーダ。
- 前記低密度パリティチェックデコーダの出力から前記低密度パリティチェックデコーダの入力を減算する減算部と、
前記減算部の減算結果を前記コンステレーションデマッパにフィードバックする請求項10に記載のビットインターリーバと、
をさらに備えることを特徴とする請求項12に記載のデコーダ。
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JP7080933B2 (ja) | 2014-03-14 | 2022-06-06 | サムスン エレクトロニクス カンパニー リミテッド | インターリービング深度を調整するための装置及び方法 |
JP2022116176A (ja) * | 2014-03-14 | 2022-08-09 | サムスン エレクトロニクス カンパニー リミテッド | インターリービング深度を調整するための装置及び方法 |
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