WO2012139261A1 - 本导体器件及其制造方法 - Google Patents
本导体器件及其制造方法 Download PDFInfo
- Publication number
- WO2012139261A1 WO2012139261A1 PCT/CN2011/001314 CN2011001314W WO2012139261A1 WO 2012139261 A1 WO2012139261 A1 WO 2012139261A1 CN 2011001314 W CN2011001314 W CN 2011001314W WO 2012139261 A1 WO2012139261 A1 WO 2012139261A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- gate stack
- substrate
- epitaxial layer
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 77
- 239000000463 material Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910010038 TiAl Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 239000007769 metal material Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- -1 one of SiOF Chemical compound 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method of fabricating the same. Background technique
- a semiconductor device (such as a transistor) including a source region and a drain region is a contact structure of a commonly required electrical connection in an integrated circuit and is one of important components in the circuit.
- Figure 1 shows an example of a prior art contact structure.
- a contact structure 130 is formed on a source region and a drain region of a semiconductor device including a gate, a source region, and a drain region.
- the top 131 of the contact structure is larger than the bottom 133 thereof.
- Such a contact structure has the following problems. Since the bottom of the contact structure is small, the contact area of the contact structure with the source and drain regions is small, and as the size of the semiconductor device is gradually reduced, the influence on the contact resistance is gradually increased. Moreover, the distance between the top of such a contact structure and the top of the gate of the semiconductor device is small, which increases the likelihood of a short between the contact structure and the gate. Summary of the invention
- a semiconductor device including a gate stack, a source region, a drain region, a contact plug, and an interlayer dielectric, the gate stack being formed on a substrate, the source region and the drain region Located on both sides of the gate stack and embedded in the substrate, the contact plug In the interlayer medium, wherein the contact plug includes a first portion, the contact plug is connected to the source region and/or the drain region with the first portion, the first portion The upper surface is flush with the upper surface of the gate stack, and the angle between the sidewall of the first portion and the bottom wall is less than 90°.
- the angle between the side wall of the first portion and the bottom wall is less than 90°, so that the top of the first portion can be smaller than the bottom portion thereof.
- the semiconductor device including the first portion has a smaller top area and a larger bottom area than other semiconductor devices of the same size. Therefore, the contact area of the first portion with the source region and/or the drain region can be increased to facilitate reducing the contact resistance; and the distance between the top of the first portion and the top of the gate stack can be increased. It is beneficial to reduce the possibility of short circuit between the first portion and the gate stack.
- a method of fabricating a semiconductor device including:
- the contact hole is filled with a conductive material.
- the epitaxial layer is formed by a facet epitaxial process on a source region and/or a drain region formed on the (100) substrate such that an angle between a sidewall of the epitaxial layer and a bottom wall thereof is less than 90.
- the semiconductor device including the first portion has a smaller top area and a larger bottom area than other semiconductor devices of the same size.
- the contact area of the first portion with the source region and/or the drain region can be increased to reduce the contact resistance; and the distance between the top of the first portion and the top of the gate stack can be increased. It is beneficial to reduce the possibility of short circuit between the first portion and the gate stack.
- Figure 1 shows a schematic cross-sectional view of a prior art contact structure.
- Fig. 2 shows a cross-sectional schematic view of a semiconductor device in accordance with an exemplary embodiment of the present invention.
- FIG. 3A illustrates a first step of fabricating a semiconductor device by which an epitaxial layer is formed in accordance with an exemplary embodiment of the present invention.
- FIG. 3B illustrates a second step of fabricating a semiconductor device in which an interlayer dielectric is formed in accordance with an exemplary embodiment of the present invention.
- FIG. 3C illustrates a third step of fabricating a semiconductor device by which a planarized interlayer dielectric is formed in accordance with an exemplary embodiment of the present invention.
- a contact hole is formed in this step.
- the fifth step through which the contact layer is formed.
- Fig. 3F shows a sixth step of fabricating a semiconductor device in which a contact hole is filled with a conductive material in accordance with an exemplary embodiment of the present invention.
- the seventh step in which a flattened first portion is formed.
- a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG.
- a first portion 280 of a contact plug 230 in accordance with an exemplary embodiment of the present invention is formed on a source region 241 and/or a drain region 242 of a semiconductor device.
- FIG. 2 shows that the first portion 280 is formed on both the source region 241 and the drain region 242 of the semiconductor device, as is known to those skilled in the art, the first portion 280 may be formed only at the source as needed.
- the first portion 280 material may be a first metal material (ie, a metal layer).
- the first metal material may include, but is not limited to, a material or a combination of materials selected from the group consisting of: W, Al, TiAl, Cu o
- the outer portion of the first portion 280 may be provided with a liner (ie barrier layer, not shown).
- the liner is formed from a second metallic material.
- the second metallic material may include, but is not limited to, a material or combination of materials selected from the group consisting of Ti, TiN, Ta, TaN, or Ru.
- the top portion of the first portion 280 is smaller than the bottom portion thereof. Since the bottom portion of the first portion 280 has a large area, it is advantageous to reduce the contact resistance between the first portion 280 and the source region 241 and the drain region 242 of the semiconductor device.
- the upper surface of the first portion 280' is flush with the upper surface of the gate stack 210 (in this document, the term "flush" means that the height difference between the two is in the process.
- the side wall of the first portion 280 is less than 90° from the bottom wall thereof. In particular, the angle between the side wall of the first portion 280 and the bottom wall may range from 50° to 60°.
- a semiconductor device 200 includes: a substrate 201; a gate stack 210 formed on a substrate 201; and a source region 241 in the bottom of each of the gate stacks 210 And a drain region 242; a first portion 280 of the contact plug 230 formed on at least one of the source region 241 and the drain region 242; and an interlayer dielectric 260 in which the contact plug 230 is embedded.
- ⁇ "Bottom 201 can be silicon or germanium, silicon-on-insulator (SOI) or silicon-on-insulator, or any semiconductor material formed on a semiconductor substrate, such as SiC, etc., or even III-V a compound semiconductor (such as GaAs, InP, etc.) or a II-VI compound semiconductor (such as ZnSe, ZnS) or the like.
- the gate stack 210 may include a gate dielectric 211 and a gate dielectric 211 Gate electrode 212.
- the gate stack 210 further includes a spacer spacer 220 (the spacer, the spacer spacer may be a single layer or a multi-layer structure, and when the sidewall spacer is a multi-layer structure, adjacent layers
- the material may be different, in other embodiments, the sidewall spacers may also be included, which are disposed on the sidewalls of the gate dielectric 211 and the gate electrode 212.
- the gate dielectric 211 may be made of silicon oxide, silicon oxynitride or a high-k dielectric material (eg, ⁇ 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO).
- a high-k dielectric material eg, ⁇ 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO.
- the gate electrode 212 may be formed of a conductive material such as a metal or a doped semiconductor material, a doped semiconductor material such as doped polysilicon.
- the source region 241 and the drain region 242 may be formed by an ion implantation process (injecting doping particles into the substrate 201) or by first forming trenches on both sides of the gate stack 210 and then epitaxially growing the semiconductor material on the exposed substrate 201, Let me repeat.
- the interlayer dielectric 260 material may be a doped or undoped vitreous silica such as one of SiOF, SiCOH, SiO, SiCO, SiCON, SiON, PSG (phosphorus silicate glass) or BPSG (borophosphosilicate glass) or Its combination.
- the angle between the side wall of the first portion 280 and the bottom wall thereof is less than 90°, so that the top of the first portion 280 can be smaller than the bottom portion thereof.
- the semiconductor device including the first portion 280 has a smaller top area and a larger bottom area than other semiconductor devices of the same size. Therefore, the contact area of the first portion 280 with the source region 241 and/or the drain region 242 can be increased to reduce the contact resistance; and the top of the first portion 280 and the top of the gate stack 210 can also be The increased distance facilitates reducing the likelihood of a short between the first portion 280 and the gate stack 210.
- the first step Through this step, an epitaxial layer is formed. More specifically, as shown in FIG. 3A, a gate stack substrate is formed on the (100) substrate, and a source region 241 and a drain region 242 are formed on both sides of the gate stack substrate, and in the source region and the The epitaxial layer 250 is formed by a faceted epitaxial growth on the drain region such that an angle between the sidewall of the epitaxial layer 250 and the bottom wall thereof is less than 90°.
- the height of the epitaxial layer 250 is less than the height of the gate stack substrate; the components of the gate stack substrate are the same as the foregoing gate stack 210, but differ in height, undergoing subsequent planarization to expose After operation of the epitaxial layer 250 and an optional replacement gate process, the gate stack substrate becomes the gate stack 210.
- the crystal face epitaxial process means that the semiconductor material has a different growth rate in different directions when the semiconductor material is epitaxially grown on the substrate, and the substrate material is (100) silicon as an example, when the semiconductor material is epitaxially grown thereon.
- the semiconductor material has a faster growth rate on (100) and a slower growth rate on (11), which in turn causes the epitaxial layer in the structure shown in Fig. 3 to have an inverted pyramid structure.
- the epitaxial layer 250 material is SiGe, Ge,
- the epitaxial layer 250 may be a single layer or a plurality of layers (in this case, the adjacent two layers of materials are different).
- the second step In this step, an interlayer dielectric 260 is formed. More specifically, the formed interlayer shield 260 covers the epitaxial layer 250 and the gate stack substrate.
- FIG. 3C illustrates a third step of a method of fabricating a semiconductor device in accordance with an exemplary embodiment of the present invention.
- a planarized interlayer dielectric 260 is formed. More specifically, after planarizing the interlayer dielectric 260, the epitaxial layer 250 is exposed. As an example, a chemical mechanical polishing (CMP) process can be utilized to planarize the interlayer dielectric 260.
- CMP chemical mechanical polishing
- the fourth step In this step, a contact hole is formed. More specifically, at least a portion of the height of the epitaxial layer 250 is removed to form a contact hole 251.
- FIG. 3D shows the case where the epitaxial layer 250 is partially removed. In other embodiments, epitaxial layer 250 can also be completely removed.
- removing at least a portion of the height of the epitaxial layer is performed by selective etching, such as the epitaxial layer including a first layer (such as Si) and a second layer (such as SiGe) and the second layer is formed on
- the step of removing at least a portion of the epitaxial layer is to remove the second layer.
- the contact layer 270 may be formed by: first, forming a metal material to cover the bottom wall and the sidewall of the contact hole 251, the metal material may be, for example, a metal material containing Ni, Co or Ti; and then annealing The process is to form a contact layer 270 (such as a metal silicide such as NiSi, CoSi or TiSi); finally, the unreacted metal material is removed.
- the sixth step In this step, the contact hole 251 is filled with a conductive material to form the first portion 280 of the contact plug 230. Wherein, the top area of the first portion 280 is smaller than the bottom area thereof.
- the step of filling the contact hole with a conductive material includes: first, forming a barrier layer covering a sidewall and a bottom wall of the contact hole, the barrier layer material being Ta, TaN, Ti, TiN or Ru One or a combination thereof; Then, a metal layer is formed, and the metal layer is formed on the barrier layer, and the metal layer material is one of W, Al, Cu, TiAl or a combination thereof.
- the first portion 280 is planarized.
- the first portion 280 can be planarized using a chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- an epitaxial layer by a facet epitaxial process on a source region and/or a drain region formed on a (100) substrate such that an angle between a sidewall of the epitaxial layer and a bottom wall thereof is less than 90°
- a contact hole is formed after removing at least a portion of the epitaxial layer, and the contact hole is filled with a conductive material, thereby forming a first portion, and an angle between a sidewall of the first portion and a bottom wall thereof is less than 90. That is, the top of the first portion is made smaller than the bottom thereof.
- the semiconductor device including the first portion has a smaller top area and a larger bottom area than other semiconductor devices of the same size.
- the contact area of the first portion with the source region and/or the drain region can be increased to reduce the contact resistance; and the distance between the top of the first portion and the top of the gate stack can be increased. It is beneficial to reduce the possibility of short circuit between the first portion and the gate stack.
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- Condensed Matter Physics & Semiconductors (AREA)
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Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201190000081.5U CN203205398U (zh) | 2011-04-15 | 2011-08-09 | 半导体器件 |
US13/378,996 US20120261772A1 (en) | 2011-04-15 | 2011-08-09 | Semiconductor Device and Method for Manufacturing the Same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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CN201110094967.7 | 2011-04-15 | ||
CN201110094967.7A CN102738234B (zh) | 2011-04-15 | 2011-04-15 | 半导体器件及其制造方法 |
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Publication Number | Publication Date |
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WO2012139261A1 true WO2012139261A1 (zh) | 2012-10-18 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/CN2011/001314 WO2012139261A1 (zh) | 2011-04-15 | 2011-08-09 | 本导体器件及其制造方法 |
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CN (2) | CN102738234B (zh) |
WO (1) | WO2012139261A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN106206584A (zh) * | 2015-04-29 | 2016-12-07 | 华邦电子股份有限公司 | 存储元件及其制造方法 |
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JP2001308323A (ja) * | 2000-04-26 | 2001-11-02 | Hitachi Ltd | 半導体装置の製造方法 |
JP2005236201A (ja) * | 2004-02-23 | 2005-09-02 | Renesas Technology Corp | 半導体装置及びその製造方法 |
CN101047145A (zh) * | 2006-03-30 | 2007-10-03 | 京东方科技集团股份有限公司 | 一种制备有源驱动tft矩阵中金属连线的方法 |
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US6054768A (en) * | 1997-10-02 | 2000-04-25 | Micron Technology, Inc. | Metal fill by treatment of mobility layers |
TW497120B (en) * | 2000-03-06 | 2002-08-01 | Toshiba Corp | Transistor, semiconductor device and manufacturing method of semiconductor device |
US20050085072A1 (en) * | 2003-10-20 | 2005-04-21 | Kim Hyun T. | Formation of self-aligned contact plugs |
JP2007158176A (ja) * | 2005-12-07 | 2007-06-21 | Hitachi Ltd | 半導体記憶装置およびその製造方法 |
JP2008004894A (ja) * | 2006-06-26 | 2008-01-10 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US7652335B2 (en) * | 2007-10-17 | 2010-01-26 | Toshiba America Electronics Components, Inc. | Reversely tapered contact structure compatible with dual stress liner process |
CN102024744B (zh) * | 2009-09-16 | 2013-02-06 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
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2011
- 2011-04-15 CN CN201110094967.7A patent/CN102738234B/zh active Active
- 2011-08-09 WO PCT/CN2011/001314 patent/WO2012139261A1/zh active Application Filing
- 2011-08-09 CN CN201190000081.5U patent/CN203205398U/zh not_active Expired - Fee Related
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JP2001308323A (ja) * | 2000-04-26 | 2001-11-02 | Hitachi Ltd | 半導体装置の製造方法 |
JP2005236201A (ja) * | 2004-02-23 | 2005-09-02 | Renesas Technology Corp | 半導体装置及びその製造方法 |
CN101047145A (zh) * | 2006-03-30 | 2007-10-03 | 京东方科技集团股份有限公司 | 一种制备有源驱动tft矩阵中金属连线的方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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CN106206584A (zh) * | 2015-04-29 | 2016-12-07 | 华邦电子股份有限公司 | 存储元件及其制造方法 |
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CN203205398U (zh) | 2013-09-18 |
CN102738234B (zh) | 2016-09-07 |
CN102738234A (zh) | 2012-10-17 |
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